Conventional acid electroplated copper is being widely used in semiconductor industries from back-end-of-the-line (BEOL) interconnects to advanced packaging applications such as copper pillar, redistribution layer (RDL) copper and Through Silicon Via ( TSV) because of low cost, easy manufacturing process and high throughput[1-3]. Industry trends towards higher performance semiconductor devices with increased interconnect density have created significant materials challenges for advanced electronics packaging metallization processes. Copper pillar becomes a transformative technology replacing traditional C4 (controlled collapse chip connection) bumps to meet new performance demands. Copper pillar chemistry requires innovative organic additives in order to meet challenges such as flat pillar shape, void-free intermetallic interface after reflow with solder, fast plating speed, high purity deposits and excellent uniformity. Copper plating baths may contain at least one or three of the additives: accelerator, suppressor, and leveler. Accelerator is usually used to enhance plating rate (depolarization agent) just as its name indicates, while suppressor and leveler are polarization agents that inhibit the plating locally. Although all the additives can be defined as either polarization or depolarization agents, depending on the electrochemical response, the function of each additive could be very different depending on the application. In this talk, the additive function in three different electroplating applications, Dual Damascene, TSV, and copper pillar, will be compared. Then we will introduce the development of Dow Electronic Materials’ next-generation copper pillar chemistry. Additives, current density and process impact on plating performance will be discussed. E. Reddington, M. Thorseth, Y. Qin, J. Woertink, R. Farrell, M. Scalisi, E. Banelis, P. Lopez-Montesinos, B. Sherzer, Z. Baumer, W. Tachikawa, J. dong, M. Lefebvre, J. Calvert, International Wafer Level Packaging Conference (IWLPC), 2014, San JoseT. P. Moffat, D. Wheeler, M.D. Edelstein, D. Josell, IBM J. RES. & DEV. 49, 2005, 19-36M. Thorseth, M. Scalisi, I. Lee, S. Park, Y. Lee, J. Prange, M. Imanari, M. Lefebvre, J. Calvert, 12th International Microelectronics Assembly and Packaging Society (IMAPS), 2016, Arizona