Plastic Quad Flat Pack Research Articles

Study on reliability of PQFP assembly with lead free solder joints under random vibration test

Harsh solder joint reliability testing is needed for high frequency vibration requirements particularly for automotive electronics. In this study, the solder joint reliability for the plastic quad flat package (PQFP) which was mounted on the printed circuit board (PCB) using 95.5Sn–3.8Ag–0.7Cu lead-free solder was investigated using the random vibration test. A high-speed camera was used to capture dynamic response of the PCB and PQFP lead during the random vibration test. The displacement measurement result was used in finite element analysis (FEA) as an input displacement loading to evaluate the stress–strain behavior of the PQFP lead and solder joint. Fatigue life prediction for the copper (Cu) lead and PQFP solder joint was carried out using three different cycle-counting methods and the Miner's law. It was shown that solder fatigue failure is more critical than Cu lead failure for the PQFP assembly under the random vibration test.

In Situ Chip Stress Extractions for LFBGA Packages Through Piezoresistive Sensors

Piezoresistive sensors have been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, test chips with piezoresistive stress sensors, diode temperature sensors as well as heaters were first designed, fabricated, and calibrated. We next packaged the test chips into low profile, fine pitch ball grid array (LFBGA) packaging with 196 balls and measured the stresses on chip surfaces inside the packaging. After measuring the packaging induced stress as well as the stress under stable environmental temperature rises, it was found that compressive stresses were obtained at room temperature, and the stresses were relaxed as temperature went up at a rate between 0.45 MPa/°C and 0.60 MPa/°C. For thermo-stress experiments, the temperatures on chip surfaces at different power levels were measured, and compressive chip stresses were first extracted. As the chip power increased, the compressive stresses became tensions. Since the LFBGA structure is thinner with higher packaging efficiency, different results from our earlier plastic quad flat package stress measurements were observed and discussed. In addition, the final comparisons between the experimental data and the finite element simulations show good consistency.

Fault prognosis technology for solder joints based on time stress and hidden Markov models

The main external factor of solder joints degradation or deviation from an expected normal condition is the time stress such as work and environment stresses.A damage assessment method for solder joints based on time stress monitoring and three-dimensional finite element model is introduced.A damage-fault evolution model of solder joints based on hidden Markov mod- els (HMM) is put forward.And then,the fault prognosis technology of the solder joints is researched based on the HMM model, real-time damage information and life consumption prognosis method.The detailed process and algorithm of the fault prognosis technology are studied based on time stress monitoring.Finally,the validity of the technology is proved by an experimental study of plastic quad flat package (PQFP) solder joints.

Fatigue Prediction of Electronic Packages Subjected to Random Vibrations

In modern automotive control modules, mechanical failures of surface-mounted electronic components such as microprocessors, crystals, capacitors, inductors, transformers, ball grid array packages (BGA), quad flat packages (QFP), and chip-scale packages (CSP) are major road blocks in the design cycle and reliability of the product. This paper presents a general approach for failure analysis and fatigue prediction of electronic component like QFPs under automotive vibration environments. The mechanical performance of this package was studied through a finite element modeling approach for a given vibration environment in an automotive application. The vibration simulation provides system characteristics such as modal shapes, modal frequencies, and dynamic responses, including displacements and stresses. By using the results of vibration simulation, fatigue life is predicted based on Miner's cumulative damage ratio and the three-band technique. Detailed (local) model of the lead wire joint is built to correlate the system level model to obtain solder stresses. On the test vehicle, a 160-pin gull-wing lead plastic QFP was chosen to illustrate this approach for failure analysis and fatigue life prediction. From the analysis, it was found that the life used up by the lead wires was 11.6% of the 4-h vibration test.

Transient cooling of electronics using phase change material (PCM)-based heat sinks

Use of a phase change material (PCM)-based heat sink in transient thermal management of plastic quad flat package (QFP) electronic devices was investigated experimentally and numerically. Results show that increased power inputs enhance the melting rate as well as the thermal performance of the PCM-based heat sinks until the PCM is fully melted. A three-dimensional computational fluid dynamics model was proposed to simulate the problem and demonstrated good agreement with experimental data. Results indicate the potential for PCM-based heat sinks for use in intermittent-use devices.

Drop impact reliability testing for lead-free and lead-based soldered IC packages

Board-level drop impact testing is a useful way to characterize the drop durability of the different soldered assemblies onto the printed circuit board (PCB). The characterization process is critical to the lead-free (Pb-free) solders that are replacing lead-based (Pb-based) solders. In this study, drop impact solder joint reliability for plastic ball grid array (PBGA), very-thin quad flat no-lead (VQFN) and plastic quad flat pack (PQFP) packages was investigated for Pb-based (62Sn–36Pb–2Ag) and Pb-free (Sn–4Ag–0.5Cu) soldered assemblies onto different PCB surface finishes of OSP (organic solderability preservative) and ENIG (electroless nickel immersion gold). The Pb-free solder joints on ENIG finish revealed weaker drop reliability performance than the OSP finish. The formation of the brittle intermetallic compound (IMC) Cu–Ni–Sn has led to detrimental interfacial fracture of the PBGA solder joints. For both Pb-based and Pb-free solders onto OSP coated copper pad, the formation of Cu 6Sn 5 IMC resulted in different failure sites and modes. The failures migrated to the PCB copper traces and resin layers instead. The VQFN package is the most resistant to drop impact failures due to its small size and weight. The compliant leads of the PQFP are more resistant to drop failures compared to the PBGA solder joints.

Prediction of electronic component-board transient conjugate heat transfer

Numerical analysis of electronic component transient heat transfer has generally been confined to nonconjugate methods. This study discusses the need for conjugate (conduction/convection) analysis, both for component temperature and thermo-mechanical behavior prediction in operational, assembly and reliability qualification environments. The capability of computational fluid dynamics (CFD) analysis to predict component transient conjugate heat transfer is investigated using an industry-standard CFD code for the thermal analysis of electronics. The test cases are based on a single board-mounted, 160-lead plastic quad flat pack (PQFP) component, subjected to dynamic power- and air temperature conditions, in still-air and forced airflows. Benchmark criteria are based on component junction temperature and component-printed circuit board (PCB) surface temperature, measured using thermal test dies and infrared thermography respectively. Using both nominal component/PCB geometry dimensions and material properties, component junction temperature is found to be accurately predicted. The results suggest that CFD analysis could play an important role in providing critical boundary conditions for component electrical performance and thermo-mechanical behavior analyses, optimizing accelerated life test (ALT) parameters and convective assembly processes.

Application of numerical analysis to the optimisation of electronic component reliability screening and assembly processes

This study investigates the prediction of transient board-mounted electronic component heat transfer in environments representative of reliability screening and surface-mount assembly processes using computational fluid dynamics (CFD) analysis. The test cases are based on a board-mounted 160-lead Plastic Quad Flat Pack (PQFP) component, analysed in still-air and a range of forced airflows. For reliability screening, three types of transient operating conditions are considered, namely (i) component dynamic power dissipation in fixed ambient conditions, (ii) passive component operation in dynamic ambient conditions, and (iii) combined component dynamic power dissipation in varying ambient conditions. For surface-mount assembly, the test vehicle is exposed to a typical solder reflow thermal profile. Benchmark criteria are based on component junction temperature and component-printed circuit board (PCB) surface temperature, measured using thermal test dies and infrared thermography, respectively. Component/PCB numerical modelling is based on nominal geometry dimensions and material properties. Overall, component transient thermal behaviour is found to be accurately predicted, suggesting that CFD analysis could play an important role in providing critical boundary conditions to determine accelerated life testing parameters and optimise new assembly processes.

A study of delamination growth in the die-attach layer of plastic IC packages under hygrothermal loading during solder reflow

This paper describes a comprehensive numerical study of the effects of many parameters on the propagation of delaminations in the die-attach layer using a finite element linear elastic fracture mechanics approach. An 80-pin plastic quad flat package of dimensions 20 mm/spl times/14 mm/spl times/2.7 mm was considered. The parameters investigated include the coefficient of thermal expansion (CTE) of the die-attach material, the thickness of the die-attach layer, the CTE of the pad material, and the size of the initial delamination (defect). The effect of the location of the initial delamination was studied by considering delaminations at the center, edge, and quarter-point locations along the pad/die-attach interface. The effect of swelling of the encapsulant due to moisture absorption during preconditioning at 85/spl deg/C/85%RH was also considered. The combined effect of the hygrostress and thermal stress developed during solder reflow was obtained by suitably superimposing the respective stress intensity factors. The effect of the pressure of water vapor at the delamination was also investigated and found to be negligible for small delaminations. This study has shown that the propagation of delamination from an initial defect located at the edge of the pad/die-attach interface is unstable. Once delamination propagates, it will continue until the entire interface is completely delaminated.

Simulating package behavior under power dissipation using uniform thermal loading

The thermomechanical behavior of electronic packages under power dissipation is simulated using uniform thermal loading. Two packages are studied, a large periphery leaded plastic quad flat pack (PQFP) package and a more compact plastic ball grid array (PBCA) package, both mounted on a printed circuit board (PCB). Experimentally verified linear elastic finite element models are used to find the displacements at the predicted failure location during power dissipation, and then during uniform thermal loading. The results for the two cases are then analyzed to find correlations between power dissipation levels and equivalent heating temperatures. One use of the results could be to replace power cycling fatigue tests with thermal cycling tests, For the packages studied, the results revealed that very little uniform heating is required to simulate the thermomechanical effects at the failure location resulting from power dissipation. Due to the prestrained state of the packages at room temperature, power dissipation decreases the expansion mismatch while increasing the thermal mismatch between package and PCB.

Thermal Characterization of Electronic Packages Using a Three-Dimensional Fourier Series Solution

The need to accurately predict component junction temperatures on fully operational printed circuit boards can lead to complex and time consuming simulations if component details are to be adequately resolved. An analytical approach for characterizing electronic packages is presented, based on the steady-state solution of the Laplace equation for general rectangular geometries, where boundary conditions are uniformly specified over specific regions of the package. The basis of the solution is a general three-dimensional Fourier series solution which satisfies the conduction equation within each layer of the package. The application of boundary conditions at the fluid-solid, package-board and layer-layer interfaces provides a means for obtaining a unique analytical solution for complex IC packages. Comparisons are made with published experimental data for both a plastic quad flat package and a multichip module to demonstrate that an analytical approach can offer an accurate and efficient solution procedure for the thermal characterization of electronic packages. [S1043-7398(00)01403-1]

MOISTURE ABSORPTION BY ENCAPSULATED MICROCHIP PACKAGES

This paper describes an experimental study that was designed to measure specific mass increases (due to the absorption of moisture) that occurred in selected pre-dried plastic encapsulated microchip packages (PEMs) exposed to moist air. Three different types of PEM packages were tested during the course of this work. Two of these PEM types were "dummy" ball grid arrays (BGAs) and plastic leaded chip carriers (PLCCs). The other PEMs tested were "real" metric plastic quad flatpack packages (MQFPs). Moisture absorption isotherms for all of the PEM types were measured at ambient temperatures and at relative humidity (RH) levels very near 50% and 100%. A theoretical method, based upon our experimental results, that could be used to predict moisture absorption behavior between 0 and 100% RH levels (at ambient temperatures) was also described.One result of this study was that nearly 50% of the moisture absorbed by selected pre-dried PEM specimens, during a 50 hr time period, occurred within the first 5 hr of the total exposure time. This fact indicates that even relatively short PEM exposure times, in very high RH environments, can be very serious with regard to the "popcorning" effect that may occur when moisture laden PEMs are reflow soldered onto printed wiring boards. The need to protect pre-dried, moisture sensitive, PEMs in dry air or in dry inert gas environments, prior to any high temperature assembly process, is clearly justified.

Reliable use of commercial technology in high temperature environments

Over 97% of all integrated circuits produced today are available only in plastic encapsulated, surface mountable, commercial grade or industrial grade versions. This is especially true for the most advanced technologies, such as high-speed microprocessors. The cost, availability, and functionality advantages of these devices are causing many electronics manufacturers to consider using them in elevated temperature applications such as avionics and automotive under-hood electronic systems to ensure early affordable access to leading edge technology. However, manufacturers only guarantee the operation of commercial devices in the 0°C to 70°C temperature range, and industrial devices in the −40°C to 85°C temperature range.This paper describes the first study which addresses the reliability of plastic encapsulated microcircuits (PEMs) in the range from 125°C to 300°C, well outside the manufacturer's suggested temperature limits. Previous work has indicated that PEMs sold for use in the commercial and industrial temperature ranges can often operate within the manufacturer's suggested electrical parameter specifications at much higher temperatures. For example, in this study the Motorola MC68332 microcontroller, which is widely used in avionic systems, remained fully functional to 180°C. This is in accordance with previous work that indicated no fundamental constraints to the operation of silicon devices at temperatures up to 200°C. However, this study also revealed that industrial grade, plastic encapsulated MC68332 devices had less than half the lifespan at 180°C than similar MC68332 devices packaged in hermetic ceramic packages. In addition to the MC68332, the other nine types of plastic components studied had a shorter lifespan at 180°C than their ceramic packaged counterparts. Outgassing of flame-retardants with the associated catalysis of the growth of intermetallics was determined to be the principal cause of failure in the plastic components.Further studies conducted on 84-lead plastic quad flatpack (PQFP) leadframes encapsulated in two different molding compounds revealed that the plastic encapsulant itself begins to lose its ability to insulate leads at temperatures greater than 250°C and can actually combust at temperatures greater than 300°C. Both insulation resistance degradation and cracking were found to be more prevalent in novalac than biphenyl. In summary, these studies have shown that while plastic encapsulated microelectronics can operate at temperatures above 125°C, they have less than half the life of ceramic microcircuits at 180°C and they begin to show signs of insulation resistance degradation after 300 hours at 250°C.

Forced Convection Board Level Thermal Design Methodology for Electronic Systems

The case is made for the continued use of single valued thermal resistances for the prediction of component junction temperature, and, hence, reliability. These values are adjusted using empirically determined influence factors to account for thermal and aerodynamic interactions at board level. The paper presents measured values of influence factors for arrays of Plastic Quad Flat Packs (PQFPs) over a range of Reynolds numbers and with a series of board level obstacles modeling upstream passive components. The results are formulated into a novel set of design rules.

Optimal dimension of PQFP by using Taguchi method

This paper addresses the use of finite element techniques and Taguchi method to optimize package design for plastic quad flat packages (PQFP) with and without a heat slug assembled. Warpage in both types of PQFPs during the curing process of temperature changing from 175°C to room temperature was simulated by using three-dimensional finite element models. Taguchi method was applied to both models to isolate the major control factors that minimize package warpage. Results of this analysis suggest that PQFPs without heat slug should keep the thickness of both mold compound and die pad as smaller as possible. For PQFPs with heat slug assembled, it was found that larger Young’s modulus of heat slug material and smaller values of temperature coefficient of expansions of mold compound, die pad, and die attachment would yield the least warpage.

Nonuniform temperature and strain fields in a powered package

This paper analyzes the nonuniform temperature and strain fields resulting from power dissipation in an electronic package. A 208 lead plastic quad flat pack (PQFP) manufactured by Texas Instruments is used to show the temperature distribution and mechanical deformation resulting from power dissipation in the package. The package is tested experimentally and thermally modeled using finite element analysis to obtain the temperature distribution in the active package. The moire interferometry technique is used to acquire displacement contours of an active PQFP and the results are compared to a uniformly heated sample. The results revealed that the thermal loading due to internal power dissipation produces significantly different strains than a uniformly heated sample.

Warpage of Plastic IC Packages as a Function of Processing Conditions

Variation of processing conditions on warpage prediction of a plastic quad flat package (PQFP) is examined. Thermal mismatch between package constituent materials is the major cause of IC package warpage. To minimize the warpage problem, a thorough understanding of epoxy molding compound (EMC) properties with molding parameters is necessary as EMC is epoxy-based with time and temperature dependent viscoelastic properties. This paper first addressed the thermal characterization of encapsulating material. Degree-of-cure (DOC or β), coefficient of thermal expansion (CTE or α), glass transition temperature Tg, and shear modulus G′ and G of the molded specimens were measured by various thermal analysis techniques. The glass transition temperature was shown to be a good and direct measure of the degree-of-cure. The CTEs (α1 and α2),G′ and G″ were found to be decreasing functions of degree-of-cure. Viscoelastic EMC material models with DOC (i.e., Tg) dependent were formulated. Package warpage predictions against different processing conditions were performed via finite element analyses. Out-of-plane displacement measurements were performed on plastic quad flat package (PQFP) to validate the numerical results. Warpage prediction by the viscoelastic material model was found to agree with the measured data better than the thermoelastic one. For a given cured content, less warpage was found in packages molded at low temperature and longer molding time OR high temperature and shorter molding time.

ASSEMBLY OF LARGE PBGAS ON PRINTED CIRCUIT BOARD WITH LARGE PQFPS DIRECTLY ON THE OPPOSITE SIDE

A two-side no-clean mass reflow process for large plastic ball grid array (PBGA) and plastic quad flat pack (PQFP) packages is presented. Emphasis is placed on the PBGA and PQFP assembly parameters such as the design, materials, and process of the packages and printed circuit board (PCB), solder paste, stencil printing, pick and place, reflow, and inspection. Solder joint reliability of the two-side PCB assembly is evaluated by shear tests and thermal cycling tests.

Environmental effects in component packaging selection

Design for environment activities in electronics have been focused on issues of product life-cycle at the board design level and to facility-level process and material choices at the semiconductor fabrication level. An important bridge between these two domains has been the influence of component selection, particularly packaging selection, on environmental impacts. Component packaging influences waste generation in two respects. First, packaging type (i.e. DIP, QFP, BGA, etc.) and size dictates direct production waste in stamping, molding and plating operations. The waste streams from these operations include copper, polymerized thermoset plastic, caustic and acidic effluents and also small traces of silver epoxy. Since many waste components are nonrecyclable and/or have high hazardous content, effective management of direct waste emissions is a critical design task. Second, packaging selection indirectly affects waste generation at the printed circuit board (PCB) level through layout and board sizing decisions. The waste streams from board fabrication include composite scrap (usually glass epoxy), metals (copper foil and dissolved solutions) and catalyst wastes (aqueous photoresist, developer and stripper solutions and hole drilling scrap and tooling). The analysis approach undertaken in this study relies on the development of a toolset of unit process models for packaging manufacturing which develops relationships between package parameters, process parameters and waste outputs. By linking a chain of process models, a mathematical description of a packaging production sequence can be estimated. The models are formulated using the line data collected on plastic quad flat package (PQFP) lines. From the process models, a case comparison of the environmental impacts for two alternative packages for components is developed. Two designs, a design that employs almost all small outline integrated circuits (SOICs) and dual in-line packages (DIPs) (except where lead count necessitates PQFPs) vs. the same design that employs all PQFPs are considered. A case study illustrating the corresponding PCB level impacts due to component packaging selection is also presented. The bare board chosen in both cases is a standard FR4 board.

Validation and application of different experimental techniques to measure electronic component operating junction temperature

Increasing power densities and changing component design have brought about the need for accurate measurement of die junction temperature. While many junction temperature measurement techniques exist it is difficult to compare their relative performance. To validate the accuracy of various direct and indirect test methods, the operating junction temperature of board-mounted SO-16 and plastic quad flat packs (PQFP)-160 components has been recorded using standard thermal test die. Numerical analysis was also used to predict junction temperature and component temperature gradients. The performance of each technique was evaluated for accuracy, ease of use and relevance to real applications, Once accuracy had been validated, two indirect measurement techniques were applied simultaneously to identify the magnitude of localized hot-spots generated by nonuniform power dissipation on the PQFP die.