Plasma-enhanced Chemical Vapor Deposition Oxide Research Articles

Plasma‐Enhanced Chemical‐Vapor‐Deposited SiOx(Ny)/n‐type Polysilicon‐on‐Oxide‐Passivating Contacts in Industrial Back‐Contact Si Solar Cells

In this article, different in situ grown plasma‐enhanced chemical vapor deposition (PECVD)‐grown interfacial oxides for n‐type polysilicon‐passivating contacts are investigated. Herein, SiOx(Ny)/n‐type amorphous silicon stacks created from either N2O plasma or O2 plasma are applied to POLy‐silicon on Oxide interdigitated back‐contact (POLO IBC) solar cells using the structured deposition process through a glass mask to create the IBC layout. The impact of plasma exposure time for interfacial oxide growth on solar cell efficiencies is experimentally determined. In the POLO IBC cell results, it is shown that the PECVD oxides SiOxNy and SiOx with optimized plasma exposure time give similar maximum efficiencies of 23.8% and 23.7%, respectively. In these data, the feasibility to deposit a high‐quality in situ PECVD interfacial SiOx(Ny) layers for surface passivation and current transport of passivated contacts at the same time is demonstrated. For the SiOx/n‐type polysilicon stack, it is found that both plasma exposure time for interfacial oxide growth and polysilicon anneal temperature variations can lead to similar optimum of solar cell efficiencies. The current open‐circuit voltage losses due to metallization for the solar cells are analyzed and a realistic efficiency of 25.22% is calculated to achieve optimized POLO IBC solar cells applying the synergistic efficiency gain analysis on Quokka3 simulations.

Effects of various substrate materials on microstructural and optical properties of amorphous silicon oxynitride thin films deposited by plasma-enhanced chemical vapor deposition

Plasma-enhanced chemical vapor deposition (PECVD) technique is well suited for fabricating optical filters with continuously variable refractive index profiles; however, it is not clear how the optical and microstructural properties of thin films differ when deposited on different substrates. Herein, silicon oxynitride films were deposited on silicon, fused silica, and glass substrates with two stoichiometric ratios by PECVD, using silane, ammonia, and nitrous oxide gasses, to investigate the effects of the substrate used on the optical properties and microstructures of the films. All the deposited films were amorphous. Further, the types and amounts of Si-centered tetrahedral Ox-Si-Ny bonds formed were based upon the substrates and stoichiometric ratios used; Ox-Si-Ny bonds with higher elemental nitrogen content were formed on Si substrates, which lead to obtaining higher refractive indices. The relationship between the surface roughness of the film and type of substrate was discussed. The extinction coefficients of all the films were very small, and the films exhibited low absorption. The refractive indices of the films formed on the different substrates had a maximum difference of 0.03. The deposition rates of the films increased in the order of fused silica, glass, and silicon.

Electrical Characterization of Low Temperature PECVD Oxides for TSV Applications

Abstract In the present work we investigate the quality of low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD) and plasma treated Tetraethyl orthosilicate (TEOS)-based TSV-liner films. Different designs of Trough Silicon Via (TSV) Test structures with 10μm and 20μm width and a depth of 100μm have been fabricated. Two differently doped silicon substrates have been used – highly p-doped and moderately doped. The results for break-through, resistivity and capacitance for the 20μm structures show a better performance compared to the 10μm structures. This is mainly due to increased liner thickness in the reduced aspect ratio case. Lower interface traps and oxide charge densities have been observed in the C-V measurements results for the 10μm structures.

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration.

Plasma- and water-assisted oxide-oxide thermocompression direct bonding for a self-assembly based multichip-to-wafer (MCtW) 3D integration approach was demonstrated. The bonding yields and bonding strengths of the self-assembled chips obtained by the MCtW direct bonding technology were evaluated. In this study, chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PE-CVD) as a MCtW bonding interface was mainly employed, and in addition, wafer-to-wafer thermocompression direct bonding was also used for comparison. N2 or Ar plasmas were utilized for the surface activation. After plasma activation and the subsequent supplying of water as a self-assembly mediate, the chips with the PE-CVD oxide layer were driven by the liquid surface tension and precisely aligned on the host wafers, and subsequently, they were tightly bonded to the wafers through the MCtW oxide-oxide direct bonding technology. Finally, a mechanism of oxide-oxide direct bonding to support the previous models was discussed using an atmospheric pressure ionization mass spectrometer (APIMS).

Design, analysis, and characterization of stress-engineered 3D microstructures comprised of PECVD silicon oxide and nitride

Microelectromechanical systems (MEMS) are typically 2D or quasi-3D structures fabricated using surface and bulk micromachining processes. In this work, an approach for 3D structure fabrication based on stress engineering is demonstrated. Specifically, sub-mm 3D spherical cage-like structures are realized through the deformation of bilayers of residually-stressed silicon oxide and silicon nitride with micrometer-scale thicknesses. Analytical and finite models to predict the shape of stress-engineered structures based on geometry and residual stress are described and used for structure design. A systematic experimental study was performed to quantify residual stresses in silicon nitride films made by plasma-enhanced chemical vapor deposition (PECVD). The measurements show that the residual stress of PECVD silicon nitride can be tuned over a wide range of tensile stresses through the control of deposition parameters, such as flow rate and power. Stress engineered 3D cage-like structures comprised of PECVD silicon nitride and oxide films were fabricated. 3D structures with a range of curvatures were demonstrated. The measured geometry of the fabricated structures are in good agreement with predictions from analytical and finite element models.

Measurements of the refractive indices and thermo-optic coefficients of Si_3N_4 and SiO_x using microring resonances

We present a method for determining the core and cladding refractive indices of a microring resonator from its measured quasi-transverse electric and magnetic resonant modes. We use single wavelength reflective microrings to resolve the azimuthal order ambiguity of the measured resonances. We perform accurate electromagnetic simulations to model the dependence of the resonances on geometrical and material parameters. We linearize the model and use the singular value decomposition method to find the best fit parameters for the measured data. At 1550 nm, we determine n(Si(3)N(4))=1.977±0.003 for stoichiometric silicon nitride deposited using low-pressure chemical vapor deposition (LPCVD) technique and n(SiO(x))=1.428±0.011 for plasma-enhanced chemical vapor deposition (PECVD) oxide. By measuring the temperature sensitivities of microring resonant modes with different polarizations, we find the thermo-optic coefficient of the stoichiometric silicon nitride to be dn(Si(3)N(4))/dT=(2.45±0.09)×10(-5) (RIU/°C) and the PECVD oxide to be dn(SiO(x))/dT=(0.95±0.10)×10(-5) (RIU/°C).

CMOS MEMS capacitive absolute pressure sensor

This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa−1 in the pressure range of 0–300 kPa.

Conformal Deposition of an Insulator Layer and Ag Nano Paste Filling of a Through Silicon Via for a 3D Interconnection

In this study, we reported the feasibility of filling a high-aspect-ratio through silicon via (HARTSV) with Ag nano paste for a 3D interconnection. TSVs with aspect ratios of 8:1 10:1 were fabricated in a deep reactive etching system by using the Bosch process. Then, SiO2 insulators were deposited by using various chemical vapor deposition (CVD) processes, including plasma enhanced CVD oxides, of which precursors were silane (PECVD Oxide) and tetraethoxysilane (PECVDTEOS), and sub-atmospheric CVD oxide (SACVD oxide). We succeeded in obtaining a SiO2 layer with good step coverage over 80% for all via CD sizes by using SACVD oxidation process. The thickness of SiO2 for the via top and the via bottom were in the range 158.8 161.5 nm and 162.6 170.7 nm, respectively. The HAR-TSVs were filled with Ag nano paste by using vacuum assisted paste printing. Then, the samples were cured on a hotplate at 80 C for 2 min. The temperature was increased to 180 C at a rate of 25 C/min and the samples were re-annealed for 2 min. We investigated the eects for the time of evacuation/purge process and of the vacuum drying on the filling properties. A field emission scanning electron microscope (FE-SEM), X-ray microscope and focused ion beam (FIB) microscope were used to investigate the filling profile of the TSV with Ag nano pastes. By increasing the evacuation/purge time and the vacuum drying time, we could fully fill the TSV was full filled with Ag nano paste and then form a metal plug.

High-Aspect-Ratio, Silicon Oxide-Enclosed Pillar Structures in Microfluidic Liquid Chromatography

The present paper discusses the ability to separate chemical species using high-aspect-ratio, silicon oxide-enclosed pillar arrays. These miniaturized chromatographic systems require smaller sample volumes, experience less flow resistance, and generate superior separation efficiency over traditional packed bed liquid chromatographic columns, improvements controlled by the increased order and decreased pore size of the systems. In our distinctive fabrication sequence, plasma-enhanced chemical vapor deposition (PECVD) of silicon oxide is used to alter the surface and structural properties of the pillars for facile surface modification while improving the pillar mechanical stability and increasing surface area. The separation behavior of model compounds within our pillar systems indicated an unexpected hydrophobic-like separation mechanism. The effects of organic modifier, ionic concentration, and pressure-driven flow rate were studied. A decrease in the organic content of the mobile phase increased peak resolution while detrimentally effecting peak shape. A resolution of 4.7 (RSD = 3.7%) was obtained for nearly perfect Gaussian shaped peaks, exhibiting plate heights as low as 1.1 and 1.8 μm for fluorescein and sulforhodamine B, respectively. Contact angle measurements and DART mass spectrometry analysis indicate that our employed elastomeric soft bonding technique modifies pillar properties, creating a fortuitous stationary phase. This discovery provides evidence supporting the ability to easily functionalize PECVD oxide surfaces by gas-phase reactions.

Comparative Study of Thermal Oxides and Post-Oxidized Deposited Oxides on n-Type Free Standing 3C-SiC

The electrical properties of oxides fabricated on n-type 3C-SiC (001) using wet oxidation and an advanced oxidation process combining SiO2 deposition with rapid post oxidation steps have been compared. Two alternative SiO2 deposition techniques have been studied: the plasma enhanced chemical vapor deposition (PECVD) and the low pressure chemical vapor deposition (LPCVD). The post-oxidized PECVD oxide is been demonstrated to be beneficial in terms of interface traps density and reliability.

A fabrication technology for three-dimensional micro total analysis systems

This paper presents a new fabrication technique capable of creating three-dimensional (3D) buried microchannels in a silicon substrate. With a single mask and a single etch of the substrate, silicon microstructures are created with control in all three dimensions by utilizing reactive ion etch (RIE) lag. The microstructures are then sealed with plasma enhanced chemical vapor deposition (PECVD) dielectrics. By depositing up to 6.3 µm of PECVD oxide, rectangular openings in the masking layer ranging in size from 2 µm × 2 µm to 4 µm × 10 µm microchannels were sealed. Using these mask openings, microchannels were created with depths ranging from 4 µm to 200 µm. In addition channels with controlled transition between depths and transition slopes ranging from 40° and 60° were created. Furthermore, the flexibility of this technique allows for the creation of predictable nano-scaled holes on the substrate surface. The entire process is fabricated on silicon and CMOS compatible, thus allowing for 3D buried channel devices to be integrated with microelectronics. To show the impact of this technique, practical microfluidic devices with a wide range of applications are demonstrated.

Direct patterning of plasma enhanced chemical vapor deposition silicon dioxide by electron beam lithography

Hydrogen silsesquioxane (HSQ) is a popular high resolution negative tone resist for electron beam lithography. This work investigates whether a HSQ-like film can be mimicked via plasma enhanced chemical vapor deposition (PECVD) rather than spin coating. It is shown that PECVD oxide acts as mainly a negative tone resist.

The Effect of Gate Oxide Processes on the Performance of 4H-SiC MOSFETs and Gate-Controlled Diodes

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The effect of different gate oxide processes on the performance of 4H-SiC MOSFETs has been studied. These processes include different gate oxide depositions (high-temperature oxide, low-temperature oxide, and plasma-enhanced chemical vapor deposition oxide) and annealing processes (oxygen, NO, and <formula formulatype="inline"><tex>$\hbox{CO}_{2}$</tex></formula>). Various MOS device parameters, particularly, threshold voltage, subthreshold slope, field-effect electron mobility, sheet electron carrier concentration, and Hall mobility, are correlated with various process steps. </para>

Seal Formation in Silicon Planar Patch-Clamp Microstructures

This paper presents a microfabricated planar patch-clamp electrode design and looks at the impact of several physical characteristics on seal formation. The device consists of a patch aperture, 1.5-2.5 mum in diameter and 7-12 mum in depth, with a reverse-side deep-etched 80-mum well. The patch aperture was coated with either thermal oxide or plasma-enhanced chemical vapor deposited (PECVD) SiO2. Some of the thermal oxide devices were converted into protruding nozzle structures, and some were boron-doped. Seal formation was tested with cultured N2a neuroblastoma cells. The PECVD oxide devices produced an average seal resistance of 34 MOmega(n = 24), and the thermal oxide devices produced an average seal resistance of 96 MOmega(n = 59). Seal resistance was found to positively correlate with patch aperture depth. Whole-cell recordings were obtained from 14% of cells tested with the thermal oxide devices, including a single recording where a gigaohm seal was obtained.

A Novel Bistable Two-Way Actuated Out-of-Plane Electrothermal Microbridge

In this paper, we report the design, simulation, fabrication, and testing of a novel electrothermally actuated buckled microbridge for out-of-plane actuation. The new structure consists of a bridge supported by two springs and two legs at both supporting ends. The bridge and the spring are trilayer structures: low-stress plasma-enhanced chemical-vapor-deposition (PECVD) oxide (2.5 mum), high compressive stress PECVD oxide (1 mum), and phosphorus-doped silicon (2 mum). The legs consist only of 2-mum-thick phosphorus-doped silicon. The overall size of the actuator is 1200 mum by 100 mum excluding the contact pads. Analytical expressions used to determine torsional and axial stiffnesses at the supporting ends are derived. Together with bistability criteria developed by Michael and Kwok, the microbridge structure is designed to exhibit a bistable behavior. It is also designed to have a two-way actuation capability. Electrothermal analysis and thermomechanical finite element ANSYS simulations are performed to determine the switching waveforms for the two-way actuation and verify the bistability. Actuation of the fabricated structure from the buckled-up to the buckled-down states required a 7-V voltage pulse for 1 ms across the legs, followed by a 5-V pulse for 4 ms across the bridge. A 9-V pulse for 0.5 ms only to legs enabled the switching of the bridge from the buckled-down to the buckled-up states. An out-of-plane movement of 31 mum is demonstrated for a 1200-mum-long microbridge. Larger movement can be obtained by increasing the microbridge length and the compressive stress of the stressed oxide layer of the bridge.

Materials characterization of WN xC y, WN x and WC x films for advanced barriers

A ternary WN x C y system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 °C in a process sequence using tungsten hexafluoride (WF 6), triethyl borane (TEB) and ammonia (NH 3) as precursors. The WC x layers were deposited by a novel ALD process at a process temperature of 250 °C. The WN x layers were deposited at 375 °C using bis( tert-butylimido)-bis-(dimethylamido)tungsten ( t BuN) 2(Me 2N) 2W (imido–amido) and NH 3 as precursors. WN x grows faster on plasma enhanced chemical vapor deposition (PECVD) oxide than WC x does on chemical oxide. WN x C y grows better on PECVD oxide than on thermal oxide, which is opposite of what is seen for WN x . In the case of the ternary WN x C y system, the scalability towards thinner layers and galvanic corrosion behavior are disadvantages for the incorporation of the layer into Cu interconnects. ALD WC x based barriers have a low resistivity, but galvanic corrosion in a model slurry solution of 15% peroxide (H 2O 2) is a potential problem. Higher resistivity values are determined for the binary WN x layers. WN x shows a constant composition and density throughout the layer.

Effect of plasma treatment on the microstructure and electrical properties of MIM capacitors with PECVD silicon oxide and silicon nitride

Metal–insulator–metal (MIM) capacitors with plasma enhanced chemical vapor deposited (PECVD) nitride exhibit trap-induced dispersive behavior and electrical hysteresis, which lead to degradation in capacitor linearity at low frequencies. The dominant defect was suggested to be silicon dangling bonds originated from nitrogen deficiency. Previous methods to eliminate the dispersive behavior and electrical hysteresis include use of oxide–nitride–oxide (ONO) stacks and/or plasma pre-treatment of silicon substrate before nitride deposition [Van Huylenbroeck S, Decoutere S, Venegas R, Jenei S, Winderickx G (2002) IEEE Electron Device Lett 23:191; Lau WS (1990) Jpn J Appl Phys 29:L690]. In this study, the plasma post-treatment method was employed; MIM capacitors with PECVD oxide and nitride were treated with N2O and SiH4/NH3 plasma, respectively, after deposition of the dielectric layer. No apparent change in film microstructure is observed after plasma treatment. Plasma post-treatment is effective in eliminating the electrical hysteresis shift of the nitride capacitors. Fourier transform infrared (FTIR) absorption spectra suggest an increase of the Si–H bond after SiH4/NH3 plasma bombardment of the nitride films. Auger depth profiling indicates a slight increase of nitrogen to silicon ratio after plasma treatment. The increase of the Si–H bonds as well as the raise of nitrogen to silicon ratio are two possible causes for the elimination of the hysteresis shift of the plasma-treated nitride capacitors. The time dependent dielectric breakdown testing indicates a decrease in both the leakage current and the lifetime of the MIM capacitors treated with plasma. Possible dielectric degradation mechanism is explored.

Low Temperature Bonding of PECVD Silicon Dioxide Layers

The bonding of plasma enhanced chemical vapor deposition (PECVD) silicon dioxide layers, deposited at 300oC, to thermal silicon dioxide layers is described. The PECVD oxide requires pre-bond annealing and CMP for void free bonding. Post bond annealing for bond strengthening must be performed at a lower temperature than the pre-bond annealing step. Bond strengths of 1J/m2 have been achieved after bond annealing at 400oC. This bonding method can be used in layer/circuit transfer and has been demonstrated with the transfer of a 2µm SOI layer from one substrate to another.

Critical Adhesion Energy of Benzocyclobutene-Bonded Wafers

The dependencies of critical adhesion energy (CAE) of benzocyclobutene (BCB) bonded wafers on BCB thickness, the use of an adhesion promoter, and the materials being bonded are studied using a four-point-bending technique. The thicknesses of BCB used in the experiments ranged from 0.4 to . The CAE depends linearly on BCB thickness due to the thickness-dependent contribution of plastic dissipation energy of the BCB and thickness independence of BCB yield strength. The CAE increases by approximately a factor of 2 when an AP is used for both 2.6- and -thick BCB bonding layers because of chemical interactions. The CAEs measured at the interfaces between a Si wafer with plasma-enhanced chemical vapor deposited (PECVD) and BCB and between a Si wafer with thermally grown and BCB are approximately a factor of 3 higher than the CAE between a PG&O 1737 aluminosilicate glass wafer and BCB. The observed bond energies are about 18 and at the interfaces between PECVD oxide and BCB and between thermally grown oxide and BCB, respectively. These bond energies correspond to bond densities of 12–13 and 15–16 .

Ammonium Hydroxide Effect on Low-Temperature Wafer Bonding Energy Enhancement

A wafer prebonding treatment by ammonium hydroxide (NH 4 OH) leading to a high bonding strength at low temperatures is presented in three material systems. After 200°C annealing, a surface energy of about 700 mJ/m 2 for thermal silicon-oxide bonding and of 1300 mJ/m 2 for plasma-enhanced chemical vapor deposition oxide bonding is realized. It is suggested that the lower ability of ammonia, the by-product of a polymerization reaction, to break the siloxane (Si-O-Si) bridging bonds appears to be responsible for the increase in surface energy in both silicon oxide bonding cases. NH 4 OH treatment is also effective on bare germanium/ silicon-oxide bonding with a surface energy of 800 mJ/m 2 . A highly hydrophilic germanium surface obtained by this treatment accounts for the high bonding energy.