Planar Tunnel Field-effect Transistor Research Articles

Design and Sensitivity Analysis of Steep-Slope Bi-Channel Vertical Tunnel Field Effect Transistor

In this paper, the electrical characteristics of a low power steep-slope vertical tunnel field effect transistor (VTFET) is introduced with dual lateral channel in the source sidewall, which can considerably improve the device performance in comparison with the planar tunnel field effect transistor (TFET). The results demonstrate that unlike the conventional TFET with limited tunneling junction at the source/channel interface, the band to band tunneling area in VTFET is created along the entire length of the source region from the both sides, which amplifies the tunneling rate. The results demonstrate that on/off current ratio of 8.36e+7 and subthreshold swing (SS) of 10 mV/dec has been achieved for the VTFET in comparison with the on/off current ratio of 9.79e+5 and SS = 31 mV/dec for the planar TFET, respectively. Sensitivity analysis is conducted via calculating the standard deviation and mean value of main electrical measures as a function of various design parameters. It is indicated that gate workfunction and source doping density are critical design parameters that may fundamentally affect the efficiency of the device. An important feature of the proposed device is the insensitivity of the off-state current and subthreshold swing to the channel length scaling and drain bias, which exhibits VTFET promising potential for future low-power circuits.

Surrounding Channel Nanowire Tunnel Field-Effect Transistor with Dual Gate to Reduce a Hump Phenomenon.

The tunnel field-effect transistor (TFET) with surrounding channel nanowire (SCNW) structure promises better performance than the conventional planar TFET in terms of subthreshold swing (SS) and on-current (ION). In spite of the advantages of SCNW TFET, there are some technical issues in the aspects of a hump phenomenon in subthreshold region and a high ambipolar current (IAMB) in off-state. In order to overcome these issues, a novel dual-gate SCNW TFET (DG-SCNW TFET) with differential gate work functions (WFs) and a gate-drain underlap is proposed and studied by using technology computer-aided design (TCAD) simulation. In addition, a hetero-junction with SiGe source is applied to improve the device performance. Finally, it is confirmed that the optimized DG-SCNW TFET shows the remarkable performance comparing with the control device.

Rigorous Study on Hump Phenomena in Surrounding Channel Nanowire (SCNW) Tunnel Field-Effect Transistor (TFET)

In this paper, analysis and optimization of surrounding channel nanowire (SCNW) tunnel field-effect transistor (TFET) has been discussed with the help of technology computer-aided design (TCAD) simulation. The SCNW TFET features an ultra-thin tunnel layer at source sidewall and shows a high on-current (ION). In spite of the high electrical performance, the SCNW TFET suffers from hump effect which deteriorates subthreshold swing (S). In order to solve the issue, an origin of hump effect is analyzed firstly. Based on the simulation, the transfer curve in SCNW TFET is decoupled into vertical- and lateral-BTBTs. In addition, the lateral-BTBT causes the hump effect due to low turn-on voltage (VON) and low ION. Therefore, the device design parameter is optimized to suppress the hump effect by adjusting thickness of the ultra-thin tunnel layer. Finally, we compared the electrical properties of the planar, nanowire and SCNW TFET. As a result, the optimized SCNW TFET shows better electrical performance compared with other TFETs.

TBAL: Tunnel FET-Based Adiabatic Logic for Energy-Efficient, Ultra-Low Voltage IoT Applications

A novel, tunnel field-effect transistor (TFET)-based adiabatic logic (TBAL) circuit topology has been proposed, evaluated and benchmarked with several device architectures (planar MOSFET, FinFET, and TFET) and AL implementations (efficient charge recovery logic, 2N-2N2P, positive feedback adiabatic logic) operating in the ultra-low voltage ( $0.3~\text{V}\geq V_{DD} \leq 0.6~\text{V}$ ) regime. By incorporating adiabatic logic functionality into standard combinational logic, an 80% reduction in energy/cycle was achieved. A further 80% reduction in energy/cycle was demonstrated by utilizing near broken-gap TFET devices and simultaneous scaling of supply voltage to 0.3 V, resulting in a 96% reduction in energy/cycle as compared to conventional Si CMOS. Extension of operating frequency beyond 10 MHz, coupled with sub-threshold circuit operation, shows the feasibility of TBAL for energy-efficient Internet of Things applications.

A Recessed-channel Tunnel Field-Effect Transistor (RTFET) with the Asymmetric Source and Drain

Tunnel field-effect transistor (TFET) is a promising candidate for the next-generation electron device. However, technical issues remain for their practical application: poor current drivability, short-channel effect and ambipolar behavior. We propose herein a novel recessed-channel TFET (RTFET) with the asymmetric source and drain. The specific design parameters are determined by technology computer-aided design (TCAD) simulation for high on-current and low S. The designed RTFET provides ~446× higher on-current than a conventional planar TFET. And, its average value of the S is 63 mV/dec.

In-Built N<sup>+</sup> Pocket p-n-p-n Tunnel Field-Effect Transistor

The source-pocket (p-n-p-n) tunnel field effect transistor (TFET) has a narrow and highly doped N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> pocket layer between the source and channel to enhance the overall performance of the conventional p-i-n TFET. However, realizing this, N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> pocket increases the fabrication complexity since either an epitaxial growth in vertical TFETs or an implantation in planar TFETs is required to create the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> pocket. In this letter, using the charge plasma concept, we propose a technique to realize an in-built N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> pocket without the need for a separate implantation. We demonstrate using 2-D simulations that the proposed in-built N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> pocket p-n-p-n TFET exhibits a higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> (~20 times) and a steeper subthreshold swing (25 mV/decade) as compared with the conventional p-i-n TFET. Our approach overcomes the difficulty of creating a narrow N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> pocket doping and thus makes the p-n-p-n TFET more attractive in carrying on with the scaling trend.

Influence of corner effect on performance of three-dimensional tunnel field-effect transistor

The electrical performance of the three-dimensional (3D) tunnel field-effect transistor (TFET) was investigated via 3D numerical simulation. It was shown that the rectangular tri-gate (ReTG) TFET has a higher on-state current (Ion) and smaller subthreshold swing (SS) than those of the planar single-gate (SG) TFET owing to the gate control enhancement in the corners of the channel. On the basis of this observation, a trapezoidal tri-gate (TpTG) TFET was proposed, and its electrical properties were optimized. It was demonstrated that Ion increased and SS decreased as the corners become sharper. When the trapezoidal channel become triangular, Ion was approximately enhanced by over 500% and SS was reduced by 33% with respect to the planar SG TFET. In addition, as the channel length shrinks, both the ReTG TFET and triangular tri-gate TFET can efficiently suppress the off-state current.