A ${V}$ -band on-chip triangular planar monopole antenna implemented with a partially reflective surface (PRS) using standard 0.13- $\mu \text{m}$ BiCMOS technology is presented. The PRS, which is realized with a dual-layered gangbuster type-4 frequency selective surface structure, is designed to obtain 90% reflection of the incident power, thus reducing the power loss caused by the lossy silicon substrate and increasing the radiation efficiency simultaneously. The antenna-PRS codesign technique to optimize the antenna geometry and the radiation power is discussed. The total area of the antenna, including the GSG pad and the PRS, is 0.868 mm2. The measured $S_{11}$ is smaller than −17 dB from 54 to 66 GHz, while the maximum measured antenna gain is 1.42 dB at 69.5 GHz. The maximum simulated antenna efficiency is 41% at 65 GHz.