Planar Junctionless Transistor Research Articles

Ground plane and selective buried oxide based planar junctionless transistor

AbstractIn this work, we demonstrate a ground plane (GP) based Selective Buried Oxide (SELBOX) Junctionless Transistor (JLT), named as GP-SELBOX-JLT. The use of GP and SELBOX in the proposed device reduces the electric field and enhances volume depletion in the channel, hence improvesION/IOFFratio and scalability. Using calibrated 2-D simulation, we have shown that proposed device exhibits better Short Channel Effect (SHE) immunity as compared to SOI-JLT. Therefore, the proposed GP-SELBOX-JLT can be scaled without degrading the performance in sub 20 nm regime. In addition, the ac study has shown that the cutoff frequency (fT) of GP-SELBOX-JLT is almost equal to conventional SOI-JLT.

Silicon carbide planar junctionless transistor for low-medium voltage power electronics

This paper proposes a Silicon Carbide (SiC) based planar junctionless transistor (JLT), designed and simulated for low to medium power electronic applications, with a calibrated deck of SiC parameters. The simple structure of this device avoids the fabrication complexity associated with intricate junction geometries of vertical power devices and growth challenges of lateral heterostructure ones. Because of the wide bandgap (WBG) of SiC, the device exhibits a breakdown voltage of 100 V at channel length of 0.1 μm, which may be enhanced, at the cost of operating speed, by increasing the channel length. Compared to commercial enhancement-mode GaN (e-GaN) devices with similar breakdown voltage specification, the proposed device offers lower specific on-resistance (R on,sp ), and a significant reduction in capacitance due to its naturally self-aligned structure, leading to higher operating speed concluded from the mixed-mode simulations.

Engineering substrate doping in bulk planar junctionless transistor: Scalability and variability study

In this work two dimensional sentaurus simulations are used to study the impact of substrate doping on scalability and the variability of the bulk planar junctionless transistor (BPJLT). The results shows that, although increasing substrate doping density in BPJLT reduces the off-state current, subthreshold slope and the drain induced barrier lowering, the on-state current of the device is almost constant. To improve digital logic circuit performance of nanoscale BPJLT, novel δ-layer BPJLT (δ-BPJLT) is being proposed by incorporating p-type δ- layer below the uniformly doped device layer containing source, channel and the drain regions of BPJLT. It has been found that, the δ-layer below the device layer leads to reduction in the off-state current, process induced variability and the short-channel effects of the BPJLT. This is mainly because of the screening effect due to δ-layer under the device layer which significantly reduces the variations induced because of random dopant fluctuations.

Channel thickness-dependent mobility degradation in planar junctionless transistors

Electrical characteristics of junctionless transistors (JLTs) with varying Si thickness (tsi), were discussed in detail with consideration to maximum depletion width (Dmax), threshold voltage (Vth) and mobility degradation caused by a transverse electric-field. The tsi significantly influences both partially depleted operation and bulk conduction, accompanied by noticeable variation in Vth and mobility degradation. Our studies provide important information for a better understanding of the operation mechanism of two-dimensional material based transistors without junctions as well as JLTs.

Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

In this paper, we investigate the accuracy of the approximated analytical model currently utilized, by many researchers, to describe the depletion region width in planar junctionless transistors (PJLT). The proposed analysis was supported by numerical simulations performed in COMSOL Multiphysics software. By comparing the numerical results and the approximated analytical model of the depletion region width, we calculated that the model introduces a maximum RMS error equal to 90 % of the donor concentration in the substrate. The maximum error is achieved when the gate voltage approaches the threshold voltage ( V t h ) or when it approaches the flat band voltage ( V F B ) of the transistor. From these results, we concluded that this model cannot be used to determine accurately the flat-band and the threshold voltage of the transistor, although it represents a straightforward method to estimate the depletion region width in PJLT. By using the approximated analytical model, we extracted an analytical formula, which describes the electron concentration at the ideal boundary of the depletion region. This formula approximates the numerical data extracted from COMSOL with a relative error lower than 1 % . The proposed formula is in our opinion, as useful as the formula of the approximated analytical model because it allows for estimating the position of the depletion region also when the drain and source terminals are not grounded. We concluded that the analytical formula proposed at the end of this work could be useful to determine the position of the depletion region boundary in numerical simulations and in graphical representations provided by COMSOL Multiphysics software.

SEU Performance Enhancement in BPJLT Devices by Channel Doping and Film Thickness

The bulk planar junctionless transistor (BPJLT) is a potential candidate for future CMOS technologies due to its CMOS compatibility and scalability. In this paper, the impact of silicon film thickness and channel doping on single-event upset (SEU) radiation performance of BPJLT based SRAMs is studied using TCAD simulations. The simulation results show that BPJLT devices having higher channel doping and smaller film thickness provides the better SEU performance.

Si 3 N 4 :HfO 2 dual‐k spacer bulk planar junctionless transistor for mixed signal integrated circuits

For the first time halfnium oxide (HfO 2 ) is being incorporated in the dual-k spacers and has been used in bulk planar junctionless transistor (BPJLT). It has been found that incorporating HfO 2 in spacers not only improves the electrostatic integrity but also improves digital/analogue circuit performance of the BPJLT. Further, the increased effective gate length due to fringing electric field through HfO 2 to thin body reduces OFF-state leakage, subthreshold swing and drain-induced barrier lowering by ~60, ~15 and ~30%, respectively. Although the presence of HfO 2 inner spacer layer at source/drain increases the parasitic capacitances, the significant improvement in ON-state drive current reduces the intrinsic gate delay of the device. Further, the analogue circuit figures of merit such as transconductance, transconductance generation factor and the intrinsic gain of the proposed device are found to be significantly improved over the conventional BPJLT device. The mixed mode device/circuit simulation results of an inverter and the common source amplifier show that leakage power dissipation, propagation delay and the open-circuit voltage gain of the proposed device are improved significantly over the conventional BPJLT device. The fabrication process flow of this novel device has also been proposed.

Radiation performance of planar junctionless devices and junctionless SRAMs

The objective of this work is to analyze the radiation performance of the planar junctionless devices and junctionless device-based SRAMs. Bulk planar junctionless transistor (BPJLT) and silicon-on-insulator planar junctionless transistors (SOIPJLT) under heavy ions irradiation have been studied using TCAD simulations. 6T-SRAM cells built up of BPJLTs and SOIPJLTs have been investigated for their soft error performance. Even though the bipolar amplification of the SOIPJLT is more compared to BPJLT, the soft error performance of the SOIPJLT SRAM is better compared to BPJLT SRAM.

Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors

Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors

Planar junctionless transistor with non-uniform channel doping

We propose a planar junctionless transistor (JLT) in silicon-on-insulator (SOI) with non-uniform channel doping in vertical direction to improve the ON to OFF drain current ratio. In single gate JLT in SOI, a thin device layer is depleted in the off-state from the top of the layer and the leakage current flows through bottom of the device layer, and the leakage current depends on the device layer thickness. We show that the decrease of doping in vertical direction suppresses the leakage current flowing through the bottom of the device by decreasing conductivity at the bottom of the device layer.

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Low-frequency (LF) noise characteristics of wide planar junctionless transistors (JLTs) are investigated. Interestingly, carrier number fluctuation is the main contributor to the LF noise behavior of JLT devices, even though their bulk conduction features are clearly proved by the extracted flat-band voltage (Vfb). This is explained by the fact that mobile electrons in depletion, originating from the bulk neutral channel or source/drain regions, can interact with slow traps in the gate oxide, giving rise in return to fluctuations of the charge density in the bulk neutral channel. Similar values of trap density (Nt) are extracted in JLT devices and inversion-mode (IM) t0072ansistors, which also supports that the LF noise of JLT is well explained by the carrier number fluctuation model.

Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling

We propose a novel highly scalable source-drain-junction-free field-effect transistor that we call the bulk planar junctionless transistor (BPJLT). This builds upon the idea of an isolated ultrathin highly doped device layer of which volume is fully depleted in the off-state and is around flatband in the on-state. Here, the leakage current depends on the effective device layer thickness, and we show that with well doping and/or well bias, this can be controllably made less than the physical device layer thickness in a bulk planar junction-isolated structure. We demonstrate by extensive device simulations that these additional knobs for controlling short-channel effects reduce the off-state leakage current by orders of magnitude for similar on-state currents, making the BPJLT highly scalable.