Planar Device Structure Research Articles

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

Grooved gate metal–oxide-semiconductor field-effect transistors (MOSFETs) are known to alleviate many of the short channel and hot carrier effects that arise when MOSFET devices are scaled down to very short channel lengths. However, they exhibit much higher parasitic capacitance with stronger bias dependence when compared to conventional planar devices. In this paper, we present a model for gate-to-drain and gate-to-source capacitance characteristics of a deep submicrometre grooved gate MOSFET. Both the intrinsic and extrinsic parts of the capacitance are modelled separately. In particular, the model presents a novel but simple way to account for the accumulation layer formation in the source/drain region of MOSFETs due to the application of the gate voltage. The results are compared with those obtained from a two-dimensional device simulator. The close match between the modelled and simulated data establishes the validity of the model. The model is then used to account for the superiority of capacitance characteristics of planar device structures and to arrive at optimization guidelines for grooved gate devices to match these characteristics.

Analysis of crosstalk in HgCdTe p-on-n heterojunction photovoltaic infrared sensing arrays

In this paper, an experimental and theoretical study is carried out of crosstalk between nearest-neighbor devices within a backside-illuminated linear HgCdTe photovoltaic infrared sensing array. The dominant form of crosstalk that occurs in high performance photovoltaic arrays is associated with photogenerated minority carriers that diffuse laterally between adjacent devices within the array. To measure crosstalk, a scanning laser microscope is used to obtain a spatial map of spot-scan photoresponse at a temperature of 80K for individual p-on-n photovoltaic devices within the linear array. These experimental results are compared to calculations performed on a commercial two-dimensional device simulation package. The crosstalk measurements and calculations presented in this paper include results on mid-wavelength infrared planar device structures, as well as long-wavelength infrared mesa-isolated devices, which give measured crosstalk values of 6.2 and 8.3%, respectively. The results indicate that the device simulations are in good agreement with experimental results. Further simulations are carried out to determine the sensitivity of crosstalk to various material and device parameters such as epitaxial layer thickness (7 to 25 µm), illumination wavelength (1.047 to 11.0 µm), minority carrier diffusion length (8 to 90 µm), and diode pitch. It is found that the dominant feature influencing the value of crosstalk is the distance between the region of photogeneration and the collecting p-n junction.

Design of high-frequency ZnO-coated optical fiber acoustooptic phase modulators

In this paper, we present a theory of an optical fiber acoustooptic phase modulator using piezoelectric zinc oxide (ZnO) coating. The effects of changing device parameters in the acoustooptic resonator are investigated for transducer design. These results are entirely different from those of the well-known; planar device structure since every part plays an important role in the resonator structure. Optical phase modulation in the frequency region up to 1 GHz is also demonstrated. Multiple sharp resonance peaks with a maximum phase shift of 0.7 radians are observed.

Enhanced arsenic diffusion and activation in HgCdTe

Temperature and time dependent Hg-annealing studies for arsenic activation have been carried out on As-doped molecular beam epitaxy HgCdTe eitherin situ or by ion implantation to determine the extent of arsenic activation in the single layer. Enhanced As diffusion and activation in double layer heterostructures have also been investigated to further our understanding of the effects on zero bias resistance-area product (RoA) and quantum efficiency. The results show that the arsenic activation anneal is limited by Hg self-diffusion into the HgCdTe epilayer. Using this arsenic activation process for eitherin situ doped arsenic or implanted arsenic, high performance p-on-n double layer heterostructure photodiodes have been demonstrated on both mesa and planar device structures.

Planar 1.3 and 1.55 μm InGaAs(P)/InP electroabsorption waveguide modulators using oxygen ion mixing and the photoelastic effect

Efficient 1.3 and 1.55 μm InP-based electroabsorption waveguide modulators with planar device structures have been demonstrated. Elevated temperature oxygen ion implantation and/or the photoelastic effect induced by W metal stressor stripes deposited on the semiconductor surface have been used to produce these self-aligned planar guided-wave devices. The oxygen ion mixing process has been used to simultaneously achieve compositional disordering and electrical isolation of superlattice material while the photoelastic effect has been used to improve the lateral mode confinement. A 1.3 μm Franz–Keldysh modulator with a ≳10 dB extinction ratio at 2 V and a 1.55 μm device with a ≳10 dB extinction ratio at 7 V are reported. These single growth step planar processing techniques have also been used to fabricate relatively low-loss (<4 dB/cm) double heterostructure InGaAs(P)/InP single-mode optical waveguides which demonstrate their usefulness in developing InP-based photonic integrated circuits.

Efficient room-temperature continuous-wave AlGaInP/AlGaAs visible (670 nm) vertical-cavity surface-emitting laser diodes

Significant improvement in the performance of AlGaInP/AlGaAs visible vertical-cavity surface-emitting laser diodes has been achieved in gain-guided planar-geometry devices utilizing proton implants to define the current injection path. Threshold currents as low as 1.25 mA were measured on 10 /spl mu/m-diameter devices, with maximum power output of 0.33 mW from larger devices. Continuous-wave (cw) lasing was achieved at temperatures as high as 45/spl deg/C. The improved diode performance is attributed to better lateral heat-sinking and reduced parasitic heat generation afforded by the planar device structure, relative to previously-reported air-post structures. This work represents the first realization of efficient room-temperature operation of AlGaInP-based visible VCSEL diodes. >

GaAs 256-bit static RAM

A GaAs 256×1-bit static RAM with 2000 FETs organised in E/D-type DCFL circuits was successfully fabricated. A planar device structure was realised by using selective ion implantation and dielectric intermediate lift-off technology. The access time and the power dissipation were 50 ns and 9.4 mW, respectively.

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed ( \tau_{d} \sim 100 ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.

Stationary Gunn domains created by anode doping gradient current-density reduction

The conditions for the production of stationary anode Gunn-effect domains have been clarified by both experimental and computational results. The stationary domains have been observed in both sandwich and planar device structures and it is proposed that this effect is due to the balancing of drift and diffusion currents at the doping gradient of the anode contact.

Discrete and planar monolithic structures of III–IV compounds and alloys

Abstract Progress in the state-of-the-art of the fabrication of discrete and planar monolithic structures in III–V semiconductor compounds and alloys will be presented. Devices made by diffusion and grown-diffusion techniques on Ga1−xAlxAs, GaAs1−xPx, and GaP will be discussed with emphasis on planar device structures. In addition, a comparison of the contacts from various metallurgies used on these materials will be discussed.