Planar Bipolar Transistors Research Articles

Gate voltage dependent characteristics of p–n diodes and bipolar transistors based on multiwallCNx/carbon nanotube intramolecular junctions

The electrical transport characteristics of multiwallCNx/carbon nanotube intramolecular junctions were studied. The junctions could be used asdiodes. We found that the rectification resulted from p–n junctions, not frommetal–semiconductor junctions. The gate effect was very weak when the diodeswere reverse biased. At forward bias, however, some of the p–n diodes could ben-type transistors. Experimental results supported the opinion that the gatevoltage dependent property is derived from the Schottky barrier between theCNx part and the electrode. Using p–n diodes, a bipolar transistor with nanoscale componentswas built, whose behavior was very similar to that of a conventional planar bipolartransistor.

Power devices modelling: on and off state

The design of power and high voltage devices using two-dimensional numerical simulation is presented. The basic equations of semiconductors are explained along with special features belonging to power devices. The software tools used are described; they are based on the solution of either Poisson's equation alone to study the high voltage, off-state behaviour of the device, or the three coupled equations (Poisson and currents) to evaluate the on-state behaviour (high or low biased). The breakdown voltage is calculated by the solution of the ionization integrals for both electrons and holes, and its location is given. On-resistance and external currents are calculated for the off-state. Some examples are given, including the current flowing in a multicell vertical DMOS (VDMOS), the voltage handling capability of the lateral double diffused MOS transistor (LDMOS) with and without a reduced surface field (RESURF) technique, the influence of a semi-resistive layer on the on-state behaviour of the LDMOS, and the voltage handling capability of a planar bipolar transistor with a semi-resistive layer.

Observation of phosphorus pile-up at the SiO2-Si interface

The Si oxidation rate at high temperatures is increased by heavy P doping. Sputter ion-Auger techniques have been used to investigate the oxide thickness and P concentration after 900 °C oxidation with an initial P surface concentration of between 2×1018 and 3.2×1020/cm3. Phosphorus was found to pile up in the Si-SiO2 interface region. The maximum P concentration near the interface was found to depend on doping and was (at certain P concentrations) an order of magnitude larger than that predicted by redistribution theory. A vacancy–P-complex model is presented to explain the observed behavior. A correlation between the selective pile-up of P at the interface and the current gain of planar bipolar transistors is reported.

Determination of a collector junction model for planar bipolar transistors

This paper is concerned with the representation of the collector-base junction of planar bipolar transistors by a model capable of accurate characterization of junction capacitance and avalanche breakdown behavior. The model chosen consists of an exponential impurity density profile with cylindrical peripheral region approximation, and is regarded as the simplest representation suitable for the purpose. Objectives are the practical determination of the defining parameters (collector background, impurity density, exponential characteristic length, and collector junction depth) for such a model, and the demonstration of its accuracy for the physical characterization of the device structure. Model parameter determination is carried out in terms of junction capacitance and BV CBO measurements, by processes of computer fitting between model and measured data; the procedures used are nondestructive. It is shown, in particular, that the values obtained for the collector resistivity and junction depth are in very good agreement with those derived by 4-point probe measurement and by bevel and stain sectioning, respectively.

Effects of the distributed nature of base resistance on the manifestation of noise in planar transistors

Noise measurements at moderate frequencies on several types of planar bipolar transistors are presented. The results show that the representation of the base region by a single resistance in the equivalent circuit is incompatible with the measured values of thermal noise and base-current noise. A theoretical analysis of thermal and current-induced noise is given for various geometries of base region, and provides a partial explanation of the observed effects.

The use of secondary ionic emission and nuclear reactions to determine the parameters in the manufacture of a planar transistor

Several microanalytical problems arising in the study of the manufacture of a planar bipolar transistor are solved using the techniques of nuclear reactions and secondary ionic emission analysis. The results obtained permit a comparison of the possibilities of the two methods.

On the wide-range bias dependence of transistor d.c. and small-signal current gain factors

A critical reappraisal is made of the bias dependence of the d.c. and small-signal a.c. current gain factors of planar bipolar transistors over a wide range of currents. This is based on a straightforward consideration of the three basic components of the d.c. base current arising due to emitter-to-base injected minority carrier transport, base-to-emitter carrier injection, and emitter-base surface depletion layer recombination effects. Among other important results it is shown that over a useful bias range the d.c. and small-signal current gain factors, respectively, obey the simple relationships: H FE∞ I c 1 3 and h fe≈ 1.5h FE Experimental results on representative n- p- n and p- n- p silicon devices are given which support most of the analytical findings.

HFEfalloff at low temperatures

It is shown that for shallow planar bipolar transistors, tunneling, currents through the emitter-base junction can cause pronounced h <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> falloff at low temperatures.

Electron Beam Fabrication of Micron Transistors

For high-speed performance as well as high packing density, it is desirable to make the components in integrated circuits as small as possible. One of the fundamental problems in making smaller components is that of limitations in the optical technology. This paper describes an experimental process and the results obtained by using an electron-optical system to fabricate small transistors. Planar bipolar transistors with emitter and base contact windows one micron wide have been fabricated, with the electron beam exposure system used to open all the diffusion windows as well as to expose the metallization patterns. Conventional etching techniques are unable to provide 1-µm wide metal paths in half-to one-micron thick metal layers; therefore the lift-off process is used. The dc and ac characteristics presented compare favorably, for the first time using this fabrication process, with the best bipolar transistors produced by optical masking processes. These characteristics provide a guide for refinement in future micron transistor design.

Leakage currents, surface current and 1/f noise in planar bipolar transistors

Using arguments based on the d.c. equivalent circuit of a planar bipolar transistor, it is shown that the ratio ICEO/ICBO is a measure of the significance of surface recombination current. Measurements of 1/f noise and ICEO/ICBO for a variety of transistors provide new evidence that the 1/f noise is due to the surface recombination current.

Transistor fabrication using diffusion barriers produced by electron beams

Diffusion barriers produced directly by electron-beam-initiated chemical reactions have been used to fabricate planar bipolar transistors without the use of normal oxidation or etching processes. Electrical characteristics of the transistors are comparable with conventional devices.

The electron beam fabrication of small geometry transistors

The present trend in molecular electronics is both to reduce the overall size of the completed circuit and also to go to more complex circuits containing larger numbers of components. Both of these tendencies result in the requirement of smaller component sizes in the circuit. However the planar method normally used to fabricate these components is subject to certain dimensional limitations. This paper describes the fabrication of a planar bipolar transistor with an emitter contact 1 μ 2. This reduction in geometry is made possible by the use of an electron beam for the exposure of the resist rather than the conventional method of defining area by optical exposure of a light sensitive resist through a photographic mask. The problems involved in the location and sequential alignment of these small areas are discussed and a novel method for overcoming these difficulties is described. This technique utilizes the effect of lateral diffusion under the oxide mask to achieve area isolation combined with the definition of small areas by the intersection of narrow stripes. It is possible by these methods to drastically reduce the requirements for sequential alignment. The characteristics of micron size transistors with total active areas only 0·0002 × 0·0006 in. will be presented.

Mechanisms of Ionizing Radiation Surface Effects on Transistors

Ionizing radiation effects on silicon planar bipolar transistors to determine degradation mechanisms