Pixel Truncation Research Articles

Low Power Motion Estimation Algorithm and Architecture of HEVC/H.265 for Consumer Applications

High-quality videos like high-definition (HD) and ultra HD became an essential requirement in recent applications such as security surveillance, television system, etc. However, due to increase in resolution of the videos, the volume of visual information data increases significantly, which became a challenge for storage, transmission and processing the HD video data. The new video compression standard, high efficient video coding (HEVC), achieved two-fold video efficiency improvements as compared to H.264/AVC using efficient compression techniques. Motion estimation (ME) is one of the computationally intensive blocks in video CODEC. In HEVC, the complexity of ME further increases due to a large processing unit and flexible partitioning of the prediction unit (PU). In this paper, we proposed a low power ME algorithm and architecture of the HEVC for consumer applications. The proposed algorithm and architecture utilizes sub-sampling, data reuse, pixel truncation and adaptive search range techniques for reducing the computational power. Simulations result shows that the proposed ME algorithm requires an average of 53.82% fewer search points as compared to the reference software HM with a small degradation in PSNR and little increment in bit-rate. The proposed architecture is simulated and synthesized using standard 90 nm technology. The proposed ME architecture can process $3840\times2160$ @ 30 fps video sequences with only 4.5193 mm2 of the area and 8.192 KB of SRAM. The operating frequency of the proposed architecture is 250 MHz with 151.7619 mW of power.

Computationally Efficient Motion Estimation Algorithm for HEVC

In this paper, we present a novel computationally efficient motion estimation (ME) algorithm for high-efficiency video coding (HEVC). The proposed algorithm searches in the hexagonal pattern with a fixed number of search points at each grid. It utilizes the correlation between contiguous pixels within the frame. In order to reduce the computational complexity, the proposed algorithm utilizes pixel truncation, adaptive search range, sub-sampling and avoids some of the asymmetrical prediction unit techniques. Simulation results are obtained by using the reference software HM (e n c o d e r_l o w d e l a y_P_m a i n and e n c o d e r_r a n d o m a c c e s s_m a i n profile) and shows 55.49% improvement on search points with approximately the same PSNR and around 1% increment in bit rate as compared to the Test Zonal Search (TZS) ME algorithm. By utilizing the proposed algorithm, the BD-PSNR loss for the video sequences like B a s k e t b a l l P a s s_416 × 240@50 and J o h n n y_1280 × 720@60 is 0.0804 dB and 0.0392 dB respectively as compared to the HM reference software with the e n c o d e r_l o w d e l a y_P_m a i n profile.

In-Block Prediction-Based Mixed Lossy and Lossless Reference Frame Recompression for Next-Generation Video Encoding

Frame recompression is an efficient way to reduce the huge bandwidth of external memory for video encoder, especially for P/B frame compression. A novel algorithm, which is called mixed lossy and lossless (MLL) reference frame recompression, is proposed in this paper. The bandwidth reduction comes from two sources in our scheme, which differs from its previous designs and achieves a much higher compression ratio. First, it comes from pixel truncation. We use truncated pixels (PR) for integer motion estimation (IME) and acquire truncated residuals for factional motion estimation (FME) and motion compensation (MC). Because the pixel access of IME is much larger than FME and MC, it saves about 37.5% bandwidth under 3-b truncation. Second, embedded compression of PR helps to further reduce data. The truncated pixels in the first stage greatly help to achieve a higher compression ratio than current designs. From our experiments, 3-b truncated PR can be compressed to 15.4% of the original data size, while most current embedded compressions can only achieve around 50%. For PR compression, two methods are proposed: in-block prediction and small-value optimized variable length coding. With these experiments, the total bandwidth can be reduced to 25.5%. Our proposed MLL is hardware/software friendly and also fast IME algorithm friendly frame recompression scheme. It is more suitable to work together with the data-reuse strategy than the previous schemes, and the video quality degradation is controllable and negligible.

Low Power Motion Estimation Design Based on Non-Uniform Pixel Truncation

Motion estimation consumes a large portion of computational resources in most video encoders, such as AVS, H.264/AVC and HEVC/H.265. Pixel truncation can effectively reduce the power consumption of motion estimation and it is usually performed uniformly within the search window, which unfortunately brings degradation to the compression efficiency. However, based on the observation of unequal distribution of motion vectors, we can apply different number of truncated bits in different search area to achieve a better tradeoff between compression efficiency and power consumption. The proposed algorithm saves approximately 64% of the hardware computational complexity than conventional full-bit pixel search and at the same time achieves almost the same compression efficiency, with only 0.04 dB loss.

Reconfigurable architecture for VBSME with variable pixel precision

Current video coding standards, e.g. MPEG-4 H.264/AVC, include Variable Block Size Motion Estimation, in this paper, this process is implemented by a reconfigurable architecture based on Signed Digit arithmetic. Bit serial computation is applied to reconfigure pixel precision. The reconfigurable architectural model is extremely simple to reconfigure. Pixel truncation is used to speed up computation saving up 23.5% of clock cycles for 4-bit precision. This design allows to process all motion vectors of a block in just one iteration. This system has been implemented in FPGA, and HDTVp results are presented. Main characteristics, of this architecture are: very reduced cost, high performance, and reconfigurable pixel precision, these features could be useful in mobile devices.

Low Power H.264 Video Compression Achitecture for Mobile Communication

This paper presents a method to reduce the computation and memory access for variable block size motion estimation (ME) using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block size(16×16 pixels) ME. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyze the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. Our method is able to reduce the total computation and memory access compared to conventional full-search method without significantly degrading picture quality. With unique data arrangement, the proposed architectures are able to saveup to 53% energy compared to the conventional full-search architecture. This makes such architectures attractive for H.264application in future mobile devices. Keywords- Low-power design, motion estimation (ME), video coding, VLSI architecture.

Power efficient motion estimation algorithm and architecture based on pixel truncation

A new block matching algorithm and its VLSI architecture for performing Motion Estimation (ME) are presented in this paper. In the reported fast two stage search algorithm, ME is performed in two stages. In the first stage, pixel truncation is used. In the second stage, ME is performed with full pixel resolution with an adaptive search pattern. The main advantage of the proposed algorithm is the inclusion of an early termination mechanism to reduce overall power consumption for the resulting architecture. The paper also introduces a suitable architecture to implement the proposed ME algorithm. In this architecture, a new memory management scheme has been proposed so that different bit planes can be accessed at different stages of ME from the same memory module. It has been shown that the proposed architecture can save approximately 27% power compared to another recently reported architecture. The proposed architecture can therefore be considered suitable for portable, battery-powered video consumer devices <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .

System-Level Energy Optimization for Error-Tolerant Image Compression

Based on the natural error tolerance of image and multimedia processing, aggressive voltage scaling has been considered for energy savings by trading off accuracy. However, aggressive voltage scaling in image compression may not reduce overall system energy consumption because of the reduction in the compression ratio. Based on the system-level analysis, we present an adaptive pixel and coefficient truncation technique to successfully reduce error rates so that we can achieve great energy savings without significant quality degradation. Our experimental results show that average energy savings of up to 40% can be realized at a trivial implementation cost.

A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

Variable block size motion estimation (VBSME) is one of several contributors to H.264/AVC's excellent coding efficiency. However, its high computational complexity and huge memory traffic make deign difficult. In this paper, we propose a memory-efficient and highly parallel VLSI architecture for full search VBSME (FSVBSME). Our architecture consists of 16 2-D arrays each consists of 16 × 16 processing elements (PEs). Four arrays form a group to match in parallel four reference blocks against one current block. Four groups perform block matching for four current blocks in a pipelined fashion. Taking advantage of overlapping among multiple reference blocks of a current block and between search windows of adjacent current blocks, we propose a novel data reuse scheme to reduce memory access. Compared with the popular Level C data reuse scheme, our approach can save 98% of on-chip memory access with only 25% of local memory overhead. Synthesized into a TSMC 180-nm CMOS cell library, our design is capable of processing 1920 × 1088 30 fps video when running at 130 MHz. The architecture is scalable for wider search range, multiple reference frames and pixel truncation as well as down sampling. We suggest a criterion called design efficiency for comparing different works. It shows that the proposed design is 72% more efficient than the best design to date.

Low-Power H.264 Video Compression Architectures for Mobile Communication

This paper presents a method to reduce the computation and memory access for variable block size motion estimation (ME) using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block-size (16 times 16 pixels) ME. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyze the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. Our method is able to reduce the total computation and memory access compared to conventional full-search method without significantly degrading picture quality. With unique data arrangement, the proposed architectures are able to save up to 53% energy compared to the conventional full-search architecture. This makes such architectures attractive for H.264 application in future mobile devices.

Application of pixel truncation to reduce intensity artifacts in myocardial SPECT imaging with tc-99m tetrofosmin

Background. Technetium 99m–labeled radiopharmaceuticals accumulate in the liver and gallbladder, where they generate intensity artifacts that can result in misdiagnosis of myocardial single photon emission computed tomography (SPECT) images. This study identifies and eliminates factors affecting the magnitude and appearance of intensity artifacts in a gallbladder-heart phantom. Methods and Results. The myocardium and background compartments of a phantom were filled with Tc-99m at concentrations of 320 and 26.1 kBq/mL, respectively. A disposable plastic syringe containing 5 mL of Tc-99m as a model of the gallbladder was fixed in a position lateral to the heart phantom. Artifact intensity was determined on SPECT images over a specific activity range in the syringe (28.6, 6.6, and 0.2 MBq/mL). Among 72 projection images, those with maximal heart counts in the region of interest were selected. Counts above and below 110% of the maximal heart count in all projection images were excluded and reconstructed, respectively. At 28.6 and 6.6 MBq/mL, excessive artifacts generated cold pixels immediately around the source, whereas lower activity (0.2 MBq/mL) caused the artifacts to disappear. Truncating the counts in the gallbladder caused the intensity artifacts at specific activities of 28.6 and 6.6 MBq/mL to disappear. Conclusions. The magnitude and appearance of intensity artifacts depend on contrast between extracardiac activities in the same slices of the heart in myocardial SPECT images with Tc-99m tetrofosmin, and pixel truncation can eliminate them. (J Nucl Cardiol 2002;9:622-31)

Low-power VLSI design for motion estimation using adaptive pixel truncation

Power consumption is very critical for portable video applications such as portable videophone and digital camcorder. Motion estimation (ME) in the video encoder requires a huge amount of computation, and hence consumes the largest portion of power. We propose a novel method of reducing power consumption of the ME by adaptively changing the pixel resolution during the computation of the motion vector. The pixel resolution is changed by masking or truncating the least significant bits of the pixel data, which is governed by the bit-rate control mechanism. Experimental results show that on average more than 4 bits ran be truncated without significantly affecting the picture quality. This results in more than 60% reduction in power consumption.