Low Power H.264 Video Compression Achitecture for Mobile Communication

Abstract

This paper presents a method to reduce the computation and memory access for variable block size motion estimation (ME) using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block size(16×16 pixels) ME. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyze the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. Our method is able to reduce the total computation and memory access compared to conventional full-search method without significantly degrading picture quality. With unique data arrangement, the proposed architectures are able to saveup to 53% energy compared to the conventional full-search architecture. This makes such architectures attractive for H.264application in future mobile devices. Keywords- Low-power design, motion estimation (ME), video coding, VLSI architecture.