Pixel Layout Research Articles

Readout circuit with dual switching mode design for infrared focal plane arrays

The paper proposes a readout circuit architecture with adjustable integration time for dual-band infrared detectors. The readout circuit uses direct injection to be combined with a capacitive trans-impedance amplifier. The amplifier is sharing between two pixels to reduce the complexity of the readout circuit. The proposed device reduces power consumption and area overhead compared to traditional structures. An experimental chip was fabricated using the TSMC 0.35μm 2P4M 5V process. The resulting unit pixel layout area is 40μm×40μm with input photocurrent ranging from 0.11pA to 50nA. CTIA mode is applicable from 0.11pA to 10nA, while DI mode is applicable from 3.3pA to 50nA. The maximum operating frequency of the chip are 4MHz. The CTIA output swing is 1.2V, the DI output swing is 2V. The signal to noise ratio of the readout circuit is 65dB and power consumption is less than 9.6mW.

Improvement of color separation characteristics of a side-illuminated color photo sensor

For easy color photography, we have proposed a method of irradiating a silicon photosensor from the side. This color imaging method applies a simple pixel structure without color filters, and prevents the generation of false colors and moiré patterns. A test chip was fabricated using a 0.35 µm complementary metal–oxide–semiconductor 1-poly 4-metal process. The chip dimensions are 5000 × 5000 µm2. The pixel layout structure that we proposed previously was remodeled. We confirmed that the four colors blue, green, red, and near-infrared are isolated in the normal color wavelength range in a light irradiation experiment.

Electrical characterization of different DEPFET designs on die level

For the future X-ray astronomy project Advanced Telescope for High ENergy Astrophysics plus (ATHENA+) wafer-scale DEpleted P-channel Field Effect Transistor (DEPFET) detectors are proposed as Focal Plane Array (FPA) for the Wide Field Imager (WFI). Prototype structures with different pixel layouts, each consisting of 64 x 64 pixels, were fabricated to study four different DEPFET designs. We report on the results of the electrical characterization of the different DEPFET designs. The transistor properties of the DEPFET structures are investigated in order to determine whether the design intentions are reflected in the transistor characteristics. In addition yield and homogeneity of the prototypes can be studied on die, wafer and batch level for further improvement of the production technology with regard to wafer-scale devices. These electrical characterization measurements prove to be a reliable tool to pre-select the best detector dies for further integration into full detector systems.

Challenges in CMOS‐based images

AbstractHigh resolution CMOS image sensor demand is driven by consumer applications like mobile phone or digital still camera. To maintain the image quality, we have to save the signal to noise ratio (SNR) despite the number of photons reduction gathered by the pixel. In this paper, we present how back‐side illumination technology could help to recover signal and how to optimize the process and device in order to reduce the noise. A quantum efficiency larger than 70% is targeted to justify efforts done on BSI process development. We also have to pay attention to pixel to pixel crosstalk coming from free carrier diffusion. To overcome this parasitic phenomenon, deep trench isolation (DTI) should be considered in order to significantly reduce crosstalk between two neighboring pixels. The second main noise contributor related to BSI process is the dark current signal. Dark current less than 1 aA per pixel at room temperature is mandatory to save the image quality at low light level. Therefore, all the Si‐SiO2 interfaces at the pixel side walls have to be processed without any process damage to reduce as much as possible the surface defects. On top of that, side wall implantation and side wall dielectric fabrication have been optimized to reduce this noise source. The pixel layout has to be fully optimized also to collect and store charges properly. With respect to the 3D pixel shape, a new fully depleted pinned photodiode with vertical charge storage and no lag has been developed. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Submicrometer grating light bar for a color-separation backlight

A light bar patterned using a submicrometer grating was designed to replace conventional dye color filters for color liquid crystal displays. The light bar generates color rays by transmitting them from side-lit color light-emitting diodes through the submicrometer grating. These angular color rays are then redirected by a V-grooved light guide, and then converged by a lens array and mapped to corresponding subpixel positions to efficiently display color images. The results show that 106% of the National Television System Committee (NTSC) color space in a blue-green-red-green (B-G-R-G) repeating pattern display pixel layout can be achieved.

Design of the AGIPD sensor for the European XFEL

For experiments at the European X-Ray Free-Electron Laser (XFEL) the Adaptive Gain Integrating Pixel Detector (AGIPD) is under development. The particular requirements include a high dynamic range of 0, 1 to more than 104 photons of 12.4 keV per pixel within an XFEL pulse of less than 100 fs duration, and a radiation tolerance for doses up to 1 GGy for 3 years of operation. AGIPD is a hybrid-pixel detector system with a total of 1024 × 1024 pixels of size 200 μm × 200 μm. AGIPD will use 16 p+n-silicon sensors of 500 μm thickness. The nominal operating voltage is 500 V, however, for special applications operation close to 1000 V should be possible. Experimental data on the X-ray-dose dependence of the oxide-charge density and of the surface-current density have been implemented in the SYNOPSYS TCAD simulation program in order to optimize the design of the pixel and guard-ring layout. The methodology of the sensor design, the optimization of the most relevant parameters, and the optimized layout are described. Finally, the simulated performance, in particular the breakdown voltage, dark current and inter-pixel capacitance as function of the X-ray dose are presented.

The use of silicon photomultipliers for very high energy gamma ray astronomy: the optical issues

Due to its sensitivity and speed, the detector still widely used in Cerenkov astrophysics experiments remains the Photo-Multiplier Tube (PMT). However, there are some disadvantages to the PMT technology: the rather poor quantum efficiency, the use of high voltages, the high cost when used in large number in a matrix arrangement and a subsequent large weight. Hence, we have investigated the possibility to design future Cerenkov telescope cameras based on solid state technology, specifically Geiger Avalanche PhotoDiodes (G-APD’s). This paper describes our extensive simulations to design the optical setup to be employed with G-APD’s. We also discuss the reflector configurations, pixel layouts, light concentrators, microlens arrays and spectral efficiencies to optimize light collection. The electronic aspects of our work were presented in a recent companion paper (Pellion et al., Exp. Astron. 27(3):187, 2010).

Design of a Capacitive Detection Circuit using MUX and DLC based on a νMOS

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

Identification of Radiation Induced Dark Current Sources in Pinned Photodiode CMOS Image Sensors

This paper presents an investigation of Total Ionizing Dose (TID) induced dark current sources in Pinned PhotoDiodes (PPD) CMOS Image Sensors based on pixel design variations. The influence of several layout parameters is studied. Only one parameter is changed at a time enabling the direct evaluation of its contribution to the observed device degradation. By this approach, the origin of radiation induced dark current in PPD is localized on the pixel layout. The PPD peripheral shallow trench isolation does not seem to play a role in the degradation. The PPD area and a transfer gate contribution independent of the pixel dimensions appear to be the main sources of the TID induced dark current increase. This study also demonstrates that applying a negative voltage on the transfer gate during integration strongly reduces the radiation induced dark current.

A Study of a High Performance Capacitive Sensing Scheme Using a Floating-Gate MOS Transistor

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 μm standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

Modeling of current—voltage characteristics for double‐gate a‐IGZO TFTs and its application to AMLCDs

Abstract— The equations for the transfer characteristics, subthreshold swing, and saturation voltage of double‐gate (DG) a‐IGZO TFTs, when the top‐ and bottom‐gate electrodes are connected together (synchronized), were developed. From these equations, it is found thatsynchronized DG a‐IGZO TFTs can be considered as conventional TFTs with a modified gate capacitance and threshold voltage. The developed models were compared with the top or bottom gate only bias conditions. The validity of the models is discussed by using the extracted TFT parameters for DG coplanar homojunction TFTs. Lastly, the new pixel circuit and layout based on a synchronized DG a‐IGZO TFT is introduced.

A CMOS Bio-Inspired 2-D Motion Direction Sensor Based on a Direction Computation Method Derived From the Directionally Selective Ganglion Cells in the Retina

A CMOS bio-inspired motion direction sensor structure and its associated computation method are proposed. Both method and structure with excitation-inhibition operation are derived from the directionally selective ganglion cells (DSGCs) in the retina to mimic their functions. Edge-number normalization for direction calculation and pseudo-random tessellation (PRT) structure for pixel layout arrangement are also proposed to enhance the accuracy of the computation. An experimental chip based on the proposed method and structure has been designed, fabricated, and measured. The chip comprised 32 × 32 pixels with a pixel size of 63 × 63 μm2 and a fill factor of 12.8%. The total chip size is 3.3 × 4.2 mm2 and the power consumption is 9.9 mW in the dark and 21 mW at a maximum clock rate of 10 MHz with 3.3-V power supply. The fabricated chip has been measured with different moving patterns, and a computation error of less than 11 degrees has been accomplished. This verifies the correct functions of the proposed motion direction sensor. With the capability of real-time motion detection and processing under low power dissipation, the proposed sensor is feasible for many applications.

Beam test results for the RAPS03 non-epitaxial CMOS active pixel sensor

Recently our group has been investigating the possibility of using a standard CMOS technology – featuring no epitaxial layer – to fabricate a sensor for charged particle detection. In this work we present the results obtained exposing sensors with 256×256 pixels ( 10 × 10 μ m pixel size, two different pixel layouts) to 180 GeV protons and positrons at the SuperProtoSynchrotron facility (CERN). We have investigated the different response of the two architectural options in terms of S/N, cluster width, intrinsic spatial resolution, efficiency. The results show a good Landau response, S/N about 22 with an average cluster size of 4.5 pixels, and an intrinsic spatial resolution of 1.5 μ m (order of 1/7th of the pixel size).

11.4: Transparent AMOLED Display Based on Bottom Emission Structure

AbstractA transparent active matrix organic light emitting diode AMOLED display based on a bottom emission structure, which is best for largesized OLED displays, has been fabricated. The transparent AMOLED display shows an image only to its bottom side, and background images can be seen through the transmissive windows. Pixel layout of the conventional bottom emission structure has been redesigned to merge transmissive openings to a single window per each pixel for higher transmissivity. A prototype of the transparent AMOLED display demonstrated 27% transmissivity and 100% NTSC color gamut.

Simulations of planar pixel sensors for the ATLAS high luminosity upgrade

A physics-based device simulation was used to study the charge carrier distribution and the electric field configuration inside simplified two-dimensional models for pixel layouts based on the ATLAS pixel sensor. In order to study the behavior of such detectors under different levels of irradiation, a three-level defect model was implemented into the simulation. Using these models, the number of guard rings, the dead edge width and the detector thickness were modified to investigate their influence on the detector depletion at the edge and on its internal electric field distribution in order to optimize the layout parameters. Simulations indicate that the number of guard rings can be reduced by a few hundred microns with respect to the layout used for the present ATLAS sensors, with a corresponding extension of the active area of the sensors. A study of the inter-pixel capacitance and of the capacitance between the implants and the high-voltage contact as a function of several parameters affecting the geometry and the doping level of the implants was also carried out. The results are needed in order to evaluate the noise and the cross-talk among neighboring pixels when connected to the front-end electronics.

Overview of Ionizing Radiation Effects in Image Sensors Fabricated in a Deep-Submicrometer CMOS Imaging Technology

An overview of ionizing radiation effects in imagers manufactured in a 0.18-mum CMOS image sensor technology is presented. Fourteen types of image sensors are characterized and irradiated by a <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> Co source up to 5 kGy. The differences between these 14 designs allow us to separately estimate the effect of ionizing radiation on microlenses, on low- and zero-threshold-voltage MOSFETs and on several pixel layouts using P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> guard-rings and edgeless transistors. After irradiation, wavelength dependent responsivity drops are observed. All the sensors exhibit a large dark current increase attributed to the shallow trench isolation that surrounds the photodiodes. Saturation voltage rises and readout chain gain variations are also reported. Finally, the radiation hardening perspectives resulting from this paper are discussed.

Recent developments with CMOS SSPM photodetectors

Experiments and simulations using various solid-state photomultiplier (SSPM) designs have been performed to evaluate pixel layouts and explore design choices. SPICE simulations of a design for position-sensing SSPMs showed charge division in the resistor network, and anticipated timing performance of the device. The simulation results predict good position information for resistances in the range of 1–5 kΩ and 150-Ω preamplifier input impedance. Back-thinning of CMOS devices can possibly increase the fill factor to 100%, improve spectral sensitivity, and allow for the deposition of anti-reflective coatings after fabrication. We report initial results from back illuminating a CMOS SSPM, and single Geiger-mode avalanche photodiode (GPD) pixels, thinned to 50 μm.

53.2: Recent Improvements of Droplet‐Driven Electrowetting Displays

AbstractA new display technology based on droplet moving by electro‐wetting was introduced in 2007. Major improvements were made regarding hydrophobic layer, fluids, pixel layout, driving electronics and system design resulting in an operating voltage of less than 20 V for a 2 mm droplet. This enables new approaches for bistable and high reflective displays (e‐paper) with low power consumption, superior ambient light performance and wide temperature range. The pixel size can be varied between 0.5 and 10 mm for single pixels and being typical 2 mm for 8‐Segment as well as for (color) matrix displays driven by Passive Matrix.

18.3: Additional Refresh Technology (ART) of Advanced‐MVA(AMVA) Mode for High Quality LCDs

AbstractWe proposed “Additional Refresh Technology(ART)”, which has the features of low color washout and fast response speed by only modifying the pixel layout. Besides, by utilizing ART technology, the image can be real time optimized with simple method. ART have successfully been implemented as the Advanced‐MVA(AMVA) mode for AUO's LCD‐TV products, that ART has become the promising solution of advanced LCD‐TV panels for mass‐production.

Implementation and Analysis of Charge-Pump Active-Matrix Organic Light-Emitting Diode Display Panel

An organic light-emitting diode (OLED) display panel using a charge-pump (CP) pixel addressing scheme was implemented and shown to be effective for information display applications. The panel luminance was 681 cd/m2 when driven by control signals with an amplitude of 8 V and a common-cathode voltage of 6 V. It was found that the parasitic overlap capacitance between a common electrode and a column bus plays a crucial role in the operation of the CP-OLED display panel. The losses of panel luminance and contrast ratio due to the capacitance could be minimized by optimizing the pixel layout design and fabrication processes.