Pixel Circuitry Research Articles

P‐6: Redefining Pixel Circuit Analysis: Causal Discovery and Probabilistic Modeling

When analyzing data using existing machine learning models without explicit causal information, several limitations often arise, particularly in the misinterpretation of correlations as causal relationships. These limitations are more pronounced in complex scenarios or in situations where outcomes are influenced by sequential effects. This paper presents an advanced methodology for analyzing pixel circuit design and its driving conditions, a domain characterized by complex interactions and multiple variables. Traditional machine learning methods, when applied in isolation, have shown limitations in unraveling the intricate causal relationships inherent in such systems. To address this challenge, we integrated Explainable AI (XAI) techniques, particularly SHAP (SHapley Additive exPlanations) values, into our analysis. In collaboration with domain experts, we constructed a Directed Acyclic Graph (DAG) that effectively reduced the complexity of interconnections and ensured consistency with empirical data. This approach facilitated a more accurate identification of the impact of each parameter and its causal influence. By decomposing the joint distribution of the variables into conditional distributions, taking into account their parental relationships, we gained a deeper understanding of the changes in causal mechanisms. Our methodology significantly enhanced the accuracy of causal analysis under realistic pixel driving conditions. The findings not only offer novel insights into pixel circuitry but also demonstrate the efficacy of combining machine learning with XAI in complex systems analysis, gaining wide acceptability among relevant experts.

Integration of EDWARD readout architecture in full-field fluorescence imaging detector

Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are a constant challenge. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD (Event-Driven With Access and Reset Decoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one, named 3FI65P1, is a full device with the analog pixel circuitry suited for full-field fluorescence imaging. It is already manufactured, and preliminary results are presented. The second chip, named EDWARD65P1, contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of the EDWARD architecture alone.

Design and Simulation of 140 dB Dynamic Range and 20 uVrms Readout Noise CMOS Image Sensor

This paper provides the design, simulation andimplementation of a very wide dynamic range and a low readoutnoise CMOS image sensor (CIS) with high sensitivity by using adiode connected transistors in parallel with floating diffusionnode and sensor output. The sensor is simulated, designed andimplemented in a 130 nm CMOS technology using cadence tool.The area of the proposed pixel reaches to 3 um x 3 um andconsists of seven NMOS transistors and one capacitor. Thereadout circuit has the following parameters as very low outputnoise of 20 uVrms with a 5 MHz bandwidth for pixel circuitry.Power dissipation of 10 uW was achieved at an operation voltageof 1.6 V for pixel circuitry. The proposed sensor has goodfeatures of low noise and a 140 dB wide dynamic range due to thediode connected transistor configuration that has been used. Thispaper provides the effect of adding a diode connected transistorsM7 and M8 on an increasing dynamic range of CMOS imagesensor to 140 dB and reducing its readout noise to 20 uVrms. Also,this paper provides a mathematical simulation of noise model ofCIS using Matlab and cadence.

Spectral Noise Analysis of a CMOS Imager at Low Temperature for Logarithmic Mode

The most common and useful CMOS high-dynamic-range imager is the one employing the active pixel sensor (APS) operating in the logarithmic mode. Notwithstanding, temporal noise can compromise the quality of the image generated by the focal-plane array. Most of the image-sensor noise models and results found in the literature are limited to a temperature range higher than that of the freezeout temperature, where the semiconductor doping impurities are all activated. The focus of this paper is to compare the noise spectrum behavior of the logarithmic image sensor at room temperature with that of a temperature near and below the freezeout point. Experimental results carried out in a small bidimensional pixel array fabricated in a standard 4-metal 2-poly 0.35- $\mu \text{m}$ CMOS technology suggests that thermal noise remains quite steady as the temperature reduces due to the increase in the sense-node resistance of the pixel circuitry. On the other hand, “spikes” have been identified with significant intensity in the spectral noise in all pixels when studied individually. These spikes in the spectrum have the same value in frequency when the device is submitted to different light intensities and temperatures. However, they were only observed for temperatures below 150 K and for frequencies below the corner frequency. The nonrandomic presence of these spikes in the noise spectrum indicates the presence of traps related to the defects inside the gate oxide and at the oxide–silicon interface. At room temperature, these spikes are not observed due to the thermal energy being higher than the binding energy of these traps.

Bioinspired polarization imager with high dynamic range

Polarization is one of the three fundamental properties of light, along with color and intensity, yet most vertebrate species, including humans, are blind with respect to this light modality. In contrast, many invertebrates, including insects, spiders, cephalopods, and stomatopods, have evolved to detect polarization information with high-dynamic-range photosensitive cells and utilize this information in visually guided behavior. In this paper, we present a high-dynamic-range polarization imaging sensor inspired by the visual system of the mantis shrimp. Our bioinspired imager achieves 140 dB dynamic range and 61 dB maximum signal-to-noise ratio across 384×288 pixels equipped with logarithmic photodiodes. Contrary to state-of-the-art active pixel sensors, where photodiodes in individual pixels operate in reverse bias mode and yield up to ∼60 dB dynamic range, our pixel has a logarithmic response by operating individual photodiodes in forward bias mode. This novel pixel circuitry is monolithically integrated with pixelated polarization filters composed of 250-nm-tall × 75-nm-wide aluminum nanowires to enable snapshot polarization imaging at 30 frames per second. This sensor can enable many automotive and remote sensing applications, where high-dynamic-range imaging augmented with polarization information can provide critical information during hazy or rainy conditions.

Organic Light-Emitting Field-Effect Transistors: Device Geometries and Fabrication Techniques.

Organic light-emitting transistors (OLETs), as novel and attractive kinds of organic electronic devices, have gained extensive attention from both academia and industry. The unique device architectures can simultaneously combine the electrical switching functionality of organic field-effect transistors and the light generation capability of organic light-emitting diodes in a single device, thereby holding great promise for reducing the complicated processes of next-generation pixel circuitry. This review involves the design, fabrication, and applications of OLETs with a comprehensive coverage of this field with the aim to give a deep insight into the intrinsic mechanisms of devices. Challenges and future prospects of OLETs are also discussed.

P‐216: Late‐News Poster: UHPD Technology for Enhanced User Experience of Near‐Eye Applications

UHPD technology is developed on glass substrate. This technology eliminates screen‐door effect and therefore enhances significantly user experience. A 2228ppi AMOLED panel has been demonstrated. Critical breakthroughs include 11.4um pixel circuitry integrated in LTPS process and 17.27% aperture ratio in each color. With additional MOST display flexibility is increased dramatically.

Characterization of chromium compensated GaAs as an X-ray sensor material for charge-integrating pixel array detectors

We studied the properties of chromium compensated GaAs when coupled to charge integrating ASICs as a function of detector temperature, applied bias and X-ray tube energy. The material is a photoresistor and can be biased to collect either electrons or holes by the pixel circuitry. Both are studied here. Previous studies have shown substantial hole trapping. This trapping and other sensor properties give rise to several non-ideal effects which include an extended point spread function, variations in the effective pixel size, and rate dependent offset shifts. The magnitude of these effects varies with temperature and bias, mandating good temperature uniformity in the sensor and very good temperature stabilization, as well as a carefully selected bias voltage.

Theoretical investigation of the noise performance of active pixel imaging arrays based on polycrystalline silicon thin film transistors.

Active matrix flat-panel imagers, which typically incorporate a pixelated array with one a-Si:H thin-film transistor (TFT) per pixel, have become ubiquitous by virtue of many advantages, including large monolithic construction, radiation tolerance, and high DQE. However, at low exposures such as those encountered in fluoroscopy, digital breast tomosynthesis and breast computed tomography, DQE is degraded due to the modest average signal generated per interacting x-ray relative to electronic additive noise levels of ~1000e, or greater. A promising strategy for overcoming this limitation is to introduce an amplifier into each pixel, referred to as the active pixel (AP) concept. Such circuits provide in-pixel amplification prior to readout as well as facilitate correlated multiple sampling, enhancing signal-to-noise and restoring DQE at low exposures. In this study, a methodology for theoretically investigating the signal and noise performance of imaging array designs is introduced and applied to the case of AP circuits based on low-temperature polycrystalline silicon (poly-Si), a semiconductor suited to manufacture of large area, radiation tolerant arrays. Computer simulations employing an analog circuit simulator and performed in the temporal domain were used to investigate signal characteristics and major sources of electronic additive noise for various pixel amplifier designs. The noise sources include photodiode shot noise and resistor thermal noise, as well as TFT thermal and flicker noise. TFT signal behavior and flicker noise were parameterized from fits to measurements performed on individual poly-Si test TFTs. The performance of three single-stage and three two-stage pixel amplifier designs were investigated under conditions relevant to fluoroscopy. The study assumes a 20×20cm2 , 150μm pitch array operated at 30fps and coupled to a CsI:Tl x-ray converter. Noise simulations were performed as a function of operating conditions, including sampling mode, of the designs. The total electronic additive noise included noise contributions from each circuit component. The total noise results were found to exhibit a strong dependence on circuit design and operating conditions, with TFT flicker noise generally found to be the dominant noise contributor. For the single-stage designs, significantly increasing the size of the source-follower TFT substantially reduced flicker noise - with the lowest total noise found to be ~574e [rms]. For the two-stage designs, in addition to tuning TFT sizes and introducing a low-pass filter, replacing a p-type TFT with a resistor (under the assumption in the study that resistors make no flicker noise contribution) resulted in significant noise reduction - with the lowest total noise found to be ~336e [rms]. A methodology based on circuit simulations which facilitates comprehensive explorations of signal and noise characteristics has been developed and applied to the case of poly-Si AP arrays. The encouraging results suggest that the electronic additive noise of such devices can be substantially reduced through judicious circuit design, signal amplification, and multiple sampling. This methodology could be extended to explore the noise performance of arrays employing other pixel circuitry such as that for photon counting as well as other semiconductor materials such as a-Si:H and a-IGZO.

TU-FG-209-03: Exploring the Maximum Count Rate Capabilities of Photon Counting Arrays Based On Polycrystalline Silicon

Purpose: Photon counting arrays (PCAs) offer several advantages over conventional, fluence-integrating x-ray imagers, such as improved contrast by means of energy windowing. For that reason, we are exploring the feasibility and performance of PCA pixel circuitry based on polycrystalline silicon. This material, unlike the crystalline silicon commonly used in photon counting detectors, lends itself toward the economic manufacture of radiation tolerant, monolithic large area (e.g., ∼43×43 cm2) devices. In this presentation, exploration of maximum count rate, a critical performance parameter for such devices, is reported. Methods: Count rate performance for a variety of pixel circuit designs was explored through detailed circuit simulations over a wide range of parameters (including pixel pitch and operating conditions) with the additional goal of preserving good energy resolution. The count rate simulations assume input events corresponding to a 72 kVp x-ray spectrum with 20 mm Al filtration interacting with a CZT detector at various input flux rates. Output count rates are determined at various photon energy threshold levels, and the percentage of counts lost (e.g., due to deadtime or pile-up) is calculated from the ratio of output to input counts. The energy resolution simulations involve thermal and flicker noise originating from each circuit element in a design. Results: Circuit designs compatible with pixel pitches ranging from 250 to 1000 µm that allow count rates over a megacount per second per pixel appear feasible. Such rates are expected to be suitable for radiographic and fluoroscopic imaging. Results for the analog front-end circuitry of the pixels show that acceptable energy resolution can also be achieved. Conclusion: PCAs created using polycrystalline silicon have the potential to offer monolithic large-area detectors with count rate performance comparable to those of crystalline silicon detectors. Further improvement through detailed circuit simulations and prototyping is expected. Partially supported by NIH grant R01-EB000558. This work was partially supported by NIH grant no. R01-EB000558.

A Pixel Analog-Counting Single-Photon Imager With Time-Gating and Self-Referenced Column-Parallel A/D Conversion for Fluorescence Lifetime Imaging

A single-photon, time-gated, $160 \times 120 $ pixel imager is presented for its application in fluorescence lifetime imaging microscopy. Exploiting single-photon avalanche diodes and an extremely compact pixel circuitry—only seven MOSFETs and one MOSCAP—the imager is capable of gathering information about photon position, number, and time distribution, enabling cost-effective devices for scientific imaging applications. This is achieved thanks to the photon counting and time-gating capabilities implemented in the analog domain, which in turn enable a $15\;{\upmu}{\text{m}}$ pixel with a 21% fill-factor. A reconfigurable column circuitry supports both the analog conventional readout and a self-referenced analog-to-digital conversion, able to cancel out the pixel-to-pixel nonuniformities, and speeding up the framerate to 486 fps. The imager, featuring also a delay locked loop to stabilize the internal waveform generation for reliable timing performance, has been implemented in a standard high-voltage $0.35\;{\upmu}{\text{m}}$ CMOS technology. Measurements in a fluorescent lifetime setup have been performed, comparing the results with single-point acquisitions made with commercial time-correlated equipment.

Voltage Mode FPN Calibration in the Logarithmic CMOS Imager

The CMOS active pixel sensor (APS) operating in the logarithmic mode is the most common and useful CMOS wide-dynamic-range imager. Notwithstanding, fixed-pattern noise (FPN) between pixels compromises the quality of the image generated by the focal-plane array. Classical techniques as correlated double sampling do not work properly in this mode, and alternative techniques must be applied in order to calibrate FPN. The alternative techniques require either complex pixel circuitry, or external memory and software level calibration. Purposefully to improve image quality at reduced circuitry complexity, a new calibration technique is proposed that can be applied directly to the basic three-FET APS circuit. The efficacy of the proposed technique was experimentally verified with a small pixel array fabricated in a standard 0.35- $\mu \text{m}$ CMOS technology. The experimental results show a steady FPN attenuation within the whole tested illumination range and the improvement of the signal-to-noise and distortion ratio of the array.

Improving charge-collection efficiency of SOI pixel sensors for X-ray astronomy

We have been developing a new type of active pixel sensor, referred to as “XRPIX” for future X-ray astronomy satellites on the basis of silicon-on-insulator CMOS technology. The problem on our previous device, XRPIX1b, was degradation of the charge-collection efficiency (CCE) at pixel borders. In order to investigate the non-uniformity of the CCE within a pixel, we measured sub-pixel response with X-ray beams whose diameters are 10μmΦ at SPring-8. We found that the X-ray detection efficiency and CCE degrade in the sensor region under the pixel circuitry placed outside the buried p-wells (BPW). A 2D simulation of the electric fields with the semiconductor device simulator HyDeLEOS shows that the isolated pixel circuitry outside the BPW makes local minimums in the electric potentials at the interface between the sensor and buried oxide layers, where a part of charge is trapped and is not collected to the BPW. Based on this result, we modified the placement of the in-pixel circuitry in the next device, XRPIX2b, for the electric fields to be converged toward the BPW, and confirmed that the CCE at pixel borders is successfully improved.

The Method of 2/3 Sampled Sub-Pixel Rendering for AMOLED Display

Due to the capability of the AMOLED (Active matrix organic light emitting diode) display can provide superior color saturation, flexible utilization, slimmer screen profile and more impressive image quality, it has received increasing demand for application in electronic devices. The organic light emitting diode (OLED) is current driven device so that the characteristics of thin field transistor (TFT) influence panel uniformity. Multiple TFT of pixel circuitry has been designed to compensate the Vth (threshold voltage) variations of array process and other driving issues. The fine metal mask (FMM) used in the OLED evaporation is an accurate mask having physical margin limitations in the high PPI (pixel per inch) AMOLED application. This paper details the utilization of a 2/3 sampled sub-pixel rendering (SPR) method to liberate more 50% layout area than the RGB stripe configuration. The proposed algorithm utilizes edge detection and one-side color diffusion to improve display performance as well as RGB stripe compatibility. A 4.65” HD (720 ×1280) AMOLED panel with a 317 PPI retina display was implemented to realize the development of our SPR technology.

Megapixel digital InSb detector for midwave infrared imaging

Since the late 1990s Semiconductor devices (SCDs) has developed and manufactured a variety of InSb two-dimensional (2D) focal plane arrays (FPAs) that were implemented in many infrared (IR) systems and applications. SCD routinely manufactures both analog and digital InSb FPAs with array formats of 320×256, 480×384, and 640×512 elements, and pitch size in the range 15 to 30 μm. These FPAs are available in many packaging configurations, including fully integrated detector-Dewarcooler-assembly, with either closed-cycle Stirling or open-loop Joule-Thomson coolers. In response to a need for very high resolution midwave IR (MWIR) detectors and systems, SCD has developed a large format 2D InSb detector with 1280×1024 elements and pixel size of 15 μm. The ROIC is fabricated in CMOS 0.18-μm technology, that enables the small pixel circuitry and relatively low power generation at the focal plane. The digital ROIC has an analog to digital (A/D) converter per-channel and allows for full frame readout at a rate of 100 Hz. Such on-chip A/D conversion eliminates the need for several A/D converters with fairly high power consumption at the system level. The digital readout, together with the InSb detector technology, lead to a wide linear dynamic range and low residual nonuniformity, which is stable over a long period of time following a nonuniformity correction procedure. A special Dewar was designed to withstand harsh environmental conditions while minimizing the contribution to the heat load of the detector. The Dewar together with the low power ROIC, enable a megapixel detector with overall low size, weight, and power with respect to comparable large format detectors. A variety of applications with this detector make use of different cold shields with different f-number and spectral filters. In this paper we present actual performance characteristics of the megapixel InSb detector and demonstrate its high manufacturability.

Enhancing the Brightness of Parallax Barrier Based 3D Flat Panel Mobile Displays Without Compromising Power Consumption

This paper presents an alternative approach for achieving higher optical efficiency in conventional parallax barrier 3D mobile displays. The method entails modifying and enhancing the protrusion structure of conventional multi-domain vertical alignment (MVA) pixel arrays plus the storage capacitors (Cst) of the pixel circuitry which increase effective pixel transmission area by a factor of 1.07. Hiding the modified storage capacitor under the parallax barrier strip increases the barrier gap or slit size by a factor of 1.52. The result is a structure that enhances mobile displays' optical efficiency by a compounded factor slightly over 60% without compromising power consumption.

An investigation of signal performance enhancements achieved through innovative pixel design across several generations of indirect detection, active matrix, flat‐panel arrays

Active matrix flat-panel imager (AMFPI) technology is being employed for an increasing variety of imaging applications. An important element in the adoption of this technology has been significant ongoing improvements in optical signal collection achieved through innovations in indirect detection array pixel design. Such improvements have a particularly beneficial effect on performance in applications involving low exposures and/or high spatial frequencies, where detective quantum efficiency is strongly reduced due to the relatively high level of additive electronic noise compared to signal levels of AMFPI devices. In this article, an examination of various signal properties, as determined through measurements and calculations related to novel array designs, is reported in the context of the evolution of AMFPI pixel design. For these studies, dark, optical, and radiation signal measurements were performed on prototype imagers incorporating a variety of increasingly sophisticated array designs, with pixel pitches ranging from 75 to 127 microm. For each design, detailed measurements of fundamental pixel-level properties conducted under radiographic and fluoroscopic operating conditions are reported and the results are compared. A series of 127 microm pitch arrays employing discrete photodiodes culminated in a novel design providing an optical fill factor of approximately 80% (thereby assuring improved x-ray sensitivity), and demonstrating low dark current, very low charge trapping and charge release, and a large range of linear signal response. In two of the designs having 75 and 90 microm pitches, a novel continuous photodiode structure was found to provide fill factors that approach the theoretical maximum of 100%. Both sets of novel designs achieved large fill factors by employing architectures in which some, or all of the photodiode structure was elevated above the plane of the pixel addressing transistor. Generally, enhancement of the fill factor in either discrete or continuous photodiode arrays was observed to result in no degradation in MTF due to charge sharing between pixels. While the continuous designs exhibited relatively high levels of charge trapping and release, as well as shorter ranges of linearity, it is possible that these behaviors can be addressed through further refinements to pixel design. Both the continuous and the most recent discrete photodiode designs accommodate more sophisticated pixel circuitry than is present on conventional AMFPIs--such as a pixel clamp circuit, which is demonstrated to limit signal saturation under conditions corresponding to high exposures. It is anticipated that photodiode structures such as the ones reported in this study will enable the development of even more complex pixel circuitry, such as pixel-level amplifiers, that will lead to further significant improvements in imager performance.

Innovative Voltage Driving Pixel Circuit Using Organic Thin-Film Transistor for AMOLEDs

In this work, we propose a novel active-matrix organic light-emitting diode displays (AMOLED) pixel circuit based on organic thin-film transistor (OTFT) architecture, which consisted of four switches, one driving transistor, and a capacitor. The pentacene-based OTFT device possesses a field-effect mobility of 0.1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V ldr s, a threshold voltage of -1.5 V, subthreshold slope of 1.8 V/decade and an on/off current ratio 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . The resultant voltage-driving pixel circuit, named ldquocomplementary voltage-induced coupling drivingrdquo (CVICD), is different from the current-driving scheme and can appropriately operate at low gray level for the low-mobility OTFT circuitry. The current non-uniformity less than 2.9% is achieved for data voltage ranging from 1 to 17 V by SPICE simulation work. In addition, the new external driving method can effectively reduce the complexity of OLED pixel circuitry.

The Image Transceiver Device: Studies of Improved Physical Design.

The Image Transceiver Device (ITD) design is based on combining LCOS micro-display, image processing tools and back illuminated APS imager in single CMOS chip [1]. The device is under development for Head-Mounted Display applications in augmented and virtual reality systems. The main issues with the present design are a high crosstalk of the backside imager and the need to shield the pixel circuitry from the photo- charges generated in the silicon substrate. In this publication we present a modified, “deep p-well” ITD pixel design, which provides a significantly reduced crosstalk level, as well as an effective shielding of photo-charges for the pixel circuitry. The simulation performed using Silvaco software [ATLAS Silicon Device Simulator, Ray Trace and Light Absorption programs, Silvaco International, 1998] shows that the new approach provides high photo response and allows increasing the optimal thickness of the die over and above the 10-15 micrometers commonly used for back illuminated imaging devices, thereby improving its mechanical ruggedness following the thinning process and also providing a more efficient absorption of the long wavelength photons. The proposed deep p-well pixel structure is also a technology solution for the fabrication of high performance back illuminated CMOS image sensors.

A Multispectral Analog Photon-Counting Readout Circuit for X-ray Hybrid Pixel Detectors

In this paper, an all-analog pixel architecture for the readout of X-ray pixel detectors with multiple energy discrimination is proposed. The circuit comprises a self-triggered reset charge amplifier and three distinct channels devoted to the detection on a specific energy band. Each channel is composed of an autocalibrated comparator, an energy window identification logic, and an analog counter with an adjustable dynamic range. A test prototype has been implemented with a standard complementary metal-oxide-semiconductor 0.35-mum technology. The pixel circuitry dissipates 15 muW at 3.3 V, has a noise equivalent charge of 82 e <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> at 200 fF, and allows, on each of the three channels, a dynamic range that exceeds 12 bits. The designed pixel is a square with a 109-mum pitch.