Voltage Mode FPN Calibration in the Logarithmic CMOS Imager

Abstract

The CMOS active pixel sensor (APS) operating in the logarithmic mode is the most common and useful CMOS wide-dynamic-range imager. Notwithstanding, fixed-pattern noise (FPN) between pixels compromises the quality of the image generated by the focal-plane array. Classical techniques as correlated double sampling do not work properly in this mode, and alternative techniques must be applied in order to calibrate FPN. The alternative techniques require either complex pixel circuitry, or external memory and software level calibration. Purposefully to improve image quality at reduced circuitry complexity, a new calibration technique is proposed that can be applied directly to the basic three-FET APS circuit. The efficacy of the proposed technique was experimentally verified with a small pixel array fabricated in a standard 0.35- $\mu \text{m}$ CMOS technology. The experimental results show a steady FPN attenuation within the whole tested illumination range and the improvement of the signal-to-noise and distortion ratio of the array.