Pitch Package Research Articles

In Situ Study on Cu-to-Cu Thermal Compression Bonding

Cu-to-Cu thermal compression bonding (TCB) has emerged as a promising solution for ultrafine pitch packaging in 3D integrated circuit technologies. Despite the progress made by conventional Cu-to-Cu TCB methods in achieving good mechanical strength of the Cu bonds, the bonding processes generally require high temperature and high pressure, which may degrade the performance and reliability of the device. Therefore, it is imperative to investigate the processing parameters to understand the bonding mechanism and achieve effective TCB at a low temperature and low pressure. Here, we developed an in situ TCB technique inside a scanning electron microscope. The in situ TCB method enables a real-time observation of bonding development, which provides critical insights into how the texture and microstructure of Cu bumps may influence the creep and surface diffusion during the bonding process. This work features a strategy to advance our understanding of the bonding mechanisms and provides insight into tailoring the microstructure of Cu for bonding at a low temperature and low pressure.

Novel Electroformed Ni-Au Alloy for High Temperature Semiconductor Test Structures

The ongoing reduction in semiconductor and package pitch leads to challenges for engineering suitable miniaturized test and measurement contact vehicles. Traditional probe card approaches for miniaturization may reach fundamental limits for reduction in scale and pitch. Direct electroforming of conductive electrical contacts at pitch using LIGA technology can allow for direct registration to the test points, the simultaneous formation of all contacts and an opportunity to extend the roadmap for miniaturization. We report here on a new and novel nickel-gold alloy (one to three percent gold by weight) that can be produced by electroforming. This new material was computationally designed to optimize the thermodynamics of the two alloy components such that the alloy has a temperature stable nanocrystalline grain structure which produces highly desirable mechanical and physical properties. Specifically, the alloy is highly electrically and thermally conductive with a resistivity of 10 micro-ohm-cm, while also having a yield strength in excess of 1.5 GPa and an elastic modulus of 130 GPa. This combination of high strength and moderate elastic modulus creates and optimum for mechanical elastic stored energy in a formed contact beam. That is to say, contacts engineered from this material are flexible and strong enough to remain in the elastic regime and have sufficient normal force to maintain low and stable contact resistance, which boosts their long term service life. Further, the alloy shows a fixed cantilever beam bending fatigue limit of more than 1 GPa, further enhancing its viability for long term service. For applications requiring even more strength a 2 GPa yield strength version has also been produced, however this version leads to minor trade-offs in terms of ductility and electrical resistivity and cost. Since these contacts will be used at elevated temperature, the alloy has been designed to be nearly as electrically conductive as plated unalloyed nickel and thermodynamically stable under long term high temperature storage conditions of 400 C. Characterization of the microstructure shows that it is a supersaturated solid solution of Au in a Ni host matrix with evidence of preferential Au segregation to the Ni grain boundaries. Xray diffraction analysis confirms a nanocrystalline grain structure whose size varies as a function of the alloying content. By segregating the Au to the grain boundaries, we extend the electron mean free path and boost electrical conductivity. We also reduce the grain size of the metal leading to improvements in mechanical properties such as yield and fatigue. The electroplating solution is environmentally friendly with no significantly hazardous materials and is REACH compliant. We have shown chemical compatibility with a limited test set of standard photo-resists and masks used for the LIGA process. The plating process is reasonably fast and has shown the ability to plate layers as thick as 400 um without cracks, defects or voids. For some applications it may be desirable to add more plated layers to engineer the contact surface. Gold and other precious metals can be plated on top of the Ni-Au layer with good adhesion and lead to improvements in long term low level contact resistance.

Periodic reverse electrodeposition of (1 1 1)-oriented nanotwinned Cu in small damascene SiO2 vias

It is quite challenging to electrodeposit (111)-oriented nanotwinned Cu in small damascene SiO2 vias because of the existence of the sidewalls of the vias. However, by tailoring electroplating waveforms and temperatures, one can overcome this difficulty. Fine pitch nanotwinned Cu (NT-Cu) with high ratio of (111) surface grains were fabricated using periodic reverse (PR) electrodeposition in damascene SiO2 vias. The PR electroplating parameters for via-filling were adjusted by tuning duty cycle and electrolyte temperatures. The PR current may remove randomly oriented nuclei caused by the sidewall-growing front. Thus, the bottom-up filling of the highly (111)-oriented NT-Cu was achieved. (111) surface ratios greater than 85% and 50% were obtained in 10-µm and 2-µm vias in diameter, respectively. Besides, a mathematical model was proposed to predict the (111) surface ratio of the ultra-fine pitch vias fabricated by PR electrodeposition. This investigation offers a new route to the development of NT-Cu interconnects for ultra-fine pitch packaging.

DM3730 Processor Hardware Debugging on Linux Platform

Texas Instruments fabricated a single chip DM3730 processor with 45nm technology with improved performance. Less power consumption and imrpoved Graphics features are the key parametes of ARM architecture. DM3730 has 1GHz processor with 0.4mm pitch Package on Package. Design of effective system is facilitated by properly debugging the hardware and software. The system for detection of driver fatigue for its implementation requires coming in contact with the camera to capture driver image, speaker for warning messages, GSM module to disseminate SMS, mouse, internet, keyboarb, etc. for installing different packages. In this paper, DM3730 Processor is tested for different peripherals on Linux Platform.This paper is a part of research work on the project “Development of Non-Intrusive Driver Fatigue Detection &Alarming System to evade on road accidents” sanctioned under Early Career Research Award sponsored by Science & Engineering Research Board, Govt. of India, New Delhi at Vignan Institute of Technology & Science, Vignan Hills, Hyderabad.

Study of Electrodeposited High Entropy Single Element (HESE) Cu for Cu-Cu Direct Bonding

Electronic industry had required the smaller size and the higher performance of the device. According to Moore’s law, Technology node which also represents minimum feature size have shrank as rate of 0.7 and density of semiconductor have doubled about every two years. However, decreasing of technology node have been confronted with limit to more dense packaging by two-dimensional large-scale integrated circuits (ICs). Therefore, it is essential that developing of packaging techniques from two-dimensional ICs to three-dimensional ICs. The critical essentials of three-dimensional die stacking technology are TSV (through silicon via) and micro-bump. These technologies have contributed to the appearance of HBM (high bandwidth memory). HBM was packet of the memory, which composed of several stacked layers of the memory chips. Each memory chips were vertically connected by TSV and micro-bump. Thus, HBM have lower RC delay and higher performance of data processing than two-dimensional packaged memory. Even though advance of memory packaging have progressed, the lower pitch size and the higher density of memory chips have been requested ceaselessly in electronics packaging industry. Because the requiring of HPC (high performance computing) in the IT industry field such as AI (artificial intelligence), IOT (internet of things) and VR (virtual reality) have maintained. Especially, in order to accomplish vertical fine height between memory chips in the fine pitch packaging of HBM, micro-bump which consists of copper pillar, deposition of nickel diffusion barrier, and tin-silver or tin-silver-copper based cap have been used. TCB (thermal compression bonding) and reflow process (thermal aging) are typical fabrication process of micro-bump in HBM to combine between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degree Celsius. However, there would be issues of reliability of micro-bump in fine-pitch bonding since intermetallic compound (IMC) formed through the reaction between under bump metallurgy and bump cap at smaller area due to lower pitch. For example, during reaction, if atomic flux difference between top and bottom occurred, kirkendall void which provides track of brittle fracture at IMC layer after reflow process could be formed. Moreover, during reflow, if side wetting of tin atoms from solder occurred, solder depletion can be appeared. Solder depletion also cause a serious issue of reliability of micro-bump. In order to remove these problems and make smaller interconnect, bump cap-less interconnect has been considered. Among many ideas related to bump cap-less interconnect, copper-to-copper direct bonding between copper pillar have been considered due to stability for electromigration, low resistivity and not utilizing IMC. However, more heat energy needs to trigger diffusion. [1] In this study, to decrease the challenges of bump bonding process, copper-to-copper direct bonding was conducted below 300℃. For triggering diffusion between copper below 300℃, high entropy single element (HESE) Cu film have been used. HESE Cu film is electrodeposited film which is reinforced self-annealing property. And HESE Cu films have been fabricated by electrochemical process at condition of low temperature and high current density. The self-annealing property of HESE Cu film arose from high defect density and non-equilibrium grain boundaries at the triple junction. The copper-copper bonding experiments were performed using thermal pressing machine. Thermal parameters and pressure parameters were varied to obtain proper bonded samples. The HESE Cu films were characterized by SEM (scanning electron microscope) and EBSD (Electron backscattering diffraction). The microstructure of HESE Cu films were examined by TEM (transmission electron microscopy). Chen, Chih, Doug Yu, and Kuan-Neng Chen. "Vertical interconnects of microbumps in 3D integration." MRS Bulletin40.3 (2015): 257-263.

The Synergistic Roles of Temperature and Pressure in Thermo-Compression Bonding of Au

Thermocompression bonding is especially important for low pitch (<10 µm) packaging and wafer connections compared to wire bonding, conventional bumps and BGA (Ball Grid Array) technologies. The lack of solder in thermocompression bonding eliminates potential intermetallics at the bond interface leading to increased bonded area fraction, which translates to better quality bonds and higher reliability. In many cases, thermocompression bonding is achieved at higher temperatures and longer times than would be feasible for many applications. A more fundamental understanding of the bonding process, and therefore a path toward lower temperatures and pressures is addressed by studying the surface (interface) diffusion and bonding pressure separately. Comparing these processes separately and the morphology of the bonded interface helps to address which parameters are most important and whether the thermocompression bonding process is simply a sum of the two components or whether there are synergistic effects. This study investigated roles of temperature and pressure separately in diffusion and surface topology changes under conditions that were comparable to those used during thermocompression bonding. This was achieved using Power Spectral Density Function (PSDF) analysis which is based on statistical information extracted from AFM scans. Scans were taken before and after annealing at different temperatures and time; and before and after a surface flattening process at constant temperature for different time periods. Next, we investigated Au-Au bonded interfaces. 1.2 µm thick, sputter-deposited Au films of intermediate roughness (3-5 nm) were bonded at low temperatures (150 °C-250 °C) and different pressures (3 - 14 MPa) for 15 min. The initial peak to valley heights of the unbonded Au films, determined using AFM scans, were 20-30 nm and correlation length was approximately 400 nm. The void morphology was assessed using a combination of plan view and cross section focused ion beam / scanning electron microscopy images. For structures bonded at 150 °C, the void morphology was related to initial roughness in both low and high-pressure cases. While the void length decreased along the interface for all three temperatures at 14 MPa pressure, the void height showed dependence on bonding temperature. Variation in pressure did not affect the results for bonding temperature of 200 °C. Void height increased for bonding at 200 °C and decreased for 250 °C. This decrease in void height was not observed for bonding at 3 MPa and therefore variation in void heights could be attributed to applied pressure at 250 °C. The void lengths for higher pressure samples were approximately half the length of lower pressure samples. These results can be understood with combination of stress-enhanced surface diffusivity due to higher pressure and decreased yield strength and elastic modulus with increasing bonding temperature and pressure. Figure 1

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미세피치 패키지 적용을 위한 thin ENEPIG 도금층의 솔더링 특성

Advancements in Flip Chip Assembly Equipment and Processes

High I/O devices such as microprocessors, applications processors and field programmable gate arrays have transitioned from wire bonding to flip chip interconnect as the I/O densities have increased above 2000. As the bump pitch shrinks the standard process flow for production flip chip processes is challenged. As the bump pitch continues to shrink the accuracy of standard flip chip bonders is not adequate for the fine pitch packages of tomorrow. The options to resolve this issue are extending the accuracy for standard flip chip bonders or moving the assembly of these packages to the inherently more accurate thermo-compression bonders. This paper will discuss the pros and cons of each approach along with showing data which indicates what accuracies are actually required. Although substrate manufacturers have developed low CTE designs which mitigate the warpage caused by the mismatch between the Si die and the substrate as the assembled package travels through the reflow oven, warpage at finer pitches is becoming more and more difficult to control in flip chip processes. Thermocompression (TC) bonding is seen as the next-generation packaging technology that will resolve this issue through local reflow of the solder and elimination of the reflow oven. Despite the tremendous technical and quality advantages of TC bonding, adoption has been limited by the relatively low throughput of the first generation thermocompression bonders. In this paper we describe bonding results obtained with an innovative flip chip bonding method to optimize the process to dramatically improve the throughput by applying flux directly to the substrate rather than dipping the pillars in a bath. A study of this process and comparison of various methods of accomplishing it along with their related costs are discussed in the paper. A second large productivity improvement that is promising by eliminating the need for cooling the die before transferring die that has pre-applied underfill film laminated to it is also studied with productivity models developed. Finally a unique equipment concept for managing the transition from mass reflow to thermo-compression bonding will be presented.

Simulation and measurement of the flip chip solder bumps with a Cu-plated plastic core

With the aim to miniaturize and to reduce the cost, the increasing demand, regarding to advanced 3D-packages as well as high performance applications, accelerates the development of 3D-silicon integrated circuits. The trend to smaller and lighter electronics has highlighted many efforts towards size reduction and increased performance in electronic products. The radio frequency (RF) performances are limited by parasitic effects due to the resistor–inductor–capacitor (RLC) network, between the wire bond connections from the dies to the lead frame. The use of flip-chip bonding technology for very fine pitch packaging allows high integration and limits parasitic inductances. Electromigration (EM) and thermomigration (TM) may have serious reliability issues for fine-pitch Pb-free solder bumps in the flip-chip technology used in consumer electronic products. A possibility to extend the reliability is the use of plastic ball in the solder bumps. Bumps containing a plastic solder balls have an excellent reliability. Using a plastic ball with a low Young modulus, the solder hardness is moderated and the stress on a ball is relaxed. Due to this, the stress does not concentrate on the solder joint which prolongs the lifetime. In this investigation, the thermal–electrical–mechanical coupling of electromigration on bumps containing a plastic solder is studied.

Thermal Aging Effects on the Thermal Cycling Reliability of Lead-Free Fine Pitch Packages

The microstructure, mechanical response, and failure behavior of lead-free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. A direct and deleterious effect on packaging reliability has been observed during elevated temperature isothermal aging for fine-pitch ball grid array (BGA) packages with Sn-1.0Ag-0.5Cu (SAC105), Sn-3.0Ag-0.5Cu (SAC305), and Sn-37Pb solder ball interconnects. Package sizes range from 19 mm with 0.8-mm pitch BGAs to 5 mm with 0.4-mm pitch BGAs with three different board finishes (ImSn, ImAg, and SnPb) previously studied. This paper presents the latest results from an on-going investigation on the aging temperatures were 25 °C, 55 °C, 85 °C, and 125 °C, applied for a period of 12 months. Subsequently, the specimens were thermally cycled from -40°C to 125 °C with 15 min dwell times at the high temperature. Weibull analysis of failures versus cycle number show a ~ 57% reduction in package lifetimes when aged at 125 °C compared to no aging for 19 mm BGAs, for MLFs the degradation is even worse, more than 58% reduction in experiment result. In contrast, the reliability performance of Sn-37Pb is much more stable over long time up to 12 months and temperature. We also study the evolution during isothermal aging, which is one of the major failure modes of solder joints due to its high homologous temperature. The degradation is observed for both SAC alloys on all tested package sizes and board finishes. For the 19 mm SAC105 case, e.g., there was a 53% (57%) reduction of characteristic lifetime at 125 °C for 6 months (12 months) compared to room temperature aging. The trends are in the expected directions; namely, the reliability is reduced when using higher aging temperatures, smaller solder balls, and SAC105. The dominant failure mode can be associated with the growth of Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> intermetallic compounds during the aging, particularly on the pad side.

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

ACF-COG interconnection conductivity inspection system using conductive area

The liquid crystal display (LCD) module package mainly adopts the chip-on-glass (COG) process, in which the driver IC is assembled onto a glass substrate with anisotropic conductive film (ACF). With the higher demand on the display capacity, the stability of COG interconnection under the finer pitch package becomes more important. Currently bump conductive particle counting is used to assess the interconnection quality. However, it cannot verify the interconnection conductivity promptly and would be labor intensive in case that all the bumps were required to inspect. In this paper, a conductivity inspection system based on optical microscope is presented. The resistance prediction model used in the system is based on particle conductive area and has been verified with the published experimental data, which revealed it could calculate the resistance value with the mean of particle conductive area and the number of conductive particles trapped by bump. The model is more accurate than the existed models. A visual inspection system for bump interconnection is developed in this study to compute the particle conductive area and the particle number. The system has been tested with 228 bump images of the ACF-COG modules, and the predicted resistance, 163mΩ, is in the common range. The results show that the conductive area (CA) can be an integral index of bump conductivity and comply with a normal distribution. The resistance model and inspection system provide guidance for the COG interconnection conductivity online testing and will benefit the COG assembly reliability.

The coupling effects of thermal cycling and high current density on Sn58Bi solder joints

Currently, one of the serious challenges in microelectronic devices is the miniaturization trend of packaging. As the decrease of joint dimension, electromigration (EM) and thermomechanical fatigue become critical issues for fine pitch packaging. The independent mechanisms of EM and thermomechanical fatigue are widely investigated and understood. However, the coupling effect of both conditions needs further exploration. The current study established the correlation between resistance and microstructure evolution of solder joint under the combination effect of thermal cycling and high current density and illustrated the different contributions of these two factors to the reliability of the joint through the comparison monopoly tests. The results revealed that cracks had more impact on resistance increase than phase segregation. The resistance evolution could be divided into three stages. First, the resistance mitigated due to the phase coarsening. Second, Joule heating effect made the resistance increase slowly. Third, EM led to the resistance increase rapidly. The high current density can help to improve the reliability of the solder joint under the coupling effect of thermal cycling and EM at the initial stage, but harmful to the consequence process.

An Automatic Bump Detecting System for LCD COG Module Using Fuzzy Reasoning

The Chip-on-Glass (COG) package, which assemblies the driver IC onto a glass substrate with Anisotropic Conductive Film (ACF), is mainly used in the Liquid Crystal Display (LCD) module. With the higher demand of display capacity, the stability of COG interconnection under fine pitch package becomes more important and difficult. Interconnection test and bump microscopic inspection are commonly used to confirm the viability of the interconnections, and are accomplished manually by engineers, which are repetitious and can merely give out the conductive particle numbers in rough. According to the existent ACF-COG interconnection resistance models, the conductivity of bump and pad can be quantitatively analyzed with the conductive particle contact area. In order to implement an automatic system for the bump microscopic inspection to count the particle number and achieve the distribution of contact areas, it is necessity to realize the bump detecting and extracting automatically. In this paper, an automatic bump detecting system using fuzzy reasoning is proposed, and can perform the bump image extraction with a high accuracy. With this system, the particle contact areas and conductive particle number can be analyzed automatically.

A novel polymer technology for underfill

AbstractCapillary type underfill is still the mainstream underfill for mass production flip chip applications. Flip chip packages are migrating to ultra low-k, Pb-free, 3D and fine pitch packages. Underfill selection is becoming more critical. This paper discusses the performance and potential of underfills using a novel organic-inorganic hybrid polymer technology.Compared to eutectic and high lead solder, tin-silver-copper solder has lower C.T.E., higher elasticity and greater brittleness. In light of these properties, it is generally better to select high Tg and lower CTE underfill in order to prevent bump fatigue during reliability testing. Given the brittleness of low-k dielectric layers of flip chips, the destruction of low-k layers by stress inside the flip chip packages has become a major issue. Underfills for low-k packages should have low stress, and the warpage should be small. It is expected that as the low-k trend expands, the underfill is required to provide less stress. Low Tg underfill shows lower warpage. New chemical technologies have been developed to address the needs of underfills for low-k/Pb-free flip chip packages, specifically organic-inorganic hybrid polymer compounds. The organic-inorganic hybrid polymer provides excellent cure properties which enable a balanced combination of low stress and good bump protection. The material properties of the underfill were characterized using Differential Scanning Calorimetry (DSC), Thermo-Mechanical Analysis (TMA), and Dynamic Mechanical Analysis (DMA). A daisy-chained test vehicle was used for reliability testing. A detailed study is presented on the underfill properties, reliability data, as well as finite element modeling results.

Effects of Co additions on electromigration behaviors in Sn–3.0 Ag–0.5 Cu-based solder joint

As the miniaturization trend of electronic packing industry, electromigration (EM) has become a critical issue for fine pitch packaging. The EM effects on microstructure evolution of intermetallic compound layer (IMC) in Sn–3.0 Ag–0.5 Cu + XCo (X = 0, 0.05, 0.2 wt%) solder joint was investigated. Findings of this study indicated that current stressing of Sn–3.0 Ag–0.5 Cu–0.2 Co solder joint with 104 A/cm2 at 50 °C for 16 days, no remarkable EM damages exhibited in solder matrix. Whereas, after current stressing at 150 °C for 1 and 3 days, Sn–3.0 Ag–0.5 Cu specimens showed obvious polarity effect between cathode and anode. Different morphology changes were also observed at both sides. After current stressing for 1 day, two IMC layers, Cu6Sn5 and Cu3Sn, with wave type morphology formed at cathode. Sn phases were also observed inside in the IMC layer. However, only Cu6Sn5 formed in anode. Three days later, Sn phases were found in anode. Besides, Co additions, aging treatment, Ag3Sn, and other IMCs improved the resistance of EM by the evidence of retarding polarity effect.

Impact of Process Improvements on Reliability of RCP Technology During Scale-up

The start-up of the 300mm RCP prototype production line using automated tools was challenged by significant differences in tool sets when compared to the manual and semi-automatic lab based equipment used to develop the baseline RCP fabrication process. Thus, process transfer to automated tools required key parameter adjustments in an attempt to match the process output and reliability performance previously achieved with the 200mm lab based flow. During reliability testing of early parts from the 300mm prototype line, failures in the build-up layers were observed after thermal cycling test. The failure mechanisms were previously observed and resolved during the technology development phase using the 200mm lab based tools. An experiment was developed to identify the root cause of the build-up failures. A single die, 9x9mm, 258 I/O, 0.5mm pitch package with 2 metal routing layers was chosen as a test vehicle for the experiment. Moisture preconditioning and air to air thermal cycling at 2 different conditions followed by electrical test and visual inspection for dielectric cracks were used to gage reliability performance. Several factors were evaluated related to the dielectric and metallization processes as well as the backend interconnect process. The results from the experiment indicated the appropriate tool parameters that allowed the 300mm prototype line process output to closely match that of the 200mm lab based tools. The optimized process combined with the use of an alternate solder material allowed the 300mm RCP prototype line to successfully achieve line certification status and demonstrated RCP reliability performance beyond standards.

Novel Nano-Scale Conductive Films With Enhanced Electrical Performance and Reliability for High Performance Fine Pitch Interconnect

In this paper, a novel nano-scale conductive film which combines the advantages of both traditional anisotropic conductive adhesives/fllms (ACAs/ACFs) and nonconductive adhesives/fllms (NCAs/NCFs) is introduced for next generation high-performance ultra-fine pitch packaging applications. This novel interconnect film possesses the properties of electrical conduction along the z direction with relatively low bonding pressure (ACF-like) and the ultra-fine pitch (< 30 mum) capability (NCF-like). The nano-scale conductive film also allows a lower bonding pressure than NCF to achieve a much lower joint resistance (over two orders of magnitude lower than typical ACF joints) and higher current carrying capability. With low temperature sintering of nano-silver fillers, the joint resistance of the nano-scale conductive film was as low as 10-5 Ohm. The reliability of the nano-scale conductive film after high temperature and humidity test (85degC/85% RH) was also improved compared to the NCF joints. The insertion loss of nano-scale conductive film joints up to 10 GHz was almost the same as that of the standard ACF or NCF joints, suggesting that the nano-scale conductive film is suitable for reliable high-frequency adhesive joints in microelectronics packaging.

Modeling of Radionuclide Migration Through Fractured Rock in a HLW Repository With Multiple Canisters

AbstractAn integrated numerical model for groundwater flow and radionuclide migration analyses in a water-saturated HLW repository with a multiple-canister configuration is developed by incorporating the heterogeneity of fractured host rock based on the previous multiple-canister model (MCFT2D [1, 2]). The current model incorporates i) heterogeneity of the fractured host rock represented stochastically by discrete fractures, ii) disposal-pit vertical emplacement concept, iii) representation of the waste package consisting of a waste canister and a bentonite-filled buffer, and iv) a user-determined repository configuration of multiple canisters using the repository parameters such as disposal tunnel spacing, waste package pitch, tunnel diameter, the number of tunnels in a repository, and the number of canisters in a tunnel. The current model can facilitate investigations into the effects of heterogeneous fractured host rock on water flow and nuclide migration for the different configurations of multiple canisters, as well as optimization of the repository design parameters in terms of release of nuclides from the repository.

Ultra fine pitch flat panel display packaging using 3 μm conductive particles

In this research, dependency of the contact resistance on the hardness of the gold bump and process parameters such as the contact area and the load pressure of the extra fine pitch chip-on-glass (COG) flat panel display (FPD) packaging is investigated. The FJ2530 anisotropic conductive film (ACF) by Sony Inc. containing the currently smallest 3 μm conductive particles is implemented to conduct the experiments. Feasibility of the 3 μm ACF in ultra-fine pitch COG applications is further examined. From the experimental results, we found that no special process is required to obtain a satisfied contact resistance for the ultra fine pitch packaging based on the 3 μm conductive particles. It can be concluded that the combination of the 3 μm conductive particles and the IC gold bumps with hardness 70 Hv can lead to a miniaturized device with less cost. For mass production, test sample with pitch space being larger than 10 μm is suggested to retain a better reliability.