Pitch Ball Grid Array Package Research Articles

Parametric study of thermally induced warpage of FpBGA package using finite element methods

Warpage is considered to be the major concern in ensuring the reliability and manufacturability of electronic package because a flat package is crucial for a successful formation of board level assembly process. Warpage is the out of plane displacement which is a resultant of difference in co-efficient of thermal expansion (CTE) between the adjoining packaging materials. Enormous warpage may lead to occurrence of faulty joints such as open connections, mis-shaped joints, and loss of package board-level reliability under manufacturing, thermal loading process, shock and vibration. In this paper, a Fine pitch ball grid array Package (FpBGA) which is a prominent type of electronic package offering solution for downsizing of electronic components such as mobiles and camcorders has been choose for study. Warpage of FpBGA was simulated from post cure temperature to reflow temperature using Finite Element Methods. A static thermal analysis was carried out using ABAQUS software and a parametric study was done to investigate the effect of material properties and geometric properties in minimizing the warpage. Materials properties such as CTE, Elastic modulus of substrate and die, geometric properties like thickness of die and substrate were chosen for study.

A Current Probe for Measuring the Individual Ball Current in a Ball–Grid–Array Packaged Device

A current probe was designed to measure ball currents in a Ball-Grid-Array (BGA) package via magnetic induction. This probe, which is based on a Rogowski coil structure, is manufactured in a four-layer flex circuit. Very tiny feature sizes, such as 2 mil buried micro vias and 2 mil trace widths/clearances, push the limit of the flex-circuit fabrication process technology. This design allows the current of a ball in a 1-mm pitch BGA package to be measured. It can also be migrated to package with smaller pitch if the fabrication process allows. This probe is practical for engineering applications as a result of three major advantages. It operates in a broadband from 10 to 3 GHz. The probe can be relocated to different balls and no special printed circuit board is needed. The probe shows acceptable shielding effectiveness of the unwanted fields caused by adjacent balls or sources. In conjunction with both a differential amplifier and an active oscilloscope probe, the output signal is sufficiently amplified to overcome the noise figure of the oscilloscope. This allows time domain measurements. Moreover, a frequency-domain data processing program was developed for correcting the probe's frequency response and reconstructing the time domain waveform. The probe is validated against analytical calculation, and full-wave simulation; it is characterized with the aid of circuit modeling. The probe's functionality is finally demonstrated with a field-programmable-gate-array test board.

Development of a Cu/Low-$k$ Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications

Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips into one package becomes a popular choice. In this paper, the development of a three-die stack fine pitch ball grid array package is reported. A 65 nm Cu/low-k die is used as the bottom die in the package to increase the speed of the chip with multilayer interconnect structures. Compared to the conventional dielectrics, low-k materials are softer and less resistant to thermal-mechanical stress induced by packaging processes. In this paper, finite element analysis is performed to minimize the stress in low-k layers and to address the low-k delamination issue. In the dicing evaluation, comparison among straight cut, bevel cut and two-step cut was performed in terms of die strength and chipping results. It is found that the bevel cut dicing method is the best dicing method. The die attach process (especially wire embedded film process) is optimized to ensure that no voids are present in the die attach materials after the bonding process. The ultralow loop wire bonding process (50 μm) is also well established. The maximum wire sweep for all test vehicles is less than 10% in the molding process. Finally, all samples for test vehicle 1 were shown to have successfully passed JEDEC component level tests such as thermal cycling for 1000 cycles (-40°C to 125°C) and high temperature storage (HTS at 150°C) for 1000 h.

Impact of isothermal aging on fine pitch BGA packages with Sn-Ag-Cu solder interconnects

The interaction between isothermal aging and long-term reliability of fine pitch ball grid array (BGA) packages with Sn-3.0Ag-0.5Cu (wt%) solder ball interconnects are investigated. In this study, 0.4mm fine pitch packages with 0.3mm diameter Sn-Ag-Cu solder balls are used. Two different die sizes and two different package substrate surface finishes are selected to compare the internal strain impact and alloy effect, especially the Ni effect during thermal cycling. To see the thermal impact on the thermal performance and long-term reliability, the samples are isothermally aged and thermal cycled from 0 to 100°C with a 10minute dwell time. Based on weibull plots for each aging condition, the lifetime of the package reduced approximately 44% with 150°C aging precondition. The microstructure evolution is observed during thermal aging and thermal cycling with different phase microstructure transformations between electrolytic Ni/Au and OSP surface finishes, focusing on the microstructure evolution near the package side interface. Different mechanisms after aging at various conditions are observed, and their impacts on the fatigue life of solder joints are discussed.

Investigation of mechanical shock testing of lead-free SAC solder joints in fine pitch BGA package

The lead-free Sn–Ag–Cu (SAC 305/405) solder that replaced the tin–lead eutectic solder tends to be more brittle in nature due to high stiffness and excessive solder interfacial reactions. This leads to higher occurrences of solder joints failure during surface mount assembly and handling operations as a result of PCB bending, shock impact and drop. In this work, mechanical tests simulating the shock impact were conducted on lead-free SAC of different weight percentages. These SAC materials were prepared for use in the solder joints of fine pitch ball grid array (BGA) components which were mounted onto the motherboard. After the mechanical shock tests, strain measurements were performed on the BGA components to gauge the solder joint integrity, which was shown to be related with the formation of intermetallics in the bulk and at the interface of the SAC solder. The ball pull tests were conducted to determine both the bulk and interfacial strength and the solder joint fracture, which was classified as either mode 1, 2 or 3. A correlation was made between the silver (Ag) and copper (Cu) weight percentages with the metallurgical reactions.

Realization of high sensitivity displacement field from moiré interferometer with rough phase shifting mechanism and pattern matching technique

In this study, phase shifting method is used to modify moiré system into micro moiré interferometer which can measure displacement field with highly improved sensitivity. Apart from existing micro moiré technique, a low cost and less precise translation stage with rough resolution (10 μm resolution) is adapted for the phase shifter. Least square algorithm is applied to estimate the arbitrary phase shifted amount and to minimize the errors induced by lowering the cost. Moreover, specimen grating is phase shifted instead of reference grating which enables simple construction from given moiré system. To compensate for rigid body in-plane translation of specimen that may occur during phase shifting, pattern matching algorithm is put into practice to ensure pixel correspondence for each phase shifted images. To verify the newly constructed micro moiré technique, local displacement fields of Fine pitch Ball Grid Array package and Wafer Level Chip Size Package with elevated sensitivity up to 26 nm per fringe was acquired.