Pipelining Technique Research Articles

Enhanced TACIT Encryption and Decryption Algorithm for Secured Data Routing in 3-D Network-on-Chip based Interconnection of SoC for IoT Application

This paper presents an enhanced TACIT (E-TACIT) encryption and decryption routing technique. It protects from illegal extraction of secret data in three-dimensional (3−D) routers of Network-on-Chip (NoC) by generating HASH function-based key. The E-TACIT technique solves keys and blocks size limitation of existing anticipated methods, as it has been designed for ‘n’ bit key and ‘n’ block size. Therefore, it secures data while routing process in 3−D NoC based interconnected System-on-chips (SoCs) for Internet-of-Thing (IoT) application. The NoC based interconnection provides high scalability and requires low energy consumption for data processing than conventional bus-based SoCs. The E-TACIT has been examined for Moving Picture Experts Group (MPEG-4). The technique synthesized using Vivado 2016.2 and implemented on ZYNQ XC7Z020-CLG484 FPGA for 1024 bits and verified using a network simulator. Here, we have also incorporated pipelining, re-trimming, and clock gating techniques in the design and used Dual-Port RAM during verification, which helps in achieving low latency and high throughput and occupy less silicon in comparison to Data Encryption Standard (DES) and Advanced Encryption Standard (AES) techniques.

Studies on distributed Brillouin scattering technique for monitoring of lifeline structures

Pipeline networks are the most efficient means for transporting large quantities of oil and gas through large distances. These pipelines cross different geographical terrains and are subjected to different man made and natural hazards. Also these pipelines are prone to failures due to aging. Leakage in pipelines, particularly those carrying fuels is very dangerous as it leads to environmental pollution and also fatal accidents. The pipeline infrastructure industry has seen extensive growth in the recent years and hence there is a huge necessity for the development of real time pipeline monitoring technologies for reliable and safe operation of pipeline networks. Presently, health assessment and real time monitoring is gaining popularity among the researchers as it provides quality information on the performance of complex systems during its operation. There are different types of technologies developed for real time monitoring of pipelines using distributed fiber optic sensors, acoustic emission techniques and guided wave techniques. This paper presents in detail the theory of brillouin based distributed optical fiber sensing technology and studies carried out using the distributed fiber sensing for monitoring strain and temperature profiles through laboratory experimental investigations. Experimental investigations were carried out by simulating leakage in pipelines filled with hot water to study the performance of the distributed fiber sensors. Leakage was simulated in pipelines by drilling small holes at predetermined locations. Detection time was from 5 to 10 minutes and location of leakage was exactly detected with the spatial resolution of 80 mm. Brillouin based distributed fiber sensing system is a promising technique for monitoring long distance pipelines.

A Re-examination of Dichoptic Tone Mapping.

Dichoptic tone mapping methods aim to leverage stereoscopic displays to increase visual detail and contrast in images and videos. These methods, which have been called both binocular tone mapping and dichoptic contrast enhancement, selectively emphasize contrast differently in the two eyes’ views. The visual system integrates these contrast differences into a unified percept, which is theorized to contain more contrast overall than each eye’s view on its own. As stereoscopic displays become increasingly common for augmented and virtual reality (AR/VR), dichoptic tone mapping is an appealing technique for imaging pipelines. We sought to examine whether a standard photographic technique, exposure bracketing, could be modified to enhance contrast similarly to dichoptic tone mapping. While assessing the efficacy of this technique with user studies, we also re-evaluated existing dichoptic tone mapping methods. Across several user studies; however, we did not find evidence that either dichoptic tone mapping or dichoptic exposures consistently increased subjective image preferences. We also did not observe improvements in subjective or objective measures of detail visibility. We did find evidence that dichoptic methods enhanced subjective 3D impressions. Here, we present these results and evaluate the potential contributions and current limitations of dichoptic methods for applications in stereoscopic displays.

WITHDRAWN: A faster approach to add Multi operands using unified pipelining technique

The article presents novel multi operand adder using seamless pipelining concept. The proposed adder synthesized using Xilinx 14.2 software and implemented on Virtex-5(xc5vfx30t-3ff665) device. Delay and device utilization parameter i.e. number of slice LUTs are compared with carry propagate adder (CPA), carry save adder (CSA), and conventional pipelined adder. And it shows our method gives the highest frequency of operation among all the methods.

Optimized Implementation of Gift Cipher

The Internet of Things is an emerging area which deals with transfer of the data through the wired or wireless network. The prime thing that needs to be addressed in this is the security of the data that must be transferred within the optimized time limit. In this paper, throughput and time delay are need to be considered for the optimized data transfer and while concentrating on this, there is a possibility of allowing the data to be vulnerable to attacks. Security algorithms currently available may be adequate for the wired system and not as the same for wireless scenario. PRESENT cipher is a one of the popular cryptosystem used in wireless which falls under the light weight cryptography category. Gift cipher is an enhanced version of PRESENT cipher. Which aims that maximizing the throughput. In this, iteration structure used for encryption. This can still be improved and optimized in terms of increased data rate and reduced time delay. In this paper, implements the optimization technique of the existing GIFT cipher and throughput is considered as the performance metrics. Pipeline and sub-stage pipeline techniques are used for enhancing the architecture.

Assessment of the Acoustic Reflectometry Technique to Detect Pipe Blockages

Abstract Flow assurance is an important aspect of deepwater pipeline design and operation since one of the critical issues is the eventual initiation and growth of hydrate or paraffin blockages under certain conditions. Another relevant problem is the incidence of inorganic scale deposition in oil well production tubes during operation. Offshore operators can obtain enormous benefits if information regarding the position and extent of an eventual blockage is available since mitigation measures can be optimized. This work deals with experimental and numerical simulations of an acoustic system to identify and measure blockages. The technique uses a short duration acoustic pulse that is injected into the pipe. When the pulse encounters an impedance discontinuity, a portion is reflected toward the acoustic source. The analysis of the measured signal reflections can provide valuable data related to the location and size of the blockages. An experimental setup with a steel pipe of 4 in. internal diameter and length of 100 m was developed to evaluate the suitability of the technique for gas pipelines. In parallel, finite element analyses were performed using the commercial software abaqus to simulate the same physical parameters. The experiments were numerically reproduced with good correlation proving the potential of the technique. Subsequently, a parametric study was carried out to examine the acoustic detection capability using different blockage types. Finally, a prototype of the acoustic reflectometry detection system was developed and tested in a full-scale onshore water-filled pipeline to show the feasibility of the method for detecting blockages.

Design of High Speed Asynchronous Pipelined FIR Filter Using Quasi Delay Insensitive Reduced Slack Pre-Charged Half Buffer

ABSTRACT Asynchronous design is progressively becoming more attractive alternative to synchronous design because of its potential for high-speed and low-power. The pipelining technique is very effective for synchronous digital designs. This paper proposes the design of pipelined Finite Impulse Response (FIR) filter using asynchronous quasi-delay-insensitive (QDI) template based on Reduced Slack Pre-Charged Half Buffer (RSPCHB). Both synchronous and asynchronous pipelined FIR filter have been designed using TSMC 0.18-µm CMOS technology. HSPICE simulation shows that the speed of the asynchronous system has been improved 12 times with 2 times increased area over synchronous design.

Design and Analysis of (5, 10) Regular LDPC Encoder Using MRP Technique

An efficient compact encoding process with the pipelining design of Low Density Parity Check (LDPC) Encoder with a two stage, three stage and Maximal Rate Pipelining (MRP) structures are proposed in this work. Comparatively, LDPC encoding is more complex than decoding. The complexity mainly referred to the mathematical computation involved in the design of LDPC encoder. There are several methods used to design reduced parity check matrix, one of the methods involved is the Gauss Elimination method. Conventional and wave pipelining techniques are implemented to overcome the disadvantages of the area, latency, etc., The designed architectures are synthesized in SYNOPSYS tool and implemented in the XC3S-250E FPGA device. The overheads like power and area are efficiently reduced by wave pipelining and their efficiency can be proved by synthesis report. This showcases that the LDPC Encoders require less memory by using MRP structure.

Wave Pipelined VLSI Architecture for a Viterbi Decoder Using Self Reset Logic with 0.65nm Technology

In 3G mobile terminals the Viterbi Decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. A low power Viterbi decoder is designed in circuit level using self reset logic and wave pipelining technique is implemented for high speed operation. The Viterbi decoder consists of four units like branch metric unit, add compare and select unit and the survivor path memory unit. All these units are designed using the self reset logic and wave pipelining, and simulated with its layout using MICROWIND TOOL in the 0.65nm technology, 1.8V Vdd and at a frequency of 10GHz. The simulation result shows that the power consumption is reduced by 70.55% and the speed of the circuit is increased by 45.83% compared to the Single Rail Domino Logic for constraint length of K =3 to 7.

Heart Failure Detection Using Quantum‐Enhanced Machine Learning and Traditional Machine Learning Techniques for Internet of Artificially Intelligent Medical Things

Quantum‐enhanced machine learning plays a vital role in healthcare because of its robust application concerning current research scenarios, the growth of novel medical trials, patient information and record management, procurement of chronic disease detection, and many more. Due to this reason, the healthcare industry is applying quantum computing to sustain patient‐oriented attention to healthcare patrons. The present work summarized the recent research progress in quantum‐enhanced machine learning and its significance in heart failure detection on a dataset of 14 attributes. In this paper, the number of qubits in terms of the features of heart failure data is normalized by using min‐max, PCA, and standard scalar, and further, has been optimized using the pipelining technique. The current work verifies that quantum‐enhanced machine learning algorithms such as quantum random forest (QRF), quantum K nearest neighbour (QKNN), quantum decision tree (QDT), and quantum Gaussian Naïve Bayes (QGNB) are better than traditional machine learning algorithms in heart failure detection. The best accuracy rate is (0.89), which the quantum random forest classifier attained. In addition to this, the quantum random forest classifier also incurred the best results in F1 score, recall and, precision by (0.88), (0.93), and (0.89), respectively. The computation time taken by traditional and quantum‐enhanced machine learning algorithms has also been compared where the quantum random forest has the least execution time by 150 microseconds. Hence, the work provides a way to quantify the differences between standard and quantum‐enhanced machine learning algorithms to select the optimal method for detecting heart failure.

Hardware Pipelining of Repetitive Patterns in Processor Instruction Traces

Dynamic partitioning is a promising technique where computations are transparently moved from a Gene-
 ral Purpose Processor (GPP) to a coprocessor during application execution. To be effective, the mapping
 of computations to the coprocessor needs to consider aggressive optimizations. One of the mapping opti-
 mizations is loop pipelining, a technique extensively studied and known to allow substantial performance
 improvements. This paper describes a technique for pipelining Megablocks, a type of runtime loop deve-
 loped for dynamic partitioning. The technique transforms the body of Mega-blocks into an acyclic dataflow
 graph which can be fully pipe-lined and is based on the atomic execution of loop iterations. For a set of 9 ben-
 chmarks without memory operations, we generated pipelined hardware versions of the loops and esti-mate
 that the presented loop pipelining technique increases the average speedup of non-pipelined coprocessor
 accelerated designs from 1.6× to 2.2×. For a larger set of 61 benchmarks which include memory operations,
 we estimate through simulation a speedup increase from 2.5× to 5.6× with this technique.

Design of Convolutional Neural Network with Cuckoo Search Algorithm for Super-Resolution UHD Systems on FPGA

Ultra high definition (UHD) video is considered as a technology that generates a video image with a resolution 16 times as many pixels as high definition television. Extensive and complex computational difficulties are there to generate a video in super-resolution (SR). Some extensive floating-point computations are needed for the direct implementation of area-pixel scaling, which is a factor for calculating one target pixel. In this paper, a hybrid Convolutional Neural Network and Cuckoo Search (CNN-CS) algorithm are proposed, which can replace the large scale of complex training and time-consuming machine learning technique. Cuckoo Search (CS) algorithm is based on bird’s levy-flight approach that can optimize the CNN. CS forecasting model isolates the redundant or irrelevant image patches and, therefore, it reduces the required memory space. The SR is performed effectively in hardware with less hardware utilization and memory space, where LR input data are processed line-by-line using the proposed hybrid CNN-CS algorithm. To optimize the design constraints, CS forecasting model estimates the required patches. Parallel sub pipeline (PSP) technique improves the parallelism process thereby reducing the computational complexity and improving the throughput rate and speed of execution. Finally, the proposed hybrid CNN-CS SR design is coded in Verilog HDL and is implemented with the XCKU040 FPGA device. To validate the proposed CNN-CS SR algorithm, standard datasets, such as Set-5, Set-14, BS-100 and Urban-100, are used. The visual quality of the proposed CNN-CS SR design is evaluated by the standard evaluation metrics such as peak signal-to-noise ratio (PSNR) and SSIM. The proposed hybrid CNN-CS SR design is compared with the existing state-of-the-art techniques both qualitatively and quantitatively. Experimental results demonstrate that the proposed method improved the throughput of 42.83%, memory space and power consumption are reduced to 16.16%, 63.81%, respectively, over the existing techniques.

A failure prediction model for corrosion in gas transmission pipelines

Transmission pipelines comprise a major part of a gas network, conveying natural gas within jurisdictions, and across international boundaries. In the United States, more than 10,000 failure incidents have been reported in gas transmission pipelines in a 20-year period from 1996 to 2016 leading to a cumulative property damage of more than $748 million. Among different failure sources, corrosion is ranked as the most frequent one, corresponding to approximately a quarter of total failures. Though in-line inspection is counted as the most frequently applied corrosion monitoring technique for oil and gas pipelines, it imposes considerable costs due to the necessity of implementing frequent inspections using smart devices. For this reason, several failure prediction models have been developed to estimate the corrosion failure. However, the majorities of these prediction models rely solely on experimental tests or limited historical records which undermine the extent of their applicability and ignore pipeline environmental and geographical circumstances. The objective of this research is to develop failure prediction models for external corrosion in underground gas transmission pipelines by considering both conventional and environmental/geographical variables. For this objective, multiple regression analysis was performed on the accessible historical data reported for gas transmission pipelines. Two main climate regions of Great Plains and South East in the US were selected, and their corresponding failure prediction models were developed. Such development was based on a step by step procedure analyzing different scenarios. Considering diagnostic measures, null hypothesis and residual analysis, scenario 3 was selected as satisfactory. The validation tests of the developed models present a root mean square error (RMSE) of 0.04 and 0.07 and R-Sq of 0.93 and 0.75, respectively. The results of this research can be applied in maintenance planning of gas transmission pipeline to estimate the critical time in which a pipeline may encounter external corrosion failure, and to accordingly schedule the maintenance activities.

Evaluating a Dynamic and a Modulo Scheduling-based Static Approach for Configuration Generation in CGRA Accelerators

With the increasing complexity of the applications, there is an urgent need for solutions to improve the performance of these applications. It is noted that the loops present in some of them are responsible for up to 71% of the code execution time. So, optimizing the loop’s execution it is possible to accelerate the execution of the whole application. This performance gain can be obtained with the use of software pipelining. This work proposes RENOIR, a tool that uses software pipelining technique through the implementation of the modulo scheduling algorithm, developed in software, that acts in the generation of configurations for a coarse-grained reconfigurable architecture (CGRA). RENOIR is implemented in a compiler, which receives an application and generates a code that can run on a gem5 implementation of a CGRA that includes a RISC-V microprocessor and a thin reconfigurable array. The results show that all the applications tested achieved an improvement in performance, reaching a gain of 2,32x in certain applications.

Generation-Level Parallelism for Evolutionary Computation: A Pipeline-Based Parallel Particle Swarm Optimization.

Due to the population-based and iterative-based characteristics of evolutionary computation (EC) algorithms, parallel techniques have been widely used to speed up the EC algorithms. However, the parallelism usually performs in the population level where multiple populations (or subpopulations) run in parallel or in the individual level where the individuals are distributed to multiple resources. That is, different populations or different individuals can be executed simultaneously to reduce running time. However, the research into generation-level parallelism for EC algorithms has seldom been reported. In this article, we propose a new paradigm of the parallel EC algorithm by making the first attempt to parallelize the algorithm in the generation level. This idea is inspired by the industrial pipeline technique. Specifically, a kind of EC algorithm called local version particle swarm optimization (PSO) is adopted to implement a pipeline-based parallel PSO (PPPSO, i.e., P3SO). Due to the generation-level parallelism in P3SO, when some particles still perform their evolutionary operations in the current generation, some other particles can simultaneously go to the next generation to carry out the new evolutionary operations, or even go to further next generation(s). The experimental results show that the problem-solving ability of P3SO is not affected while the evolutionary speed has been substantially accelerated in a significant fashion. Therefore, generation-level parallelism is possible in EC algorithms and may have significant potential applications in time-consumption optimization problems.

Design and implementation of pipelined and parallel AES encryption systems using FPGA

<p><span>The information security is one of the most important issues in the design of any communication network.One of the most common encryption algorithms is the Advanced Encryption Standard (AES).The main problem facing the AES algorithm is the high time consumption due to the large number of rounds used for performing the encryption operation. The more time the encryption system consumes to encrypt the data, the more chances the hackers have to break the system.This paper presents two effective algorithms that can be used to solve the mentioned problem and to achieve an effective processing time reduction using pipelined and parallel techniques to perform the encryption steps. These algorithms are based on using certain techniques to make the system able to encrypt many different states (the data will be encrypted) in the same time with no necessity to wait for the previous encryption operation to be completed. These two algorithms are very effective especially for big data size. This paper describes in detail the AES encryption system algorithm and a detailed explanation for the proposed algorithms. Moreover, the research shows the implementation of the three algorithms: the traditional, the pipelined, and the parallel algorithms, and finally a comparison between them.</span></p>

High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications

This study presents a high throughput field-programmable gate array (FPGA) implementation of advanced encryption standard-128 (AES-128). AES is a well-known symmetric key encryption algorithm with high security against different attacks that are widely used in different applications. The main goal of this study is to design a high throughput and FPGA efficiency (FPGA-Eff) cryptosystem for high-traffic applications. To achieve high throughput, loop-unrolling, inner and outer pipelining techniques are employed. In AES, substitution bytes (Sub-Bytes) is one of the costly functions that occupy a large number of resources and has a large delay. To reduce the area of Sub-Bytes, new-affine-transformation, which is the combination of inverse isomorphic and affine transformation, is proposed and employed. Besides that, AES has been modified according to the proposed architecture. For the first nine rounds, Shift-Rows and Sub-Bytes have been exchanged, and Shift-Rows is merged with Add-Round-Key. To make an equal latency between stages, Mix-Columns is divided into two different stages. AES is implemented in counter mode on Xilinx Virtex-5 using VHDL. The proposed implementation achieves a throughput of 79.7 Gbps, FPGA-Eff of 13.3 Mbps/slice, and frequency of 622.4 MHz. Compared to the state-of-the-art work, the proposed design has improved data throughput by 8.02% and FPGA-Eff by 22.63%.

AI detection of M. Tuberculosis pathogens using Generative Adversarial Network (GAN) analyses

Abstract Background Rapid identification of pathogens is critical to outbreak detection and sentinel surveillance; however most diagnoses are made in laboratory settings. Advancements in artificial intelligence (AI) and computer vision offer unprecedented opportunities to facilitate detection and reduce response time in field settings. An initial step is the creation of analysis algorithms for offline mobile computing applications. Methods AI models to identify objects using computer vision are typically “trained” on previously labeled images. The scarcity of labeled image-libraries creates a bottleneck, requiring thousands of labor hours to annotate images by hand to create “training data.” We describe the applicability of Generative Adversarial Network (GAN) methods to amass sufficient training data with minimal manual input. Results Our AI models are built with a performance score of 0.84-0.93 for M. Tuberculosis, a measure of the AI model's accuracy using precision and recall. Our results demonstrate that our GAN pipeline boosts model robustness and learnability of sparse open source data. Conclusions The use of labeled training data to identify M. Tuberculosis developed using our GAN pipeline techniques demonstrates the potential for rapid identification of known pathogens in field settings. Our work paves the way for the development of offline mobile computing applications to identify pathogens outside of a laboratory setting. Advancements in artificial intelligence (AI) and computer vision offer unprecedented opportunities to decrease detection time in field settings by combining these technologies. Further development of these capabilities can improve time-to-detection and outbreak response significantly. Key messages Rapidly deploy AI detectors to aid in disease outbreak and surveillance. Our concept aligns with deploying responsive alerting capabilities to address dynamic threats in low resource, offline computing environs.

A Hybrid-CPU-FPGA-based Solution to the Recovery of Sha256crypt-hashed Passwords

This paper presents an accelerator design for the password recovery of sha256crypt based on hybrid CPU-FPGA devices. By applying the brute-force attack computation model proposed in this paper, we decompose the sha256crypt function into two types of operations, namely the data dispatching and the block transforming. The data dispatching operation generates message blocks and the block transforming operation transforms message blocks into digests. These two operations are efficiently accelerated by the customized data dispatch unit and the pipelined block transform unit, respectively. Difficulties of adopting the pipeline technique are addressed also with the following techniques. The group scheduling is used to solve the data dependency that stalls the pipeline. The look-ahead execution eliminates the uncertainty of the execution path. The data path pruning and spatial-temporal multiplexing reduce the resource overhead of non-computing units.The proposed accelerator design is implemented and evaluated on the Xilinx Zynq-7000 XC7Z030-3 SoC. Our experimental results show that the proposed accelerator can improve energy efficiency by 2.54x over the state-of-the-art password recovery tool Hashcat running on an NVIDIA GTX1080Ti GPU. Compared with the pure FPGA-based implementation in John-the-Ripper, the proposed accelerator improves energy efficiency by 1.64x and improves resource efficiency by 1.69x.

Review of high-speed phase accumulator for direct digital frequency synthesizer

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.