Pipeline Depth Research Articles

CORDIC‐based window implementation to minimise area and pipeline depth

Filtering is one of the most important modules in signal processing paradigm. This study presents a field-programmable gate array implementation of various window functions using coordinate rotation digital computer (CORDIC) algorithm to minimise area-delay product. First, the authors modify the Taylor series approximation order used in the scaling-free CORDIC, to completely eliminate the scale-factor and, yet, preserve the range of convergence spanning across the entire coordinate space. Secondly, the authors propose a new generalised technique for micro-rotation sequence identification to reduce the number of iterations required by the pipelined CORDIC processor. Then, this circular CORDIC processor is used to realise window functions. The existing window architecture uses a linear CORDIC processor in series with circular CORDIC processor, resulting in long pipeline. The authors replace the linear CORDIC with multiple optimised shift-add networks to reduce area and pipeline depth. As a result, the proposed window architecture, on an average requires approximately 64.34% less pipeline stages and saves up to 48% area. The authors have designed the processor to implement Hanning, Hamming and Blackman window families. The implementation of the proposed architecture is detailed in this study.

Design and evaluation of fine‐grain‐mode transition method based on dynamic memory access analysing for variable stages pipeline processor

This study proposes a fine-grain-mode transition method for variable stages pipeline (VSP) processor. The method is based on dynamic memory access analysing and it reduces energy consumption. A VSP processor varies the pipeline depth dynamically according to workload. When the workload is heavy, the processor shifts into a high-speed mode that drives a deep pipeline at a high clock frequency. When the workload is light, the processor shifts into a low-energy mode that unifies pipeline stages to make the pipeline shallower and drives it at a low clock frequency. The conventional mode transition method cannot follow sharp workload changes because it takes a long time to predict workload. The fine-grain pipeline depth control, this study proposes, is based on a high-speed workload prediction mechanism using memory access frequency, and it uses a novel method to conceal the overhead because of changing the pipeline depth. Simulation results show that the authors approach can reduce the energy-delay product 10% below what it would be with the conventional approach.

Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip

Increased energy consumption in processors caused by performance enhancement has recently become a critical problem. Many current processors employ dynamic voltage and frequency scaling (DVFS) which dynamically lowers the supply voltage and clock frequency in order to reduce energy consumption. However, it is difficult to deliver fine-grain energy optimization by using DVFS. Since a voltage regulator takes a long time for scaling the voltage and charging/discharging a power line has a large energy overhead, the useful interval of DVFS is limited to coarse-grain. To optimize energy consumption at fine-grain interval, we have proposed a variable stages pipeline (VSP) processor. VSP reduces energy consumption by dynamically varying the pipeline depth to suitable pipeline depth according to behavior of a running program. VSP can obtain finer-grained energy reduction than DVFS because pipeline scaling only requires a small overhead. In this paper, we fabricated a VSP processor chip using 180 nm technology and evaluated energy consumption of the chip. We present that the fabricated VSP chip dynamically varies the pipeline depth while a program is running and reduces the energy consumption at shorter interval than DVFS. We also analyze how to optimize the energy consumption according to system demand. Our analysis result shows that the VSP can adjust the energy consumption in the same manner for diverse program phases. Â

The New Magnetic Survey Method for Underwater Pipeline Detection

Magnetic survey has been applied to detect underwater pipeline location, tracking and depth more and more nowadays. In order to detect such smaller targets, besides the application of high-precision magnetometer detector, an effective method especial for underwater pipeline is needed. This paper is to research the magnetic survey method for detecting the underwater pipeline. In terms of its magnetic anomaly characteristic, magnetic sensor array and magnetic anomaly gradient method which can eliminate geomagnetic diurnal variation are adopted to detect the location, tracking and depth of underwater pipeline. Finally, the experiment has shown that this method has good detection accuracy and value in engineering application.

Low-power fast-update pipelined phase accumulator for CML-based high-speed CMOS DDFSs

Presented is a phase accumulator (PACC) for current-mode logic (CML)-based high-speed CMOS direct digital frequency synthesisers (DDFSs). The proposed PACC not only consumes low power by using an adaptive power reduction technique, but also updates frequency information within one clock period by using dual function logic gates and the charge sharing scheme that accelerates current recovery time. This work reduces power consumption by 33% compared to the conventional PACC with a pipeline depth of 8 and 32-bit FCW.

Optimizing energy-efficiency for program partitioning and mapping onto multi-core packet processing systems

The sharp increase in bandwidth requirements and versatility of network applications has prompted packet processing systems to widely adopt a multi-core multi-threaded architectural design. A challenging issue when programming such a system is how to fully utilize the processing power in a pipeline-parallel topology. As the power consumption increases, maintaining the energy-efficiency of the whole system also becomes delicate.In this paper, we proposed a strategy based on graph bi-partitioning (Bi-Par) to automatically map the programming code onto the multiple processing cores. The algorithm searches for an optimal configuration of the pipeline depth and the width of each pipeline stage. Steps taken to optimize the performance include iterations over the sub-tasks at the pipeline edges, and performing migration of tasks between cores to improve energy-efficiency. We designed a compiler framework to implement the algorithm, and use an experimental model to validate it. The simulation results show that our approach improves the energy-efficiency in all three benchmarks by between 8.04% and 34%, with a marginal loss in throughput.

Technical inspection of pipeline groups using surface electromagnetic methods

ABSTRACTIn this paper, we present an electromagnetic surface technique for the integrity inspection of buried pipelines groups. The inspection includes the determination of the pipeline plan location and depth, assessment of insulation‐coating quality and cathodic protection conditions. This technique is based on the approximation of a metallic pipeline by a heterogeneous transmission line. In the transmission line model, the degree of coating damage (disbanded or cracked insulation) corresponds to the leakage resistance that is defined by the coating resistance and environmental resistivity. Using the transmission line model, we simulated the voltage and current distributions along a pipeline created by the cathodic protection system or an external generator in a low‐frequency range. The calculations were performed for both a single pipeline and interconnected pipelines with different insulation‐coating quality (model of a common cathodic protection system). We describe the field operations, which consist of measurements of the magnetic field created by the current flowing into a pipeline, voltages on the cathodic protection control posts and soil resistivity. To find the pipeline position, depth and current we apply the interactive inversion of the magnetic‐field data obtained along the profiles orthogonally oriented to the pipeline‐group route. The interpretation of the field data includes: calculating the leakage current (the current difference on the measuring interval) for each pipeline, determining the leakage resistance (the voltage to the leakage‐current ratio) and assessing the insulation‐coating resistance taking into account the surrounding soil resistivity. We present practical examples of the integrity inspection of interconnected pipelines group in Mexico. The successful results achieved allow us to recommend this electromagnetic technique for quantitative inspection of the technical conditions of interconnected pipelines.

FabScalar

A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-designed superscalar core types that can streamline the execution of diverse programs and program phases. No prior research has addressed the 'Achilles' heel of this paradigm: design and verification effort is multiplied by the number of different core types. This work frames superscalar processors in a canonical form, so that it becomes feasible to quickly design many cores that differ in the three major superscalar dimensions: superscalar width, pipeline depth, and sizes of structures for extracting instruction-level parallelism (ILP). From this idea, we develop a toolset, called FabScalar, for automatically composing the synthesizable register-transfer-level (RTL) designs of arbitrary cores within a canonical superscalar template. The template defines canonical pipeline stages and interfaces among them. A Canonical Pipeline Stage Library (CPSL) provides many implementations of each canonical pipeline stage, that differ in their superscalar width and depth of sub-pipelining. An RTL generation tool uses the template and CPSL to automatically generate an overall core of desired configuration. Validation experiments are performed along three fronts to evaluate the quality of RTL designs generated by FabScalar: functional and performance (instructions-per-cycle (IPC)) validation, timing validation (cycle time), and confirmation of suitability for standard ASIC flows. With FabScalar, a chip with many different superscalar core types is conceivable.

A fine-grained runtime power/performance optimization method for processors with adaptive pipeline depth

Recently, a method known as pipeline stage unification (PSU) has been proposed to alleviate the increasing energy consumption problem in modern microprocessors. PSU achieves a high energy efficiency by employing a changeable pipeline depth and its working scheme is eligible for a fine control method. In this paper, we propose a dynamic method to study fine-grained program interval behaviors based on some easy-to-get runtime processor metrics. Using this method to determine the proper PSU configurations during the program execution, we are able to achieve an averaged 13.5% energydelay-product (EDP) reduction for SPEC CPU2000 integer benchmarks, compared to the baseline processor. This value is only 0.14% larger than the theoretically idealized controlling. Our hardware synthesis result indicates that the proposed method can largely decrease the hardware overhead in both area and delay costs, as compared to a previous program study method which is based on working set signatures.

Automatic Pipelining From Transactional Datapath Specifications

This paper presents a transactional specification framework (T-spec) for describing a datapath and the tool T-piper to synthesize automatically an in-order pipelined implementation with arbitrary user-specified pipeline-stage boundaries. T-spec abstractly views a datapath as executing one transaction at a time, computing the next system states based on the current ones. The synthesized pipeline maintains this semantics, yet allows concurrent execution of multiple overlapped transactions in different pipeline stages, where each stage performs a part of the next-state computation of each transaction. T-spec makes the state reading and writing events in a datapath explicit to enable T-piper to perform exact read-after-write (RAW) hazard analysis between the overlapped transactions. T-piper can automatically generate the pipeline control not only to ensure the correctness of the pipelined executions but also to minimize (using forwarding and speculation) the performance loss due to pipeline stalls in the presence of RAW dependencies. This paper reports design case studies applying T-spec and T-piper to reduced instruction set computing and complex instruction set computing processor pipeline development. In the latter, we report the results from a rapid design space exploration of 60 generated x86-subset pipelines, varying in pipeline depth, forwarding, and speculative execution, all starting from a single T-spec.

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

Applied inference

We propose and apply a new simulation paradigm for microarchitectural design evaluation and optimization. This paradigm enables more comprehensive design studies by combining spatial sampling and statistical inference. Specifically, this paradigm (i) defines a large, comprehensive design space, (ii) samples points from the space for simulation, and (iii) constructs regression models based on sparse simulations. This approach greatly improves the computational efficiency of microarchitectural simulation and enables new capabilities in design space exploration. We illustrate new capabilities in three case studies for a large design space of approximately 260,000 points: (i) Pareto frontier, (ii) pipeline depth, and (iii) multiprocessor heterogeneity analyses. In particular, regression models are exhaustively evaluated to identify Pareto optimal designs that maximize performance for given power budgets. These models enable pipeline depth studies in which all parameters vary simultaneously with depth, thereby more effectively revealing interactions with nondepth parameters. Heterogeneity analysis combines regression-based optimization with clustering heuristics to identify efficient design compromises between similar optimal architectures. These compromises are potential core designs in a heterogeneous multicore architecture. Increasing heterogeneity can improve bips 3 / w efficiency by as much as 2.4×, a theoretical upper bound on heterogeneity benefits that neglects contention between shared resources as well as design complexity. Collectively these studies demonstrate regression models' ability to expose trends and identify optima in diverse design regions, motivating the application of such models in statistical inference for more effective use of modern simulator infrastructure.

Energy-efficient register caching with compiler assistance

The register file is a critical component in a modern superscalar processor. It must be large enough to accommodate the results of all in-flight instructions. It must also have enough ports to allow simultaneous issue and writeback of many values each cycle. However, this makes it one of the most energy-consuming structures within the processor with a high access latency. As technology scales, there comes a point where register accesses are the bottleneck to performance and so must be pipelined over several cycles. This increases the pipeline depth, lowering performance. To overcome these challenges, we propose a novel use of compiler analysis to aid register caching. Adding a register cache allows us to preserve single-cycle register accesses, maintaining performance and reducing energy consumption. We do this by passing information to the processor using free bits in a real ISA, allowing us to cache only the most important registers. Evaluating the register cache over a variety of sizes and associativities and varying the read ports into the cache, our best scheme achieves an energy-delay-squared (EDD) product of 0.81, with a performance increase of 11%. Another configuration saves 13% of register system energy. Using four register cache read ports brings both performance gains and energy savings, consistently outperforming two state-of-the-art hardware approaches.

A mechanistic performance model for superscalar out-of-order processors

A mechanistic model for out-of-order superscalar processors is developed and then applied to the study of microarchitecture resource scaling. The model divides execution time into intervals separated by disruptive miss events such as branch mispredictions and cache misses. Each type of miss event results in characterizable performance behavior for the execution time interval. By considering an interval's type and length (measured in instructions), execution time can be predicted for the interval. Overall execution time is then determined by aggregating the execution time over all intervals. The mechanistic model provides several advantages over prior modeling approaches, and, when estimating performance, it differs from detailed simulation of a 4-wide out-of-order processor by an average of 7%. The mechanistic model is applied to the general problem of resource scaling in out-of-order superscalar processors. First, we use the model to determine size relationships among microarchitecture structures in a balanced processor design. Second, we use the mechanistic model to study scaling of both pipeline depth and width in balanced processor designs. We corroborate previous results in this area and provide new results. For example, we show that at optimal design points, the pipeline depth times the square root of the processor width is nearly constant. Finally, we consider the behavior of unbalanced, overprovisioned processor designs based on insight gained from the mechanistic model. We show that in certain situations an overprovisioned processor may lead to improved overall performance. Designs where a processor's dispatch width is wider than its issue width are of particular interest.

Fast Elliptic Curve Cryptography on FPGA

This paper details the design of a new high-speed pipelined application-specific instruction set processor (ASIP) for elliptic curve cryptography (ECC) using field-programmable gate-array (FPGA) technology. Different levels of pipelining were applied to the data path to explore the resulting performances and find an optimal pipeline depth. Three complex instructions were used to reduce the latency by reducing the overall number of instructions, and a new combined algorithm was developed to perform point doubling and point addition using the application specific instructions. An implementation for the United States Government National Institute of Standards and Technology-recommended curve over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">163</sup> ) is shown, which achieves a point multiplication time of 33.05 s at 91 MHz on a Xilinx Virtex-E FPGA-the fastest figure reported in the literature to date. Using the more modern Xilinx Virtex-4 technology, a point multiplication time of 19.55 s was achieved, which translates to over 51120 point multiplications per second.

Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies

Performance and power act as opposing constraints for the optimal pipeline depth of a processor. Although increasing the pipeline depth may enable performance improvement, the higher clock speed associated with a deeper pipeline also increases the power dissipation. Previous papers have shown that the optimal pipeline depth for superscalars considering both power and performance is 18 to 20 fan-out-of-four (FO4) inverter delays. As simultaneous multithreading (SMT) becomes increasingly important for modern high-end processors, there is a need to quantify the optimal power-performance pipeline depth for SMT. Although previous work has shown that SMT retains the performance-optimal pipeline depth in near-future technologies, this result does not take power into account. The intricate interplay between the relative impacts of changing pipeline depth on power and performance makes it difficult to predict the scaling trends for optimal SMT pipeline depths considering both power and performance. Using simulations, we quantify the optimal SMT pipeline depths based on the well-known power-performance metric PD <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . Our analysis is novel and provides the following key results about the scaling trends for SMT pipelines considering both power and performance: 1) SMT has a deeper PD <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> -optimal pipeline as compared to superscalar. 2) The PD <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> -optimal SMT pipeline depth increases with an increase in the number of programs. 3) The PD <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> -optimal SMT pipeline becomes shallower with technology for a given number of programs. Based on these results, we provide the following insights into SMT designs for future technologies: 1) To retain the PD3-optimal pipeline depth across technology generations while being energy-efficient, the number of programs running on an SMT must increase. 2) To maintain a constant power dissipation across technology generations, SMT pipelines must become shallower.

Design of a high performance self-timed ARM9 processor

This paper presents an asynchronous implementation of ARM9 processor, AEM32. We introduce an adaptive pipeline structure that makes the pipeline depth dynamically. We employ a parallel processing control based on datapath splitting to execute the instruction fed into the pipeline in parallel when they have different datapath. AEM32 is synthesized using a 0.35-µm CMOS cell library. Simulation results show that our implementation had 2.6 times higher performance than the asynchronous counterpart, AMULET3i. In terms of Et2, AEM32 shows 3 times higher efficiency than the other counterpart, ARM966HS.

Optimal pipeline depth with pipeline stage unification adoption

To find the optimal pipeline design point by considering both performance and power objectives has been one focus of interest in recent researches. However, we found that previous papers did not consider deepening or shrinking pipeline depth dynamically during the program execution. In this paper, with the adoption of the earlier proposed Pipeline Stage Unification (PSU) method, we studied the relationship between power/performance and pipeline depth in processors with a pipeline of multi-usable depths. Our evaluation results of SPECint2000 benchmarks shown in this paper illustrate that the PSU adoption can achieve good efficiency for platforms which concern both energy and performance, even after the utilization of complex clock gating.

Introduction

In this issue, we present the papers from the proceedings of the 2nd International Workshop on Advanced Low Power Systems (ALPS 2007) that was held in conjunction with the 21st International Conference on Supercomputing in Seattle. "Thoughtfulness" is an important keyword in the both current and future technologies in all over the world: Thoughtful to human being, thoughtful to our surroundings, thoughtful to the earth, and so on. For the thoughtfulness, Low-power is believed to be one of the most indispensable keyword. The ALPS workshop focuses on the current technological challenges in developing low-power and power-aware computing systems ranging from servers to embedded devices. The goal of the workshop is to bring all aspects of power-aware computing from industry and academia. This year, we have one invited talk entitled "An Under 2W 100GOPS Video Recognition Processor Based on a Linear Array of 128 4-Way VLIW Processing Elements" by Shorin Kyo (NEC Corporation) and 6 papers selected based on the full paper review by the program committee members. The first set of papers discusses low-power designs. We have three papers: "Optimal Pipeline Depth with Pipeline Stage Unification Adoption" by Jun Yao, Hajime Shimada, Shinobu Miwa, and Shinji Tomita, "VCLEARIT: A VLSI CMOS Circuit Leakage Reduction Technique For Nanoscale Technologies" by Preetham Lakshmikanthan and Adrian Nunez, and "Leakage Energy Reduction in Cache Memory by Data Compression" by Kiyofumi Tanaka and Takahiro Kawahara. The second set of papers: "Preventing Timing Errors on Register Writes: Mechanisms of Detections and Recoveries" by Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, and Suichi Sakai, "Not Multi-, but Many-Core: Designing Integral Parallel Architectures for Embedded Computation" by Mihaela Malita, Gheorghe Stefany, and Dominique Thiebaut, and "Fine-grain Compensation Method with Consideration of Trade-offs between Computation and Data Transfer for Power Consumption" by Takefumi Miyoshi and Nobuhiko Sugino, covers reliability, many-core and parallelization issues. All papers here are going to create the way to the new aspects of low-power systems. We hope you will find the papers of this special issue of Computer Architecture News to be stimulating and that you will be inspired to contribute your efforts to the future low power systems.

Compacting register file via 2-level renaming and bit-partitioning

A large multi-ported rename register file (RRF) is indispensable for simultaneous multithreaded (SMT) processors to hold more intermediate results of in-flight instructions from multiple threads running simultaneously. However, enlarging the RRF incurs longer access delays and more power consumption, both of which are critical to the overall performance and are becoming a bottleneck due to the ever-increasing pipeline depth and issue width in future SMT processors. We propose a novel register renaming scheme called Multi-usable Rename Register with 2-Level renaming and allocating ( 2L-MuRR), which focuses on more efficient utilization of a fewer number of rename registers. Based on the fact that the effective bit-width of most operands is narrower than the full-bit width of a register entry, 2L-MuRR partitions each rename register into several fields of different widths. Either a single field or a field combination can hold an operand, thus making each rename register multi-usable. In addition, 2L-MuRR postpones the register allocation to the write-back stage, which is similar to the formerly proposed virtual–physical-register (VPR) scheme, further reducing the meaningless RRF occupancy. The simulations show that 2L-MuRR improves the efficiency of the RRF significantly, achieving higher performance with much fewer rename registers. For example, when the RRF size is 60, 2L-MuRR outperforms Trad (traditional register renaming approach) and VPR in terms of IPC by 38% and 11%, respectively, while decreases the RRF occupancy by 37% and 15%, respectively.