Pin Field Research Articles

Multi-Objective Optimization of Decoupling Capacitors for Placement and Component Value

A multiobjective evolutionary method is proposed for the optimization of surface mount device (SMD) multilayer ceramic chip (MLCC) capacitors used for decoupling on printed circuit boards (PCBs) with resonant power–ground plane pairs. The proposed approach provides options for designers to meet power integrity specifications by employing uniform-valued capacitors that help to reduce the bill-of-material (BOM) cost and mitigate the part procurement risk. It is also shown that uniform MLCC capacitors with variable distance from power pins can have a similar decoupling effect to an assortment of capacitors. By simultaneously optimizing the pin-capacitor distance and value, the proposed method is shown to allow for the allocation of fewer decoupling capacitors under the ball-grid-array (BGA) pin field of an integrated circuit (IC) device.

Differential Crosstalk Mitigation in the Pin Field Area of SerDes Channel With Trace Routing Guidance

Crosstalk noise on the printed circuit board is usually decreased by adding shielding ground (GND). In the trace routing area, the shielding vias are added to isolate the coupling between different traces. In the ball gate array (BGA) and pin field area, assigning more GND pins has demonstrated the effectiveness of crosstalk reduction between signals. However, such design decreases the signal to ground (S:G) ratio dramatically, herein, it is not suitable for applications that require high signal pin density. Unlike the treatment in the conventional methodology, in this paper, the differential crosstalk is mitigated by using the principle of symmetry on two adjacent differential signal pairs in the BGA and pin field regions. New full pin map patterns are proposed and compared with the conventional full pin map patterns. Without sacrificing the S:G ratio, the proposed maps prove the superiority in mitigating both differential far-end and near-end integrated crosstalk noise. To maintain the low crosstalk level in the entire link path, guidance of differential trace routing is provided and demonstrated in the details. All models in this paper satisfy SerDes channel designing and manufacturing requirements.

Pinout Optimization for 10 Gbps+ Serial Link Routing

Definition and optimization a BGA (ball grid array) package pinout is a complicated process. Multiple factors must be considered, such as chip level floorplan, board placement of the component, the board stackup, escape routability, and signal and power integrity constraints. These tradeoffs and decisions impact package body size and board real estate, therefore overall system cost. At high frequencies, such as >10 Gbps, the BGA to board via transitions cause visible impedance and noise mismatches and becomes a critical factor in the end to end channel design. Determining BGA pin assignments and their PCB transitions must meet the package crosstalk constraints within the required commodity PCB technology manufacturing rules. This paper describes a methodology of extracting 4 differential signal pairs in the board file from BGA ball to its PCB via transitions through BGA pin field into 3D field solver. The extracted geometry is simulated to determine near-end and far-end crosstalk noise levels between a single victim pair and its associated aggressors. Different pin assignment designs will have different number of aggressors to consider. Different routing layers will also produce different signal via stub lengths (specific resonant frequency) and signal via coupling contributing to far-end crosstalk noise. This may require back drilling of differential signal via stubs to minimize this noise. The aggregated crosstalk noise level must be equal to or better than what the package can deliver. Once these design rules are determined, they can be leveraged across all channels running at the same frequency.

Progressive binasal hemianopia

A 46–year-old white man presented to the emergency department after noticing an inferonasal visual field defect in his right eye. The right eye acuity was 6/18 with full colour vision, the inferonasal defect was confirmed with a red pin, fundoscopy was normal. The left eye acuity was 6/5 with a normal red pin field. He was lost to follow up. 7 months later he presented with further deterioration of vision in the right eye. He had noticed occasional sharp pains behind his right eye, but was otherwise well.

The package integration of rf-mems switch and control ic for wireless applications

The integration of microelectromechanical systems (MEMS) switch and control integrated circuit (IC) in a single package was developed for use in next-generation portable wireless systems. This packaged radio-frequency (RF) MEMS switch exhibits an insertion loss under -0.4 dB, and isolation greater than -45 dB. This MEMS switch technology has significantly better RF characteristics than conventional PIN diodes or field effect transistor (FET) switches and consumes less power. The RF MEMS switch chip has been integrated with a high voltage charge pump plus control logic chips into a single package to accommodate the low voltage requirements in portable wireless applications. This paper discusses the package assembly process and critical parameters for integration of MEMS devices and bi-complementary metal oxide semiconductor (CMOS) control integrated circuit (IC) into a single package.

Integration of PIN and Vertical Junction Field Effect Transistor for Photodetector Optoelectronic Integrated Circuit

The integration of a PIN photodiode and a vertical junction field effect transistor (VJFET) is useful for optoelectronic integrated circuit (OEIC) since the structure is compact and has potentially high power and high speed capabilities. A GaAs VJFET with the gate connected to PIN was fabricated. The fabricated PIN has a low leakage current, below 50 nA at 10 V bias. Two step atmospheric pressure metalorganic chemical vapor deposition (AP MOCVD) was used and the second step epitaxial layers were selectively grown using silicon dioxide (SiO2) mask. The gate p-layer has a tungsten (W) layer on it and was doped by carbon to prevent autodoping during the second step epitaxy. This VJFET has an improved current-voltage characteristics than the one without W on p-gate layer.