Pinout Optimization for 10 Gbps+ Serial Link Routing

Abstract

Definition and optimization a BGA (ball grid array) package pinout is a complicated process. Multiple factors must be considered, such as chip level floorplan, board placement of the component, the board stackup, escape routability, and signal and power integrity constraints. These tradeoffs and decisions impact package body size and board real estate, therefore overall system cost. At high frequencies, such as >10 Gbps, the BGA to board via transitions cause visible impedance and noise mismatches and becomes a critical factor in the end to end channel design. Determining BGA pin assignments and their PCB transitions must meet the package crosstalk constraints within the required commodity PCB technology manufacturing rules. This paper describes a methodology of extracting 4 differential signal pairs in the board file from BGA ball to its PCB via transitions through BGA pin field into 3D field solver. The extracted geometry is simulated to determine near-end and far-end crosstalk noise levels between a single victim pair and its associated aggressors. Different pin assignment designs will have different number of aggressors to consider. Different routing layers will also produce different signal via stub lengths (specific resonant frequency) and signal via coupling contributing to far-end crosstalk noise. This may require back drilling of differential signal via stubs to minimize this noise. The aggregated crosstalk noise level must be equal to or better than what the package can deliver. Once these design rules are determined, they can be leveraged across all channels running at the same frequency.