Ge Pileup Research Articles

Strain and Defect Evolution of Si1-xGex/Si Heterostructures Grown by Pulsed Laser Induced Epitaxy

The relaxation mechanism of Si1-xGex/Si heterostructures subjected to pulsed laser melting was investigated by probing the pulsed laser induced epitaxy (PLIE) regime of undoped 20 nm Si0.5Ge0.5/Si thin films. The pseudomorphic “critical thickness” and evolution of bi-layer formation was determined as a function of average Ge concentration of the films via quantitative analysis of (004) HRXRD rocking curves. Comparison of pseudomorphic thicknesses alongside SIMS analysis reveals a “dynamic critical Ge concentration” of 27-30% Ge as the PLIE limit for pseudomorphic growth that is independent of average Ge concentration of the films. Plan-view weak-beam dark-field imaging revealed that surface dislocation half-loops are the primary strain relieving defects that reach concentrations on the order of 1010 cm−2. It is theorized that quasi-cellular solidification leads to lateral Ge segregation, creating nm scale localized regions of Ge pile-up and stress concentration. The morphology of the liquid/solid interface along with stress localization is what allows for the dislocation half-loop to be the primary strain relieving defect, with <110> edge defects acting as secondary. These results are important for understanding the conditions and strategies necessary to utilize pulsed laser melting to its fullest potential in applications towards pMOS source/drain contact engineering.

(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

This paper discusses the fabrication of SiGe channel for Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs, FinFETs and Nano Wire FETs (NWFETs). Enrichment conditions need to be tuned to avoid excessive Ge pile-up on tensile-strained planar Si films due to lower Ge diffusion. Patterning SiGe Fins in thick blanket SiGe layers faces the crystal quality limits set by plastic relaxation beyond critical thickness. As an alternative, Ge enrichment of pre-existing Si Fins requires conformal SiGe growth and can produce strained SiGe Fins up to 50% without significant relaxation, independently from Fin height. Enrichment requirements for NWFETs are identical to those of planar devices. As a result, NWFETs benefit from both SiGe mechanical stability and uniaxial compressive strain performance enhancement.

Process driven oxygen redistribution and control in Si0.7Ge0.3/HfO2/TaN gate stack film systems

Bulk and surface sensitive photoemission core line spectra have been acquired for Si and Ge following each step in the process sequence of Si0.7Ge0.3/2 nm HfO2/2.5 nm TaN/950 °C gate stack film systems. Extended x-ray absorption fine structure measurements have confirmed Ge segregation and pileup to form a Ge-rich layer at the SiGe surface during Si oxidation. Transmission electron micrograph cross-sections with electron energy loss element profiles have verified the effectiveness of plasma nitridation for restricting SiGe oxidation and achieving &amp;lt;1 nm equivalent oxide thickness with gate leakage current density equivalent to that of Si substrates without the necessity of a Si cap for oxidation control.

Physical Mechanism of Threshold Voltage Modulation by Ge Channel Ion Implantation in the TiN/HfO2 Gate Stack Systems

We extensively investigated the physical origin of the threshold voltage VTH modulation by the Ge channel ion implantation (I/I) in HfO2/TiN/polycrystalline Si gate stack systems. The possible VTH modulation factors were carefully distinguished from each other by changing the channel dopant concentration and the thickness of the gate dielectric films. It was found that the changes in energy-band offset and dopant concentration in the channel region are minor factors of the VTH modulation. However, it was also found that ΔVTH is sensitive to the oxidation condition of the interfacial oxide layer; a longer oxidation induces a larger ΔVTH. From the X-ray spectroscopy, we found that a Ge pile-up at the interfacial layer/channel interface occurs, and that the VTH modulation range correlates well with the amount of piled-up Ge.

Relaxation of misfit strain in silicon-germanium (Si1−xGex) films during dry oxidation

The effects of oxidation on strain relaxation in Si1−xGex layers on silicon substrates were investigated. Si1−xGex layers, with different Ge fractions (x=0.15 and 0.3), were grown on chemically cleaned silicon substrates by an ultrahigh vacuum chemical vapor deposition process. Oxidation at 800 and 900 °C under O2 ambient in a tube furnace resulted in the production of silicon oxide layers on top and a Ge-rich region in the Si1−xGex films. It was observed that the oxidation of Si0.85Ge0.15 films at 900 °C produced the relaxation of the misfit strain in the remnant Si1−xGex layer and the increase in strain in the Ge pile-up layer with increasing oxidation time, while the oxidation at 800 °C produced no changes in the misfit strain in the Si1−xGex layers. The oxidation of Si0.70Ge0.30 films at 800 °C showed the relaxation of the misfit strain in the remnant Si1−xGex layer with the accumulation of stain in the Ge pile-up layer. However, the oxidation of Si0.70Ge0.30 layers at 900 °C exhibited the strain relaxation in the Ge pile-up layer after the Ge pile-up was extended into the remaining Si1−xGex layer, with the formation of misfit dislocations at the interface between the remaining Si1−xGex and Si substrate.

Effect of strain relaxation of oxidation-treated SiGe epitaxial thin films and its nanomechanical characteristics

In this study, we examined the effect of high-temperature oxidation treatment on the SiGe epitaxial thin films deposited on Si substrates. The X-ray diffraction (XRD), atomic force microscopy (AFM), and nanoindentation techniques were employed to investigate the crystallographic structure, surface roughness, and hardness ( H) of the SiGe thin films, respectively. The high-temperature oxidation treatment led to Ge pileup at the surface of the SiGe thin films. In addition, strain relaxation occurred through the propagation of misfit dislocations and could be observed through the cross-hatch pattern (800–900 °C) and SiGe islands (1000 °C) at the surface of the SiGe thin films. Subsequent hardness ( H) measurement on the SiGe thin films by continuous penetration depth method indicated that the phenomenon of Ge pileup caused a slightly reduced H (below 50 nm penetration depth), while relaxation-induced defects caused an enhanced H (above 50 nm penetration depth). This reveals the influence of composition and defects on the structure strength of high-temperature oxidation-treated SiGe thin films.

Controlling dislocation positions in silicon germanium (SiGe) buffer layers by local oxidation

The method of controlling dislocation positions via local oxidation of 80 nm thick Si 0.8Ge 0.2 buffer layer on Si substrate is investigated. The strained SiGe layer is locally exposed to oxidation by patterning Si 3N 4 mask layer on SiGe with perpendicularly crossing stripe patterns with <110> directions. The local oxidation of patterned SiGe regions leads to increased stress to the remaining SiGe either via Ge pileup or volume expansion during oxidation. The increased stress in the SiGe region underneath the oxide increases dislocation nucleation rate. The preferential nucleation of dislocations and subsequent propagation of dislocations through non-oxidized regions results in reduced threading dislocation density to 10 6 – 7/cm 2, which is lower than that of the conventional constant composition SiGe buffer layer. Further reduction of threading dislocation density is expected by optimizing the oxidation conditions and pattern size and shape for local oxidation.

Behavior of strain at a thin Ge pile-up layer formed by dry oxidation of a Si 0.7Ge 0.3 film

The change of strain in Si 0.7Ge 0.3 films was investigated with medium energy ion scattering (MEIS). Si was removed in the films by selective oxidation at 800 °C, resulting in the formation of a Ge pile-up layer on the surface. The relaxation and the thickness of the pile-up layer were closely related to the oxidation time. MEIS data demonstrated that relaxation of the Ge layer in the depth direction occurred partially, and that the rates of relaxation decreased with depth. In addition, the rate of relaxation increased with the oxidation time. Lastly, the relaxation of the Ge layer affected the strain of the remaining Si 0.7Ge 0.3 substrate.

Strain Behaviors of Si[sub 1−x]Ge[sub x] Grown on Oxidized and Etched Si[sub 1−x]Ge[sub x

The strain of Si 1-x Ge x (x = 0.15) was controlled by oxidation temperature, time, and initial Ge fraction in underlying Si 1-x Ge x . Followed by oxidation and HF cleaning of Si 1-x Ge x , epi-Si 1-x Ge x (x = 0.15) films were deposited on the Ge pileup layer, which is formed by the ultrahigh-vacuum chemical vapor deposition technique at 550°C. Through the X-ray rocking curve measurements and Raman scattering measurements, the strain-shift coefficient [b(x)] was evaluated. By using oxidized and etched Si 1-x Ge x for the substrate, the strain of deposited Si 1-x Ge x was changed from the partially relaxed to the tensile-strained state, a method for growing relaxed Si 1-x Ge x .

Ge out-diffusion effect on low-voltage tunnelling current in strained-Si nMOSFETs

Ge out-diffusion effect on low-voltage tunnelling current is investigated using strained-Si nMOSFETs with different strained-Si layers. In a low gate voltage region (−1 V<VG<0 V), excess tunnelling current increases with reduced strained-Si layer thickness. In addition, change of the reciprocal effective electron mobility is found to be proportional to the increase in the low-voltage tunnelling current, which is attributed to the increase in strained-Si/SiO2 interface states caused by the presence of Ge out-diffusion and pileup at strained-Si/SiO2.

Electrical and interfacial characteristics of nanolaminate (Al 2O 3/ZrO 2/Al 2O 3) gate stack on fully depleted SiGe-on-insulator

The structural and electrical characteristics of a novel nanolaminate Al 2O 3/ZrO 2/Al 2O 3 high- k gate stack together with the interfacial layer (IL) formed on SiGe-on-insulator (SGOI) substrate have been investigated. A clear layered Al 2O 3 (2.5 nm)/ZrO 2 (4.5 nm)/Al 2O 3 (2.5 nm) structure and an IL (2.5 nm) are observed by high-resolution transmission electron microscopy. X-ray photoelectron spectroscopy measurements indicate that the IL contains Al-silicate without Ge atom incorporation. A well-behaved C– V behavior with no hysteresis shows the absence of Ge pileup or Ge segregation at the gate stack/SiGe interface.

Physico-chemical and electrical properties of rapid thermal oxides on Ge-rich SiGe heterolayers

Rapid thermal oxidation of high-Ge content (Ge-rich) Si 1− x Ge x ( x = 0.85) layers in dry O 2 ambient has been investigated. High-resolution X-ray diffraction (HRXRD) and strain-sensitive two-dimensional reciprocal space mapping X-ray diffractometry (2D-RSM) are employed to investigate strain relaxation and composition of as-grown SiGe alloy layers. Characterizations of ultra thin oxides (∼6–8 nm) have been performed using Fourier transform infrared spectroscopy (FTIR) and high-resolution X-ray photoelectron spectroscopy (HRXPS). Formation of mixed oxide i.e., (SiO 2 + GeO 2) and pile-up of Ge at the oxide/Si 1− x Ge x interface have been observed. Enhancement in Ge segregation and reduction of oxide thickness with increasing oxidation temperature are reported. Interface properties and leakage current behavior of the rapid thermal oxides have been studied by capacitance–voltage (C–V) and current–voltage (J–V) techniques using metal-oxide-semiconductor capacitor (MOSCAP) structures and the results are reported.

Modeling and characterization of atomically sharp “perfect” Ge/SiO 2 interfaces

We have shown that oxidation of germanium-implanted Si can produce a pile-up of Ge in front of the oxidation front and produce an atomically-sharp interface. In this paper, we examine band-structure and processing of such an interface. Based on ab-initio calculations, the band structure of the sharp interface seems to be more favorable for use in electronic devices than the usually diffuse interface in Si/SiO 2. Furthermore, we propose an ab-initio based Monte-Carlo model to simulate oxidation of SiGe alloys. The model explains the formation of the sharp interface due to the repulsive interaction between O and Ge. Furthermore, inclusion of Ge into the oxide is predicted for higher Ge concentrations, in agreement with experiment.

Investigation of Nanostructured Germanium/Silicon Dioxide Interfaces

The precipitation of Ge nanoclusters in SiO2 after implantation arises from their immiscibility and is technologically interesting due to their luminescence and potential use for non-volatile memory devices. Exploiting the same immiscibility, we have recently found that oxidation of germaniumimplanted Si surfaces can produce a pileup of Ge in front of the oxidation front and create an atomically sharp interface. In this paper, we examine the band structure and processing of such an interface. Based on ab initio band structure calculations, the band structure of the sharp interface seems to be more favorable for use in electronic devices than the usually diffuse interface in Si/SiO2. Furthermore, we propose an ab initio based Monte Carlo model to simulate such an oxidation of SiGe alloys. The model explains the formation of the sharp interface due to the repulsive interaction between O and Ge. In such cases, Ge is expelled from the oxide and O atoms do not enter the Ge region under the oxidation front, resulting in strong segregation. Furthermore, inclusion of Ge nanoparticles in the oxide is predicted for higher Ge concentrations, in agreement with experimental results.

Experimental study of the oxidation of silicon germanium alloys

We report on the in situ oxidation of a series of Si–Ge alloy layers grown epitaxially on a (100) Si substrate. The alloy compositions of the layers varied in Ge composition from 1.8% to a high of 16.8%. Oxidations were carried out in situ in a Scientia ESCA-300 system between 400 and 800 °C. In order to explore the transition from pure SiO2 to mixed SiO2−GeO2 films, dry oxidations were carried out under partial pressures which were varied by almost nine orders of magnitude. State of the art oxidations were also carried out in a double walled oxidation furnace at one atmosphere to compare with some of the published results. In situ oxidations and analyses were done at each stage of the process from initial cleaning to monolayer absorption and oxide formation. Films grown in the thin regime up to 10 nm were analyzed by angle resolved x-ray spectroscopy. These studies were carried out to explore the influence of alloy composition on the distribution of subbonded states of Si and their influence on interfacial properties. Comparisons were made between films that were grown as pure SiO2 and those that resulted in mixed SiO2−GeO2 with regard to the areal density of these states. In spite of the strong pileup of Ge at the interface during oxide growth, there was less than expected influence of alloy composition on the interface and some evidence that interfacial annealing was taking place. It was also confirmed that mixed oxide interfaces were poorer and more highly defective than those of pure SiO2 on the same alloy.

Effect of Si cap layer on parasitic channel operation in Si/SiGe metal–oxide–semiconductor structures

We investigate the effects of silicon cap layer thinning on channel carrier confinement in silicon/strained silicon-germanium (Si/SiGe) metal–oxide–semiconductor (MOS) structures. The silicon cap thickness is shown to have a critical influence on the induced parasitic channel in the silicon cap, which lowers the transconductance value of the buried SiGe channel in hole carrier channel p metal–oxide–semiconductor field-effect transistor devices. This can have serious consequences on future implementation of SiGe ultrashort channel devices where gate induced parasitic channel and short channel effects can be pronounced. An exact methodology is devised for consumption of silicon cap layer using a modified Radio Corporation of America surface standard clean self-terminating chemical oxide and rapid thermal oxide growth. This provides (i) precise control over the silicon cap and thermal oxide thickness and (ii) a limit on the amount of thermal budget induced strain relaxation in the buried SiGe layer. The threshold voltages for inversion of carriers at the SiO2/Si and the Si/SiGe interfaces are extracted as functions of Si cap thickness. A transition from dual to single channel operation in MOS devices at room temperature on thinning the silicon cap layer is observed with capacitance–voltage measurements. Cross-section transmission electron microscopy and secondary ion mass spectroscopy techniques are used to calibrate and support the developed methodology for Si cap layer etch control and the effect of Ge species at the oxide–heterostructure interface. There is a high fixed charge density, which indicates Ge pileup at the SiO2/SiGe interface. Our analysis suggests that about 1 nm of silicon cap retention is necessary to minimize the gate induced parasitic channel and to decouple the oxide interface trap influence on the channel carriers in the SiGe.

A study of the oxidation behavior and the postannealing effect in a graded SiGe/Si heterostructure

A study on the dry thermal oxidation of a graded SiGe layer was performed. To reduce the Ge pileup effect during the thermal oxidation, the SiGe layer was deposited with much lower Ge content near the free surface than near the SiGe/Si heterointerface. After dry thermal oxidation at 900°C, the Ge composition in the pileup layer was significantly reduced and strain relaxation by defect formation was prevented due to the graded Ge distribution. To homogenize the Ge distribution between the pileup layer and remaining SiGe layer, the oxidized layers were postannealed. The homogenization is significantly enhanced by strain-induced diffusion, and it was confirmed by uphill diffusion of Ge. This result can propose an alternative oxidation method of strained SiGe/Si heterostructures.

Rapid thermal oxidation of radio frequency sputtered polycrystalline silicon germanium films

The oxide growth of rf sputtered polycrystalline Si1−xGex films was found not sensitive to the Ge concentration in the films. The infrared results showed that the oxide grown on Si0.61Ge0.39 film mainly contained GeO2 and the oxide contained Ge–O–Ge and Si–O–Ge bonds when grown on Si0.73Ge0.27 film. X-ray photoelectron spectroscopy results showed the absence of Ge in the bulk of the oxides for Si1−xGex films with x&amp;lt;0.27 and no pile-up of Ge at the SiO2/Si1−xGex interface. The electrical breakdown fields of oxides grown on Si1−xGex films were lower than the oxide breakdown field of polysilicon. The Dit and Qf values of the SiO2/Si1−xGex system were found to be rather high at ∼2.1–2.6×1012 eV−1 cm−2 and ∼1.1–2.7×1012 cm−2, respectively.

Ge-rich Si1-XGeX Nanocrystal Formation by the Oxidation of As-Deposited Thin Amorphous Si0.7Ge0.3 Layer

AbstractGe-rich Si1-XGeX nanocrystals are formed by the selective oxidation of Si during the dry oxidation of an amorphous Si0.7Ge0.3 layer. The oxidation kinetics of the alloy film shows the activation energies of linear and parabolic rate constants are about 1.35 and 1.02 eV, respectively, based on the model proposed by Deal and Grove. In addition, as a result of the selective oxidation of Si and Ge pile-up during the oxidation process, Ge-rich Si1-XGeX nanocrystals are formed with the size of 5.6 ± 1.7 nm and the spatial density of 3.6×1011/cm2 at 600°C. At higher temperature of 700 and 800°C, the size of nanocrystal is increased to about 20 nm. The nanocrystals formation by oxidation is thought to be due to higher oxidation rate at grain boundary than at bulk grain. Therefore, the dependence of size on temperature is explained with the grain size determined by solid phase crystallization of amorphous film, oxidation rate, and grain growth.

Dry thermal oxidation of a graded SiGe layer

A method for the dry thermal oxidation of a strained SiGe layer is proposed. By oxidation of a graded Si1−xGex layer, the effect of Ge pileup was significantly reduced and the undesirable strain relaxation by defect formation is prohibited. After oxidation, the oxidized SiGe layer was homogenized by postannealing process, and thereby a SiO2/SiGe interface with good structural properties was obtained. During postannealing, the homogenization was significantly enhanced by strain-induced diffusion, and it was clearly proved by the uphill diffusion. This result can propose an alternative oxidation method of strained SiGe/Si heterostructures.