Physical Unclonable Function Design Research Articles

On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging

SRAM-based weak physically unclonable functions (PUFs) have shown promise regarding tamper sensitive key storage and device ID generation. Weak PUFs rely on intrinsic process variations to produce repeatable and unique start-up behavior. However, noise in the system can affect the start-up behavior and introduce errors. A number of solutions, such as fuzzy extraction and error correcting codes have been proposed to alleviate the effect of noise and generate stable keys. Unfortunately, the overhead from these techniques grows superlinearly with increasing error rate. Alternatively, accelerating device aging or burn-in has been shown to reduce start-up error rate significantly, which leads to reduced overhead for error correction. Unfortunately, burn-in is a time-intensive process and accrues significant production cost. This paper proposes a method to reduce the cumulative burn-in time via quantification of the minimum burn-in requirements for chip. We propose a low-cost proxy to measure the degree of process variation of each device at birth and use previously proposed device aging models to determine the burn-in requirements. Our results show that this procedure reduces cumulative burn-in cost without compromising the resultant reliability of weak PUFs. Furthermore, we analyze the effect of having additional PUF cells, alternate weak PUF designs and transistor technologies on burn-in requirements.

Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design

A physical unclonable function (PUF) is a promising security primitive which utilizes the manufacturing process variations to generate a unique unclonable digital fingerprint for a chip. It is especially suitable for resource constrained security applications, e.g. internet of things (IoT) devices. The ring oscillator (RO) PUF and the static RAM (SRAM) PUF are two of the most extensively studied PUF designs. However, previous RO PUF designs require a lot of hardware resources for ROs to be robust and SRAM PUFs are not suitable for authentication. The previous research by the author proposed a tristate static RAM (TSRAM) PUF which is a highly fiexible challenge response pair (CRP) based SRAM PUF design. In this paper, a novel configurable PUF structure based on tristate inverters, namely a tristate configurable ring oscillator (TCRO) PUF is proposed. A configurable delay unit, composed of a tristate matrix, is used to replace the inverters in the RO PUF. The configurable bits are able to select a subset of the tristate inverters in the delay unit. Each tristate inverter is completely utilized by using the configurable delay unit and thus the approach enhances the flexibility and entropy of the proposed PUF design. The proposed PUF design can generate an exponential number of CRPs compared with the conventional RO PUF. Moreover, the proposed design significantly reduces the hardware resource consumption of the RO PUF. Delay models of both the TSRAM PUF and the proposed TCRO PUF designs are presented. A comprehensive evaluation of the TSRAM PUF is proceeded. To validate the proposed TSRAM PUF and TCRO PUF designs, a simulation based on UMC 65nm technology and a hardware implementation on a Xilinx Virtex-II FPGA are presented. The experimental results demonstrate good uniqueness and reliability as well as high efficiency in terms of hardware cost.

A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable Functions

The promise of strong physical unclonable functions (PUF) is to utilize the manufacturing variations of circuit elements to produce an independent and unpredictable response to any input challenge vector. Attacks on PUFs that predict the responses to input challenge vectors offer an interesting research problem. An attacking approach based on the optimization theory and side-channel information is proposed where we estimate the manufacturing variations of the circuit elements and predict the PUF’s responses to challenge vectors whose actual responses are not known. We apply this attacking approach on some popular PUF designs, including the Arbiter PUFs, the Memristor Crossbar PUFs, and the XOR Arbiter PUFs. Simulations show a substantial reduction in attack complexity compared with previously proposed machine-learning (ML)-based attacks: we achieve an average reduction of 66% in attack time compared with the ML approach. Despite some overhead, our approach is also applicable when the PUF responses are noisy.

ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function

Ring oscillator (RO)-based physical unclonable function (PUF) is an emerging hardware security primitive but its response reproducibility is susceptible to changes in operating conditions and device aging. Present solutions to increase RO PUF reliability either incur large hardware overhead or require sophisticated RO selection algorithm. This paper exploits the optimal biasing of current starved (CS) inverter for the design of RO PUF with very high reliability against both temperature and voltage variations. With two additional transistors, the CS inverter can be adaptively biased at idle time and in active mode to significantly reduce the overall stress, making the proposed CS RO PUF robust against both environmental condition variations and aging. Without using error correction code, the reliability is further improved by a low-cost proximity detector circuit with a small sacrifice on challenge-response pair space. The correlation between successive RO pairs of different input challenges is also broken by an irregular clocking of the linear feedback shift register used to encipher the input challenges. Based on Monte Carlo simulation in TSMC 40-nm CMOS process, the reliability of native PUF responses has been raised substantially from 89.78% for the regular RO PUF to 95.88% for the proposed CS RO PUF over a broad temperature range of -40°C to 120 °C and ± 20% supply variation. With the proximity detector, the proposed Aging-resistant Current-starved RO (ACRO) PUF can attain 100% reliability statistically by discarding 34.47% fewer challenge-response pairs than the regular RO PUF. It is also ~3.7x more aging resilient than existing aging-resilient RO PUFs with ~2.38x lower power dissipation.

Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices

Currently the semiconductor industry is in search of a Physically-Unclonable-Function (PUF) implementation, which combines high reliability and uniqueness with low area and power consumption. The characteristics of emerging nanoscale Resistive Random Access Memory (ReRAM) devices fulfill most of these properties, as they exhibit inherent variability with low area consumption. Of particular interest is that the resistive states of ReRAM devices show a strong dependence on the distribution of grain boundaries within the device, which leads to variability in total device resistance. In this work we transform the classic CMOS time-delay PUF (TD-PUF) utilizing integrated nanoscale ReRAM devices to achieve better performance metrics including uniqueness and reliabilitiiy. The enhanced design exploits the property of high resistance variability of ReRAMs for the design of a ReRAM based delay stage that exhibits excellent uniqueness. Accurate simulation and characterization of the proposed PUF was achieved by extracting resistance values, temperature dependence and usage stress of ReRAM devices fabricated in-house and their application in the proposed TD-PUF are discussed. A 24 stage time-delay PUF utilizing 48 ReRAM devices was simulated and results show excellent reliability with respect to environmental parameters. A temperature range of 0 to 125°C was simulated and an optimum reliability was observed at 0.79 V. A supply voltage noise of ±30 mV had no impact on the uniqueness and reliability. The proposed design was compared against two pure CMOS implementations of a TD-PUF. The comparison was performed with respect to the aforementioned metrics and under the same environmental conditions, showing up to 5 times increase in performance.

Improved Reliability of FPGA-Based PUF Identification Generator Design

Physical unclonable functions (PUFs), a form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n -bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs and can consume excessive resources. To address these problems, in this article we present an efficient, lightweight, and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed that improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed post-characterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25°C to 70°C with ± 10% variation in the supply voltage.

Silicon photonic physical unclonable function.

Physical unclonable functions (PUFs) serve as a hardware source of private information that cannot be duplicated and have applications in hardware integrity and information security. Here we demonstrate a photonic PUF based on ultrafast nonlinear optical interactions in a chaotic silicon micro-cavity. The device is probed with a spectrally-encoded ultrashort optical pulse, which nonlinearly interacts with the micro-cavity. This interaction produces a highly complex and unpredictable, yet deterministic, ultrafast response that can serve as a unique "fingerprint" of the cavity and as a source of private information for the device's holder. Experimentally, we extract 17.1-kbit binary keys from six different photonic PUF designs and demonstrate the uniqueness and reproducibility of these keys. Furthermore, we experimentally test exact copies of the six photonic PUFs and demonstrate their unclonability due to unavoidable fabrication variations.

A comprehensive set of schemes for PUF response generation

In this paper we present a comprehensive set of schemes to generate Physical Unclonable Function (PUF) IDs out of raw results generated by multiple PUF designs. Software scripts have been developed to generate the PUF IDs using five different schemes. We also propose a set of PUF metrics that are based on the Worst Case (WC) PUF performance. Values of these metrics, for the Ring Oscillator (RO) PUF and SR-Latch PUF, have been presented and analyzed in the paper. Additionally, the effect of choosing different parameters on PUF quality metrics is thoroughly analyzed.

DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication

A physically unclonable function (PUF) is an irreversible probabilistic function that produces a random bit string. It is simple to implement but hard to predict and emulate. PUFs have been widely proposed as security primitives to provide device identification and authentication. In this paper, we propose a novel dynamic-memory-based PUF [dynamic RAM PUF (DRAM PUF)] for the authentication of electronic hardware systems. The DRAM PUF relies on the fact that the capacitor in the DRAM initializes to random values at startup time. Most PUF designs require custom circuits to convert unique analog characteristics into digital bits, but using our method, no extra circuitry is required to achieve a reliable 128-bit PUF. The results show that the proposed DRAM PUF provides a large number of input patterns (challenges) compared with other memory-based PUF circuits such as static RAM PUFs. Our DRAM PUFs provide highly unique PUFs with a 0.4937 average interdie Hamming distance. We also propose an enrollment algorithm to achieve highly reliable results to generate PUF identifications for system-level security. This algorithm has been validated on real DRAMs with an experimental setup to test different operating conditions.

Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test

Unpredictability is an important security property of Physically Unclonable Function (PUF) in the context of statistical attacks, where the correlation between challenge-response pairs is explicitly exploited. In the existing literature on PUFs, the Hamming Distance Test, denoted by HDT( t ), was proposed to evaluate the unpredictability of PUFs, which is a simplified case of the Propagation Criterion test PC( t ). The objective of these test schemes is to estimate the output transition probability when there are t or fewer than t bits flips, and ideally this probability value should be 0.5. In this work, we show that aforementioned two test schemes are not enough to ensure the unpredictability of a PUF design. We propose a new test, which is denoted as HDT( e , t ). This test scheme is a fine-tuned version of the previous schemes, as it considers the flipping bit pattern vector e along with parameter t . As a contribution, we provide a comprehensive discussion and analytic interpretation of HDT( t ), PC( t ), and HDT( e , t ) test schemes for Arbiter PUF (APUF), Exclusive-OR (XOR) PUF, and Lightweight Secure PUF (LSPUF). Our analysis establishes that HDT( e , t ) test is more general in comparison with HDT( t ) and PC( t ) tests. In addition, we demonstrate a few scenarios where the adversary can exploit the information obtained from the analysis of HDT( e , t ) properties of APUF, XOR PUF, and LSPUF to develop statistical attacks on them, if the ideal value of HDT( e , t ) = 0.5 is not achieved for a given PUF. We validate our theoretical observations using the simulated and Field Programmable Gate Array (FPGA) implemented APUF, XOR PUF, and LSPUF designs.

A physical unclonable function based on a 2‐transistor subthreshold voltage divider

SummaryIn this paper, a compact circuit solution for silicon‐based static physical unclonable functions (PUFs) is presented. The proposed solution exploits the variability of a simple voltage divider, implemented by two identical series‐connected nMOSFETs in a commercial 65‐nm CMOS process, to generate a random and stable nanokey. Both the transistors are biased in the subthreshold regime to enhance the output voltage dispersion and consequently the variability of the PUF response. The bit key generation is obtained by comparing the analog outputs of a pair of voltage dividers. Monte Carlo simulations on 10,000 samples have been performed to deduce the design guidelines for transistor sizing aimed at ensuring a high robustness of the PUF response against noise, supply voltage, and temperature variations. When compared with some state‐of‐the‐art PUF designs, the proposed circuit solution proves to be a promising and competitive candidate for implementing analog and static PUFs featuring small area occupancy, low‐power features, and high reliability. Copyright © 2016 John Wiley & Sons, Ltd.

STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability

Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement low-cost device authentication and secure secret key generation. Weak PUF s (i.e., devices able to generate a single signature or to deal with a limited number of challenges) are widely discussed in literature. One of the most investigated solutions today is based on SRAMs. However, the rapid development of low-power, high-density, high-performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. In this article, we propose an innovative PUF design based on STT-MRAM memory. We exploit the high variability affecting the electrical resistance of the Magnetic Tunnel Junction (MTJ) device in anti-parallel magnetization. We will demonstrate that the proposed solution is robust, unclonable, and unpredictable.

Improved ring oscillator PUF on FPGA and its properties

PUFs (Physical Unclonable Function) are increasingly used in proposals of security architectures for device identification and cryptographic key generation. Many PUF designs for FPGAs proposed up to this day are based on ring oscillators (RO). The classical approach is to compare frequencies of ROs and produce a single output bit from each pair of ROs based on the result of comparison of their frequencies. This ROPUF design requires all ROs to be mutually symmetric and also the number of pairs of ROs is limited in order to preserve the independence of bits in the PUF response. This led us to design a new ROPUF on FPGA which is capable of generating multiple output bits from each pair of ROs and is also allowing to create higher number of pairs of ROs, thereby making the use of ROs more efficient than the classical approach. Our PUF design is based on selecting a particular part of a counter value and using it for the PUF output. By applying Gray code on the counter values, we have considerably improved the PUF’s statistical properties. In principle, this PUF design does not need the ROs to be mutually symmetric, however, it is shown that this ROPUF design has significantly better properties with varying supply voltage when symmetric ROs are used. All of the presented measurements were performed on Digilent Basys 2 FPGA Boards (Xilinx Spartan3E-100 CP132). In this work, we provide a more detailed description of the PUF design on FPGA and the behaviour of ROs with varying supply voltage. Our proposed PUF architecture offers more output bits with required statistical properties from each RO pair than the classical approach, where frequencies of ROs are compared. The presented improvements significantly reduce the dependence on fluctuation of supply voltage.

Emerging Physical Unclonable Functions With Nanotechnology

Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs.

A Novel Thyristor-Based Silicon Physical Unclonable Function

This paper describes a new silicon physical unclonable function (PUF) using thyristor components that can be fabricated on a standard CMOS process. Our proposed design is built using thyristor-based sensors, time difference amplifier (TDA), time difference comparator, voting mechanism, and diffusion algorithm circuit. Multiple identical thyristor-based sensors are fabricated on the same chip. Due to the manufacturing process variations, each sensor produces two slightly different delay values that can be compared in order to create a digital identification for the chip. Diffusion algorithm circuit further ensures that the proposed PUF is able to effectively identify a population of integrated circuits. We also improve the stability of PUF design with respect to temporary environmental variations, such as temperature and supply voltage with the introduction of TDA and voting mechanism. The thyristor-based PUF is fabricated in a 0.18- $\mu \text{m}$ CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of a uniform distribution and a high stability of 96.8% with respect to temperature variation from −40 °C to 100 °C, and supply voltage variation from 1.7 to 1.9 V.

Proposal and Properties of Ring Oscillator-Based PUF on FPGA

This paper deals with design of physical unclonable functions (PUFs) based on field-programmable gate array (FPGA). The goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. Therefore, a design of a ring oscillator (RO)-based PUF producing more output bits from each RO pair is presented. 24 Digilent Basys 2 FPGA boards (Spartan-3E) and 6 Digilent Nexys 3 FPGA boards (Spartan-6) were tested and statistically evaluated indicating suitability of the proposed design for device identification. A stable PUF output is required for generating cryptographic keys. As post-processing technique to further improve the efficiency of this PUF design, we used Gray code on the obtained bits from RO pairs. Ultimately, the PUF design is combined with error correction code and together with Gray code is able to generate cryptographic keys of sufficient length.

Experimental Characterization of Physical Unclonable Function Based on 1 kb Resistive Random Access Memory Arrays

In this letter, we propose a reliable design of physical unclonable function (PUF) exploiting resistive random access memory (RRAM). Unlike the conventional silicon PUFs based on manufacturing process variation, the randomness of RRAM PUF comes from the stochastic switching mechanism and intrinsic variability of the RRAM devices. RRAM PUF’s characteristics, such as uniqueness and reliability, are evaluated on 1 kb HfO2-based 1-transistor-1-resistor (1T1R) arrays. Our experimental results show that the selection of the reference current significantly affects the uniqueness. More dummy cells to generate the reference can improve the uniqueness of RRAM. The reliability of RRAM PUF is determined by the RRAM data retention. A new design is proposed where the sum of the readout currents of multiple RRAM cells is used for generating one response bit, which statistically minimizes the risk of early lifetime failure. The experimental results show that with eight cells per bit, the retention time is more than 50 h at 150 °C or equivalently 10 years at 69 °C. This experimental work demonstrates that RRAM PUF is a viable technology for hardware security primitive with inter-Hamming distance 49.8% and intra-Hamming distance 0%.

Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs

Physically unclonable functions (PUFs) are an innovative way to generate device unique keys using uncontrollable production tolerances. In this work, we present a method to use PUFs on modern FPGA-based system-on-chips (SoCs). The processor system part of the SoC is used to configure the FPGA part. We propose a reconfigurable PUF design that can be changed by using the partial reconfiguration (PR) feature of modern FPGAs. Multiple ring oscillator PUF (RO PUF) designs are loaded on the same logic blocks of the FPGA in order to make use of different resources, i.e., sources of entropy, on the FPGA. Their frequencies are read out individually and the differences between neighbored oscillators are used to generate a bit response. The responses of each design can be concatenated to a larger response vector that can be used to generate a cryptographic key. We present an implementation that is able to decrease the needed resources by 87.5% on a Xilinx Zynq.

Hardware/software co-design of physical unclonable function based authentications on FPGAs

Physical Unclonable Functions (PUFs) enable the generation of device-unique, on-chip, and digital identifiers by exploiting the manufacturing process variation. The past decade has seen an extensive effort in PUF design. Yet, most PUF constructions are regarded as stand-alone hardware building blocks. In contrast, we propose PUF constructions that are tightly integrated into the design of a micro-processor. The proposed PUFs are essentially a collection of time-to-digital converters that are integrated into the custom instruction or memory-mapped interface of a processor. Therefore, the processor can issue the PUF challenges and collect the associated responses using instruction executions. This integration enables practical, run-time physical authentication and it allows flexible post-processing mechanisms using software. In this article, we describe the design, implementation, and the performance analysis details of such hardware/software co-designed authentication mechanisms on FPGAs. We propose two variants of the PUF architecture: a synchronous module that requires minimal place and route constraints utilizing the common clock of the SoC, and an asynchronous alternative that is independent of the clock but realized with a controlled placement. We implemented the synchronous architecture on the Altera Cyclone-IV FPGAs and performed a large-scale characterization on 55 boards. The asynchronous design is realized on the Xilinx Virtex-5 FPGAs and tested on 100 boards. Measurements reveal that the proposed solutions can authenticate trillions of devices and provide better performance than the ring oscillator based alternative.

A new physical unclonable function architecture**Project supported by the National Natural Science Foundation of China (No. 61376031).

This paper describes a new silicon physical unclonable function (PUF) architecture that can be fabricated on a standard CMOS process. Our proposed architecture is built using process sensors, difference amplifier, comparator, voting mechanism and diffusion algorithm circuit. Multiple identical process sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different physical characteristic values that can be compared in order to create a digital identification for the chip. The diffusion algorithm circuit ensures further that the PUF based on the proposed architecture is able to effectively identify a population of ICs. We also improve the stability of PUF design with respect to temporary environmental variations like temperature and supply voltage with the introduction of difference amplifier and voting mechanism. The PUF built on the proposed architecture is fabricated in 0.18 μm CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of uniform distribution and a high stability of 98.1% with respect to temperature variation from −40 to 100 °C, and supply voltage variation from 1.7 to 1.9 V.