Physical Unclonable Functions Architectures Research Articles

CalyPSO: An Enhanced Search Optimization based Framework to Model Delay-based PUFs

Delay-based Physically Unclonable Functions (PUFs) are a popular choice for “keyless” cryptography in low-power devices. However, they have been subjected to modeling attacks using Machine Learning (ML) approaches, leading to improved PUF designs that resist ML-based attacks. On the contrary, evolutionary search (ES) based modeling approaches have garnered little attention compared to their ML counterparts due to their limited success. In this work, we revisit the problem of modeling delaybased PUFs using ES algorithms and identify drawbacks in present state-of-the-art genetic algorithms (GA) when applied to PUFs. This leads to the design of a new ES-based algorithm called CalyPSO, inspired by Particle Swarm Optimization (PSO) techniques, which is fundamentally different from classic genetic algorithm design rationale. This allows CalyPSO to avoid the pitfalls of textbook GA and mount successful modeling attacks on a variety of delay-based PUFs, including k-XOR APUF variants. Empirically, we show attacks for the parameter choices of k as high as 20, for which there are no reported ML or ES-based attacks without exploiting additional information like reliability or power/timing side-channels. We further show that CalyPSO can invade PUF designs like interpose-PUFs (i-PUFs) and (previously unattacked) LP-PUFs, which attempt to enhance ML robustness by obfuscating the input challenge. Furthermore, we evolve CalyPSO to CalyPSO++ by observing that the PUF compositions do not alter the input challenge dimensions, allowing the attacker to investigate cross-architecture modeling. This allows us to model a k-XOR APUF using a (k − 1)-XOR APUF as well as perform cross-architectural modeling of BRPUF and i-PUF using k-XOR APUF variants. CalyPSO++ provides the first modeling attack on 4 LP-PUF by reducing it to a 4-XOR APUF. Finally, we demonstrate the potency of CalyPSO and CalyPSO++ by successfully modeling various PUF architectures on noisy simulations as well as real-world hardware implementations.

A robust architecture of ring oscillator PUF: Enhancing cryptographic security with configurability

Physically Unclonable Functions (PUFs) are becoming more widely recognized as tamper-resistant, high-entropy hardware security primitives. Leveraging the intrinsic manufacturing properties of integrated circuits, PUFs provide a lightweight, cost-effective technique for device identification and cryptographic key generation. Despite the existence of various PUF designs and architectures, the ring oscillator (RO) PUF stands out as one of the most notable. This significance is due to its simplicity of implementation and outstanding performance metrics. However, traditional RO-PUFs are often classified as weak PUFs because they support a limited size of input-output combinations. This paper introduces a configurable inversion unit designed to construct a lightweight, robust architecture configurable (RAC) RO-PUF. The proposed unit comprises an XOR gate, an XNOR gate, and a multiplexer. The RACRO-PUF significantly increases the size of generated output bits while efficiently utilizing minimal hardware resources. The performance of the RACRO-PUF stands out in evaluations, recording a uniqueness of 49.78 %, uniformity of 49.42 %, reliability of 97.72 %, and impressive randomness of 98.34 %.

Non Fungible Gratings as Physical Unclonable Functions

Physical Unclonable Functions (PUFs) are physical devices exploiting intrinsic randomness through the fabrication process that can be used for authentication and secure key generation. In this article, we describe a novel weak PUF architecture based on the inscription of random gratings in an optical fiber, which can be easily interrogated by a commercial instrument due to the enhanced backscatter. With PUF lengths of only 40 mm, we show that the false positive and false negative probabilities can reach below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-27</sup> . We also describe a temperature and strain compensation algorithm to mitigate environmental fluctuations. Furthermore, we describe an alternative technique which increases the number of bits used for digitizing the PUF's signature, thus significantly decreasing the false identification probabilities by almost two orders of magnitude.

Voltage-controlled magnetic anisotropy based physical unclonable function

We design a spintronic physical unclonable function (PUF) based on sub-100 nm voltage-controlled magnetic anisotropy hybrid magnetic tunnel junctions (VCMA-MTJs). This complementary metal-oxide-semiconductor VCMA-MTJ (CMOS/VCMA-MTJ) PUF architecture was evaluated by combining micromagnetic simulations, Verilog-A modeling, and circuit-level simulations. The PUF architecture, comprising four 16 rows × 16 columns arrays, demonstrates effective read and write operations using conventional voltage sensing that are orders of magnitudes lower than previous spintronic-based PUFs. This study proves the potential of the proposed solution in security applications based on hardware authentication.

A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks

Modeling attacks such as machine learning attacks are pretty efficient in breaking hardware security primitives like silicon strong physical unclonable functions (PUFs). As compared to regular strong PUFs such as arbiter PUFs and lightweight (LW)-PUFs, subthreshold current array (SCA)-PUFs exhibit a better resilience against modeling attacks since they utilize the non-linear relationship between the subthreshold current and gate voltage of transistors to obfuscate the corresponding relationship between input challenge and output response. Unfortunately, the degree of non-linearity (DoNL) within SCA-PUFs is still not sufficiently high to resist against state-of-the-art modeling attacks. Therefore, to further enhance DoNL for resisting against modeling attacks, a new strong PUF architecture is proposed in this paper by embedding reconfigurable neural networks (RNNs) into SCA-PUFs. Mathematical foundations are established for finding appropriate RNNs that are able to maximize the DoNL of an SCA-PUF. As shown in the result, when state-of-the-art modeling attacks like Lagrange multiplier attacks (LMAs) are selected, the robustness of the proposed RNN-embedded SCA-PUF is enhanced over 20 times with less than 18.5% power and area overhead as compared to a regular SCA-PUF.

Highly Reliable and Secure PUF Using Resistive Memory Integrated Into a 28 nm CMOS Process

Owing to the increased demand for secure communication channels and authentication steps, physical unclonable functions (PUFs) are increasingly important for hardware security. In this article, we report a novel PUF architecture and generation scheme that utilizes the inherent program-time variation of resistive random access memory (ReRAM) cells as an entropy source. ReRAM cells are integrated into a standard 28 nm CMOS manufacturing process, and also show robust non-volatile memory operation. We generated a PUF data set larger than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text{8}}$</tex-math> </inline-formula> bits and verified its randomness using a standard NIST test suite. Further verifications such as inter-and intra-hamming distance, 150 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C data retention of PUF bits, and spatial co-relation tests confirm the high reliability of the generated PUF keys.

Shrink Generator-based Strong PUF Architecture with Improved Uniqueness and Reliability on an FPGA

Silicon-based Physically Unclonable Functions (PUFs) are a source of physical security primitive that is either implemented on ASICs or FPGAs. A class of these security primitives that provide an exponentially large set of Challenge- Response Pairs (CRPs) is termed Strong PUF. That notwithstanding, the Arbiter and Feedforward Arbiter PUFs which are traditionally Strong PUFs, are not suitable for FPGA implementation. In this paper, a newly proposed PUF architecture that improves on the existing Configurable Ring Oscillator (CRO) PUF by increasing its dynamic configurability and its level of entropy is presented. To maintain the exponentially large set of CRPs, the Shrink Generator is applied to the traditionally Weak CRO-PUF. The proposed design is implemented and tested on a spartan-6 FPGA board using the Xilinx ISE tool. The proposed architecture demonstrates a uniqueness of 50.01% and is 96.43% reliable.

Suitability of Generalized GAROs on FPGAs as PUFs or TRNGs Considering Spatial Correlations

In the last years, guaranteeing the security in IoT communications has become an essential task. In this paper, the bias of a wide set of oscillators has been studied to determine their suitability as both True Random Number Generators (TRNGs) and Physically Unclonable Functions (PUFs). For this purpose, a generic configurable structure has been proposed and implemented in an FPGA. With this implementation, by introducing some external signals it is possible to configure the system in different oscillator topologies. This way, we have managed to analyze 2730 oscillators composed by 7 Lookup Tables (LUTs) without having to resynthesize the code each time. The performed analysis has included conventional ring oscillators, Galois ring oscillators and newly proposed oscillator topologies. From this analysis we have concluded that none of these oscillators behave as an ideal TRNG but ring oscillators present the closest to an ideal behavior. Regarding their suitability as PUFs, some of the newly proposed oscillators in this paper present a high reproducibility, higher than that of conventional ring oscillator PUF (RO-PUF) and a high uniqueness. Furthermore, we have noticed that both their reproducibility and their uniqueness tend to improve when increasing the length of the oscillators, which opens the possibility of finding new oscillators with even better properties by studying oscillators of bigger lengths. Finally, by studying the spatial correlation of the bias of these oscillators, we have observed that they present a much lower spatial correlation compared to the ring oscillators, which opens the possibility of using these oscillators in PUF architectures that use more comparisons than typical RO-PUFs.

Enhancing Strong PUF Security With Nonmonotonic Response Quantization

Strong physical unclonable functions (PUFs) provide a low-cost authentication primitive for resource-constrained devices. However, most strong PUF architectures can be modeled through learning algorithms with a limited number of CRPs. In this article, we introduce the concept of nonmonotonic response quantization for strong PUFs. Responses depend not only on which path is faster but also on the distance between the arriving signals. Our experiments show that the resulting PUF has increased security against learning attacks. To demonstrate, we designed and implemented a nonmonotonically quantized ring oscillator-based PUF in 65-nm technology. Measurement results show nearly ideal uniformity and uniqueness with a bit error rate of 13.4% over the temperature range from 0 °C to 50 °C.

Memristor-based PUF for lightweight cryptographic randomness

Physical unclonable functions (PUF) are cryptographic primitives employed to generate true and intrinsic randomness which is critical for cryptographic and secure applications. Thus, the PUF output (response) has properties that can be utilized in building a true random number generator (TRNG) for security applications. The most popular PUF architectures are transistor-based and they focus on exploiting the uncontrollable process variations in conventional CMOS fabrication technology. Recent development in emerging technology such as memristor-based models provides an opportunity to achieve a robust and lightweight PUF architecture. Memristor-based PUF has proven to be more resilient to attacks such as hardware reverse engineering attacks. In this paper, we design a lightweight and low-cost memristor PUF and verify it against cryptographic randomness tests achieving a unique, reliable, irreversible random sequence output. The current research demonstrates the architecture of a low-cost, high endurance Cu/HfO_2/p^{++}Si memristor-based PUF (MR-PUF) which is compatible with advanced CMOS technologies. This paper explores the 15 NIST cryptographic randomness tests that have been applied to our Cu/HfO_2/p^{++}Si MR-PUF. Moreover, security properties such as uniformity, uniqueness, and repeatability of our MR-PUF have been tested in this paper and validated. Additionally, this paper explores the applicability of our MR-PUF on block ciphers to improve the randomness achieved within the encryption process. Our MR-PUF has been used on block ciphers to construct a TRNG cipher block that successfully passed the NIST tests. Additionally, this paper investigated MR-PUF within a new authenticated key exchange and mutual authentication protocol between the head-end system (HES) and smart meters (SM)s in an advanced metering infrastructure (AMI) for smartgrids. The authenticated key exchange protocol utilized within the AMI was verified in this paper to meet the essential security when it comes to randomness by successfully passing the NIST tests without a post-processing algorithm.

A survey on silicon PUFs

Integrated Circuits (ICs) and electronic devices have become an integral part of daily human life (mobile, home, car, etc.). However, specific security measures should be taken to protect the communicated information to and from these devices. However, the existing conventional security primitives require large amounts of memory capacity, processing power, and energy resources that contradict the specific nature of devices. On the other hand, they store secret keys on the devices for future use, making them vulnerable to physical attacks. A new concept, known as Physically Unclonable Functions (PUFs), has been recently investigated to mitigate this problem. A PUF is a hardware-specific security primitive uses the randomness found in the disorder of physical media caused by the manufacturing variation process to provide cryptographic functionalities. Consequently, PUFs are inexpensive to fabricate, prohibitively challenging to duplicate, admit no compact mathematical representation, and are intrinsically tamper-resistant. This manuscript gives a complete survey of PUFs as a promising research field in security with a wide application, especially with connected devices. First, we motivate our contribution by comparing it with the existing surveys about PUFs. Then we provide the needed background to understand PUF architectures and applications by covering: the variability and randomness concepts, their classes, and properties. Then, we survey the existing initiatives related to silicon PUFs in terms of implementation and design used to extract unique secret information from the physical characteristics of an integrated circuit. In addition, we compare the surveyed works in terms of performance and security. Furthermore, we classify and compare the existing silicon PUF applications and use cases. Before concluding, we give the principal metrics used to evaluate the PUFs’ performance and present some related attacks. Finally, we talk about the current limitations of silicon PUF architectures and applications, and we look at and talk about research opportunities and major trends.

Design and Evaluation of a Tunable PUF Architecture for FPGAs

FPGA-based Physical Unclonable Functions (PUF) have emerged as a viable alternative to permanent key storage by turning effects of inaccuracies during the manufacturing process of a chip into a unique, FPGA-intrinsic secret. However, many fixed PUF designs may suffer from unsatisfactory statistical properties in terms of uniqueness, uniformity, and robustness. Moreover, a PUF signature may alter over time due to aging or changing operating conditions, rendering a PUF insecure in the worst case. As a remedy, we propose CHOICE , a novel class of FPGA-based PUF designs with tunable uniqueness and reliability characteristics. By the use of addressable shift registers available on an FPGA, we show that a wide configuration space for adjusting a device-specific PUF response is obtained without any sacrifice of randomness. In particular, we demonstrate the concept of address-tunable propagation delays, whereby we are able to increase or decrease the probability of obtaining “ 1 ”s in the PUF response. Experimental evaluations on a group of six 28 nm Xilinx Artix-7 FPGAs show that CHOICE PUFs provide a large range of configurations to allow a fine-tuning to an average uniqueness between 49% and 51%, while simultaneously achieving bit error rates below 1.5%, thus outperforming state-of-the-art PUF designs. Moreover, with only a single FPGA slice per PUF bit, CHOICE is one of the smallest PUF designs currently available for FPGAs. It is well-known that signal propagation delays are affected by temperature, as the operating temperature impacts the internal currents of transistors that ultimately make up the circuit. We therefore comprehensively investigate how temperature variations affect the PUF response and demonstrate how the tunability of CHOICE enables us to determine configurations that show a high robustness to such variations. As a case study, we present a cryptographic key generation scheme based on CHOICE PUF responses as device-intrinsic secret and investigate the design objectives resource costs, performance, and temperature robustness to show the practicability of our approach.

Inconsistency of Simulation and Practice in Delay-based Strong PUFs

The developments in the areas of strong Physical Unclonable Functions (PUFs) predicate an ongoing struggle between designers and attackers. Such a combat motivated the atmosphere of open research, hence enhancing PUF designs in the presence of Machine Learning (ML) attacks. As an example of this controversy, at CHES 2019, a novel delay-based PUF (iPUF) has been introduced and claimed to be resistant against various ML and reliability attacks. At CHES 2020, a new divide-and-conquer modeling attack (splitting iPUF) has been presented showing the vulnerability of even large iPUF variants.Such attacks and analyses are naturally examined purely in the simulation domain, where some metrics like uniformity are assumed to be ideal. This assumption is motivated by a common belief that implementation defects (such as bias) may ease the attacks. In this paper, we highlight the critical role of uniformity in the success of ML attacks, and for the first time present a case where the bias originating from implementation defects hardens certain learning problems in complex PUF architectures. We present the result of our investigations conducted on a cluster of 100 Xilinx Artix 7 FPGAs, showing the incapability of the splitting iPUF attack to model even small iPUF instances when facing a slight non-uniformity. In fact, our findings imply that non-ideal conditions due to implementation defects should also be considered when developing an attack vector on complex PUF architectures like iPUF. On the other hand, we observe a relatively low uniqueness even when following the suggestions made by the iPUF’s original authors with respect to the FPGA implementations, which indeed questions the promised physical unclonability.

Current mirror based CSI arbiter PUFs for generation of reliable secure keys

At present due to emergence of digital technologies into all spheres of human life demands for hardware security due to enhanced online shopping and payments through mobiles. In this regard light weight and tamper resistive cryptographic Physical Unclonable Functions (PUFs) with the unique set of responses are considered as fitted hardware security solution. In this paper we proposed an arbiter PUF to encounter the two major issues like uniqueness and reliability by employing current mirror based inverters at each delay stage and this configuration significantly Reduce the curve and widen the delay difference between the two symmetric daisy-chain delay paths that can be selected by the input challenge. The charging and discharge flow of the current starter inverters is considerably smaller and the propagation delay is blurred to temperature differences. Therefore we can easily achieve high reliability compared to existing PUF structures. The proposed current mirror-based CSI PUF architecture cadence is simulated using Virtuoso CMOS 45 nm technology and measures its performance metrics for statistical analysis and obtains ideal values.

Optimization of Memristive Crossbar Array for Physical Unclonable Function Applications

Memristive crossbar Physical Unclonable Function (PUF) structures are emerging as strong security primitives for resource-constrained devices demanding good retention time, negligible standby power, small size, and ultra-low power operating requirements. Memristive PUF exploits the inherent high process variations of a memristor as a source of entropy to generate device-specific signatures. These PUFs need to be strong enough to deal with active and passive attacks as well as machine learning attacks, hence requires more device-to-device variability. Memristive PUF requires dense crossbar architecture to generate unique, uniform, and reliable device signatures. Dense memristive crossbars (Xbar) face the challenges of low noise margin, proper load resistance selection, scalability, and a precise sense circuitry at the load resistance side to read the resistive state of a memristor accurately. In this work, we have simulated and optimized the load resistance of memristive scaled up crossbar arrays. We have used two of our fabricated devices for memristive crossbar PUF simulation. The proposed crossbar PUF architecture satisfies the basic PUF evaluation metrics and improves noise margin (NM). The load resistance is optimized through MATLAB simulation. The impact of optimized load resistance on Xbar architecture is observed to be noticeable and around 18% improvement in the noise margin was observed when the crossbar is scaled up from 16×2 to 128×2.

Design and Implementation of Enhanced PUF Architecture onFPGA

ABSTRACT Physical un-clonable functions (PUF) play important role in hardware security due to its random response generation. It offers a wide range of security applications, such as key generation, digital rights management, and Field Programmable Gate Array (FPGA) intellectual property (IP) protection. In literature, several PUF structures of both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) are used to improve the performance parameter, mainly reliability and uniqueness. Because of the large number of challenges and responses pairs (CRPS), Arbiter PUF (APUF) is widely used but suffers from less reliability and uniqueness. The proposed PUF structure is designed to achieve the ideal value of performance metrics and also to reduce the prediction rate. This paper presents a new approach to design Double Feed-Forward XOR Arbiter PUF (DFFX APUF), is a combination of Feed-Forward Arbiter PUF, the output of this combination is XORed to generate the single response. Newly proposed PUF is implemented on Xilinx Virtex-6 FPGA. The reliability and uniqueness are the parameters to evaluate the performance of the DFFX APUF and is compared with the Feed-Froward APUF and Double-APUF. The proposed PUF architecture results, the uniqueness of 5% and reliability of 8% greater than FF-APUF and Double-APUF.

Design, Analysis and Application of Embedded Resistive RAM Based Strong Arbiter PUF

Resistive Random Access Memory (RRAM) based Physical Unclonable Function (PUF) designs exploit either the probabilistic switching or the resistance variability during forming, SET and RESET processes of RRAM. Memory PUFs using RRAM are typically weak PUFs due to fewer number of challenge response pairs. We propose a strong arbiter PUF based on 1T-1R bit cell which is designed from conventional RRAM memory array with minimally invasive changes. Conventional voltage sense amplifier is repurposed to act like an arbiter and generate the response. Similarly, address and data lines are repurposed to act as challenge and response bits respectively. The PUF is simulated using 65 nm predictive technology models for CMOS and Verilog-A model for a hafnium oxide based RRAM. The proposed PUF architecture is evaluated for uniqueness, uniformity and reliability for various number of stages. It demonstrates mean intra-die Hamming Distance (HD) of 0.135 percent and inter-die HD of 51.4 percent, and passes the NIST tests. We study the vulnerability of proposed PUF to machine learning attacks. We also present an application of proposed PUF for data attestation in the internet of things. Proposed PUF-based data attestation consumes 9.88pJ of total energy per data block of 64-bits and offers a speed of 120.7 kbps.

Multibit-Generating Pulsewidth-Based Memristive-PUF Structure and Circuit Implementation

As Internet of Things (IoT) devices have evolved, physical unclonable functions (PUFs) have become a popular solution for hardware security. In particular, memristor devices are receiving attention as suitable candidates for reliable PUFs because they can be integrated into nano-cross point array circuits with ultra-high efficiency. However, it has been found that typical 1-bit generating PUFs consume too many challenge–response pairs (CRPs) to generate a single response. This issue has to be overcome to construct a strong and reliable PUF with a large number of valid CRPs. We suggest a bank design and quantizing entropy source method for constructing a multibit-generating PUF. In this paper, we propose a new pulsewidth-based memristive PUF (pm-PUF) architecture that incorporates analog memristor devices and a nano-cross point array. We describe the architecture’s circuit implementation and its operating process in detail. We also evaluate the inter and intra performances of the pm-PUF in terms of randomness, diffuseness, uniqueness, and steadiness to show that the proposed pm-PUF will be a promising solution for a high-density hardware security system.

Machine Learning Attacks and Countermeasures for PUF-Based IoT Edge Node Security

The Internet of things (IoT) ecosystem has grown exponentially with the convergence of various technologies such as deep learning, sensor systems, and advances in computing platforms. With such a highly pervasive nature of “smart” devices, the nature of data being collected and processed can be increasingly private and require safeguards to ensure the data’s integrity and security. Physically unclonable functions (PUFs) have emerged as a lightweight, viable security protocol in the Internet of Things (IoT) framework. Malicious modeling of PUF architectures has proven to be difficult due to the inherently stochastic nature of PUF architectures. In this work, we show that knowledge of the underlying PUF structure is unnecessary to clone a PUF. We tackle the problem of cloning PUF-based edge nodes in different settings such as unencrypted, encrypted, and obfuscated challenges in an IoT framework. We present a novel non-invasive, architecture-independent, machine learning attack for robust PUF designs and can handle encryption and obfuscation-based security measures on the transmitted challenge response pairs (CRPs). We show that the proposed framework can successfully clone different PUF architectures, including those encrypted using two (2) different encryption protocols in DES and AES and with varying degrees of obfuscation. We also show that the proposed approach outperforms a two-stage brute force attack model. Finally, we offer a machine learning-based countermeasure, a discriminator, which can distinguish cloned PUF devices and authentic PUFs with an average accuracy of 96%. The proposed discriminator can be used for rapidly authenticating millions of IoT nodes remotely from the cloud server.

Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications

Physically unclonable functions (PUF) are digital fingerprints which generate high entropy, temper-resilient keys and/or chip-identifiers for security applications. When considering the miniaturized hardware development for the Internet of Things (IoT), security is of high importance. In this case, PUF designing using SRAM or D flip-flops are quite common but with compromised uniqueness due to the limited silicon area. In this work, a symmetric tri-state D flip-flop based lightweight PUF is proposed with increased uniqueness. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers a uniqueness of 0.4994, which is the highest among all the considered architectures. Compared to the Arbiter PUF the proposed architecture has 0.267 $$\times$$, 0.064 $$\times$$, and 0.043 $$\times$$ less, power, silicon area, and energy per bit, respectively. Similarly, when compared with the Ring Oscillator PUF, the proposed architecture has 0.017 $$\times$$, 0.031 $$\times$$, and 0.0005 $$\times$$ less, power, silicon area, and energy per bit, respectively. Also, unlike other flip-flop based PUF, the proposed one does not require any post-processing block to remove the bias, thus contributes to saving the total implementation area and power of the system. An FPGA implementation is also presented as a proof-of-concept to verify functional correctness. For a better performance comparison among the considered architectures, a novel figure of merit (FOM) considering power, reliability, delay, silicon area, and uniqueness has been proposed, and it is observed that the proposed architecture offers the highest FOM among considered PUF architectures.