Abstract
At present due to emergence of digital technologies into all spheres of human life demands for hardware security due to enhanced online shopping and payments through mobiles. In this regard light weight and tamper resistive cryptographic Physical Unclonable Functions (PUFs) with the unique set of responses are considered as fitted hardware security solution. In this paper we proposed an arbiter PUF to encounter the two major issues like uniqueness and reliability by employing current mirror based inverters at each delay stage and this configuration significantly Reduce the curve and widen the delay difference between the two symmetric daisy-chain delay paths that can be selected by the input challenge. The charging and discharge flow of the current starter inverters is considerably smaller and the propagation delay is blurred to temperature differences. Therefore we can easily achieve high reliability compared to existing PUF structures. The proposed current mirror-based CSI PUF architecture cadence is simulated using Virtuoso CMOS 45 nm technology and measures its performance metrics for statistical analysis and obtains ideal values.
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