Physical Design Stage Research Articles

Performance analysis of meta-heuristic optimization techniques for multi-objective VLSI circuit partitioning

Abstract The efficiency of various stages of physical design in the Very Large Scale Integration (VLSI) circuit can be enhanced by using multi-objective optimization techniques. The circuit is partitioned into a set of modules at the beginning of the physical design phase. This step is known as circuit partitioning. All subsequent physical design stages, like floor planning, placement, pin configuration, and routing etc, are influenced by the outcome of the circuit partitioning method being used. The efficiency of the partitioning method controls the quality of ultimate architecture. The efficiency achieved by the final product may be decreased by incorrect partitioning. This study compares the effectiveness of four Meta-heuristic optimization methods include the Genetic Algorithm (GA), Satin Bowered Bird (SBO), Particle Swarm Optimization (PSO), Simulated Annealing (SA) — in terms of number of net cut, duration of sleeping mode, and efficiency in power consumption for addressing the VLSI circuit partitioning problem. This experiment achieves K-way partitioning of the circuit that minimizes net cuts as well as maximizes sleep duration simultaneously, by evaluating optimization function. Solutions developed using GA, SBO and PSO consistently surpass those acquired using SA with respect to quality of optimal solution. The average optimum net cut and sleep duration achieved by this experiment are 10.7 and 9.9 in GA ; 11.5 and 12.3 in SBO, 11.80 and 9.10 in PSO; and 16.8 and 6.7 in SA based method respectively. This research resulted in a considerable reduction in power consumption, with the system’s average power efficiency achieved by 21.6%, 26.84%, 19.85%, and 14.62%, respectively, in GA, SBO , PSO, and SA based optimizations. The experimental results are compared with a recent publication and proposed GA, SBO, and PSO based methods achieve 18.75%, 4.17%, and 1.04% improvement in terms of average net cut respectively. The proposed GA, SBO, PSO and SA based methods also achieve 44.90%, 51.30%, 40.05%, and 18.60% improvement in terms of average power efficiency.

Three-Stage Rapid Physical Design Algorithm for Continuous-Flow Microfluidic Biochips Considering Actual Fluid Manipulations

With the continuous development of microfluidic technology, continuous-flow microfluidic biochips (CFMBs) are being increasingly used in the Internet of Things. The automation design of CFMBs has also received widespread attention. The architecture design of CFMBs is divided into a high-level synthesis stage and a physical design stage. Among them, the problem of the physical design stage is very complex. At this stage, the chip architecture is generated based on the device library and a set of flow paths, taking into account the actual fluid manipulations, while minimizing the cost of the chip, such as the number of ports, total length of flow channels, number of flow channel intersections. As fabrication technology advances, the number of devices integrated into CFMBs is increasing. The existing physical design algorithms can no longer meet the design requirements of CFMBs in terms of time. Therefore, we propose a three-stage rapid physical design algorithm for CFMBs considering the actual fluid manipulations. The proposed algorithm includes a port-driven preprocessing stage, a force-directed quadratic placement stage, and a negotiation-based routing stage. In the port-driven preprocessing stage, a port-driven preprocessing algorithm is proposed to generate connection matrices between ports and devices to reduce the number of ports introduced. In the force-directed quadratic placement stage, we model the placement problem as an extremum problem of a quadratic cost function, which mathematically reduces the search space significantly and shortens the running time of the algorithm significantly. In the negotiation-based routing stage, a heuristic negotiation-based routing algorithm and a flow channel strategy that prioritizes the construction of parallel execution are proposed to reduce the running time of the algorithm while ensuring that the number of crossings in the routing solution is close to the optimal solution. Experimental results confirm that our proposed method is able to generate the high-quality solutions quickly. Under general scale problems, compared to the existing method based on ILP, our proposed method achieves a speedup ratio of 23,171 in terms of CPU time and optimizations in terms of number of ports and port reuse of 3.18% and 6.52%, respectively. These optimizations come at the cost of only a slight increase in the number of intersections, the flow length, and the number of flow valves. In addition, our proposed method can effectively solve large-scale problems that cannot be solved by existing method based on ILP.

A Machine Learning-Based Short-Circuit Power Prediction at Floorplan Stage of IC Physical Design

This work is devoted to the study of the use of machine learning (ML) to predict short-circuit power consumption at the floorplan stage of the physical design of integrated circuits. The study was carried out for 4 cell groups: registers, combinational cells, sequential cells, and cells included in the clock network. An Arithmetic Logic Unit was selected and designed to create a database necessary for the training and testing of ML models. The design is carried out for various combinations of parameters. Input parameters for training models are supply voltage, temperature, clock frequency, library type based on threshold voltage, block utilization and block aspect ratio. The output parameters are the values of short-circuit power after gate level simulation, considering the parasitic parameters. In total, five algorithms were tested: Polynomial Regression, Decision Tree Regression, Random Forest Regression, Supported Vector Regression (SVR) and Multi-layer Perceptron (MLP). Root Mean Squared Error, R2 and Mean Absolute Percentage Error (MAPE) metrics were used to evaluate the performance of the models. The MLP showed the best performance, but the SVR algorithm with standardization of output parameters showed similar results with significantly less training time. The MAPE value for registers is » 0,89 %, for combinational cells » 3,19 %, for sequential cells » 2,42 % and for the clock network cells » 9,55 %. The proposed method of model training is not based on any technology-dependent data, which makes it universal for different technology nodes. The disadvantage of the method is the need for implementation of the whole design flow for a selected design with the selected range of parameters for collecting necessary training data, which requires additional time and machine resources.

Goods Inventory Information Systems Based on the Fast Concept at SDN 07 Sidang Danau

Inventory data collection activities in schools are still manual and the data tracking system is not yet available because the inventory data collection system in schools is not well managed so that it often makes it difficult to search for data on existing items. The inventory data collection system running at SDN 07 Sindang Danau still uses a simple computerized system utilizing standard office (Microsoft Office Excel and Word). This allows for many errors in processing inventory data, and causes inventory data collection managed by SDN 07 Sindang Danau to be less efficient. , As well as resulting in difficulties in searching for data and taking up a relatively long time in preparing reports. To help solve this problem, it is necessary to have a web-based inventory data system using the FAST concept (framework for the application of system thinking) which has 6 stages of scope definition, problem analysis, requirements analysis, logical design, decision analysis and physical design.

TF-Predictor: Transformer-Based Prerouting Path Delay Prediction Framework

Timing mismatch between different stages of physical design poses great challenges for circuit optimization to achieve the desired performance, power and area (PPA) tradeoff. The inaccurate timing estimation prior to routing may lead to over-design with unwanted power and area consumption or iterating back to cell placement at the cost of design turn-around time. Existing learning models could not predict post-routing circuit timing with satisfying accuracy and efficiency due to the limitations of the ignorance of delay correlation along the timing path and the empirical feature selection solutions. In this work, an accurate and efficient pre-routing path delay prediction framework is proposed by utilizing transformer network and residual model with an ensemble feature selection mechanism. Owing to the combined filter and wrapper methods, an ensemble feature selection mechanism is implemented to determine the optimal feature subset based on the timing and physical information at the placement stage for path delay prediction, which is extracted as feature sequences for each cell along the timing path to be trained by transformer network. With the residual model, the predicted timing mismatch between the placement and routing stages by transformer network is further calibrated to estimate the post-routing path delay. The proposed framework has been validated with ISCAS’85 and OpenCores benchmark circuits for the prediction of post-routing path delay, where the perdition error in terms of rRMSE is limited within 1.3% and 3.0% and the correlation coefficient R is higher than 0.999 and 0.995 for seen and unseen circuits respectively, indicating an error reduction by 2.3 10.6 times compared by prior learning-based models. In addition, the framework achieves average three orders of magnitude speedup compared with the commercial tools and is accelerated by a factor of 14 128 as against the competitive learning models, which is promising to be applied to guide design optimization prior to time-consuming routing stage.

DEVELOPMENT OF SHARIA ACCOUNTING SYSTEM IN THE AGRICULTURAL SECTOR (SITASI) WITH PILOT CONVERSION METHOD

This research was initiated because of a request from the Jaya Makmur Gapoktan, Tonjong District, Brebes Regency which needed an application for its business books. Currently, Gapoktan Tonjong is still doing the bookkeeping manually. Gapoktan Jaya Makmur runs its business in the field of savings and loans with an interest system. However, in practice, this business is more similar to financing with a profit-sharing system that is in accordance with sharia principles. This study develops a sharia accounting system in agriculture that can help Gapoktan Jaya Makmur in keeping its business books. System development includes the stages of system analysis, conceptual design, physical design and implementation. For the implementation phase, the researcher uses the pilot conversion method. The results of this study indicate that there are Gapoktan in Brebes Regency that is still running a business in the field of savings and loans with an interest system. However, there are also those who run a business in the financing sector, which is similar to the mudharabah principle, although it still needs further adjustments. This sharia accounting system in agriculture was developed by default for this type of business financing with the mudharabah system. For Gapoktan who wants to use this application, it is necessary to be given an understanding of the basic concepts of accounting, mudharabah principles, and assistance in the preparation of financial statements.

Method of designing the system of classes of the subject area model on the basis of the architecture of integrated objects

The article presents a method of designing the system of software classes, which includes the stages of conceptual, logical and physical design of classes with the implementation of a software system in the architecture of integrated objects. The input data for design is the model of the subject area, which is obtained as the result of object-oriented analysis, which is represented by conceptual, mathematical and semantic models. The conceptual model defines the entities and attributes of entities and is considered as the basis for designing the properties of classes. Mathematical model, as a dynamic model of entity behavior, is formally or informally defined by mathematical formulas, algorithms, diagrams or descriptions of the implementation, which is the basis for designing class methods. The semantic model defines the concepts of subject area in relation to the elements of its model and includes identifiers, meaningful names and descriptions used for the design, programming and implementation of system functionality in terms of subject area. The proposed design method is based on the following principles: normalization of classes (reduction of data to atomic values, reduction of class methods arguments and removal of redundant class methods), replacement of inheritance by logical composition and physical integration, decapsulation (separation of physical functional model from logical data model), virtualization of classes (logical model of classes are considered as a set of relational data model and physical functional model of class methods), interrelation of models (end-to-end mapping of conceptual model on logical and physical model, and class implementation). The essence of the method is to perform successive stages of design: normalization of conceptual model, logical design of classes (transformation of mathematical model into normalized functional model, design and analysis of class characteristics), physical design of classes in architecture of integrated objects (creation of classes, mapping of logical classes on physical classes, implementation of classes in programming language). Actually, the developed design method leads to the creation of a model focused on solving problems, when instances of entities are not created entirely and only the properties and methods that are needed to calculate the desired results for given input values are used. An example of application of the method for a certain subject area with demonstration of design results is considered, and also the approach on the basis of query language of formulation of problems in terms of subject area with generation of source code in programming language is shown. The application of the method allows to increase the efficiency of creating software systems due to the non-redundancy of the system of classes and parameters of class methods, reuse of code and selection of the minimum required set of properties and class methods when solving specific problems.

A survey on machine learning-based routing for VLSI physical design

Routing is one of the most important and time-consuming stages of physical design. As the process node of semiconductors keeps scaling down, the routing process faces increasing challenges, and the traditional solutions are not sufficiently efficient. In recent years, machine learning has aroused much interest in this context, and an increasing number of algorithms have introduced advanced machine learning techniques to help solve the routing problem. In this paper, we survey the recent development of machine learning-based routing algorithms.

ANALISIS PERANCANGAN SISTEM INFORMASI AKUNTANSI PENGGAJIAN PADA YAYASAN MASJID NURUL HUDA JATIWARINGIN

This research was conducted at Yayasan Masjid Nurul Huda Jatiwaringin which is an institution that moves in the education field. The purpose of this study is to find out and evaluate the payroll accounting information system that is running on the Yayasan Masjid Nurul Huda Jatiwaringin and to provide an alternative design of payroll accounting information system at Yayasan Masjid Nurul Huda Jatiwaringin. The data used in this study are primary data obtained directly from the Nurul Huda Mosque Foundation Jatiwaringin and secondary data obtained in the form that is already in the form of publication. The analytical tool used in this research is a qualitative descriptive analysis tool by conducting system analysis, which then proceeds with a conceptual design sketch by designing a flowchart, Data Flow Diagram (DFD), Entity Relationship Diagram (ERD), and Normalization. After that proceed to the physical design stage but only limited to the design of database design, input and output design. Based on the results of the study the authors found that the salary system run by the foundation is less effective because there is still a double task on the treasurer, and also the document sheet used still does not meet the needs of the system. In addition, the absence of authorization activities of employee attendance list performed by the timekeeping function and outgoing cash proof documents has not been authorized by the accounting function. Furthermore, the authors designed a payroll accounting information system that is able to overcome the weaknesses and shortcomings.

DrPlace: A Deep Learning Based Routability-Driven VLSI Placement Algorithm

<p indent=0mm>In order to improve the routability of deep learning based placement algorithms in the VLSI physical design stage, on the basis of open source placement algorithm DREAMPlace, a deep learning based routability-driven VLSI placement algorithm named DrPlace is proposed. The framework of the algorithm model is composed of deep learning based routability-driven global placement, routability-driven legalization, and routability-driven detailed placement. The algorithm adds the pin density function into the global placement model and proposes an efficient GPU implementation of pin density key kernel. According to the experiment results on ISPD 2011 and DAC 2012 benchmark suites, the algorithm improves the routability of the DREAMPlace and is more effective than traditional routability-driven placement algorithms.

Analyzing Clustering and Partitioning Problems in Selected VLSI Models

As the modern integrated circuit continues to grow in complexity, the design of very large-scale integrated (VLSI) circuits involves massive teams employing state-of-the-art computer-aided design (CAD) tools. An old yet significant CAD problem for VLSI circuits is physical design automation. In physical design automation, we need to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface. The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for combinatorial circuits, there are several models for the clustering problem. In particular, we consider the problem of clustering without replication in combinatorial circuits with a view towards minimizing delay (CN). The corresponding problem with replication has been well-studied and solvable in polynomial time. However, replication can become expensive when it is unbounded. Consequently, CN is a problem worth investigating. We establish the computational complexities of several variants of CN. Additionally, we obtain approximability and inapproximability results for some NP-hard variants of CN. We also present approximation and exact exponential algorithms for some variants of CN. We prove that for some cases there exists an approximation factor of strictly less than two and that our exact exponential algorithms beat brute force. Furthermore, we provide the first parameterized approximation algorithm in which the approximation ratio is also a parameter.

Pengembangan Prototype Sistem E-Commerce pada Ajun Elektronik dengan Metode FAST

While the development of information technology is very influential for the progress of a business, promoting a business that is owned, then one of them by using an ecommerce website. E-commerce is a trading activity carried out online through a website.&#x0D; Problems in electronic adjunct stores Stores still use a conventional system where if a buyer wants to buy the desired item, the buyer must come directly to the store and this condition makes marketing and sales hampered by distance and time. In addition, the promotion at Arjun Electronics Store has not been fully implemented properly because it is only done by directly informing buyers who come to the shop. the purpose of this research is to produce a system that can provide ease of introducing products in the electronic adjuncts and sell all electronic products for household needs. With e-commerce site that is able to provide information about goods to customers quickly through internet network technology. Where asthe FAST method is a fairly flexible framework for various types of projects and strategies. System development with the FAST method is carried out sequentially which includes the stages of scope definition, problem analysis, needs analysis, logical design, decision analysis, physical design and integration, construction and testing, insralation and delivery, The results of this study in the form of website-based e-commerce optimization. With this website, stores can expand marketing, consumers become easier to get information about goods without having to come to the Electronic Adjunct Store and with the (e-commerce), the store can facilitate the conventional transaction process that has been conventional to be modern and can certainly make it easier to create sales reports that were previously still manual.

Analisis Perancangan Sistem Informasi Akuntansi Penggajian Pada Yayasan Masjid Nurul Huda Jatiwaringin

This research was conducted at Yayasan Masjid Nurul Huda Jatiwaringin which is an institution that moves in the education field. The purpose of this study is to find out and evaluate the payroll accounting information system that is running on the Yayasan Masjid Nurul Huda Jatiwaringin and to provide an alternative design of payroll accounting information system at Yayasan Masjid Nurul Huda Jatiwaringin. The data used in this study are primary data obtained directly from the Nurul Huda Mosque Foundation Jatiwaringin and secondary data obtained in the form that is already in the form of publication . The analytical tool used in this research is a qualitative descriptive analysis tool by conducting system analysis, which then proceeds with conceptual design sketch by designing flowchart, Data Flow Diagram (DFD), Entity Relationship Diagram (ERD), and Normalization . After that proceed to the physical design stage but only limited to the design of database design, input and output design. Based on the results of the study the authors found that the salary system run by the foundation is less effective because there is still a double task on the treasurer, and also the document sheet used still does not meet the needs of the system. In addition, the absence of authorization activities of employee attendance list performed by the timekeeping function and outgoing cash proof documents has not been authorized by the accounting function. Furthermore the authors designed a payroll accounting information system that is able to overcome the weaknesses and shortcomings

Full-chip wire-oriented back-end-of-line TDDB hotspot detection and lifetime analysis

Time-dependent dielectric breakdown (TDDB) has become an important cause of failure for inter-metal dielectrics (IMD) in integrated circuits as feature sizes continue to shrink and novel materials are introduced. Although many studies have been conducted to understand the underlying physics of this issue, not enough work has been focused on evaluating TDDB lifetime of practical chip designs in the physical design stage. This paper proposes a full-chip TDDB failure analysis methodology to evaluate lifetime and identify TDDB hotspots in VLSI layouts, which are essentially interconnect wires that have high failure risk due to TDDB. The proposed method features three new techniques compared to existing methods. First, we have developed a partitioning-based scheme to deal with scaling of full-chip analysis by partitioning the full chip layout into small tiles. Second, for each tile, the new method calculates a newly-introduced TDDB failure metric called TDDB Damage for vulnerable wires. Such a wire-oriented TDDB analysis is the first of its kind and is very amenable for physical design as the wires can be easily adjusted or re-routed for TDDB-aware optimization. Third, the new method considers the impact of the non-uniform electric field calculated using the finite element method (FEM), which significantly improves the accuracy of TDDB risk evaluation. Experimental results show that the proposed new TDDB analysis method is more accurate than a recently proposed full-chip TDDB analysis method in which electrical field is treated as a constant value. Additionally, the proposed method can analyze a practical VLSI layout in a few hours.

Clustering without replication in combinatorial circuits

The modern integrated circuit is one of the most complex products engineered to date. It continues to grow in complexity as years progress. As a result, very large-scale integrated (VLSI) circuit design now involves massive design teams employing state-of-the-art computer-aided design (CAD) tools. One of the oldest, yet most important CAD problems for VLSI circuits is physical design automation, where one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface (Lim in Practical problems in VLSI physical design automation, Springer, Dordrecht, 2008). The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for combinatorial circuits, there exists several models for the clustering problem. In particular, we consider the problem of clustering in combinatorial circuits for delay minimization, without permitting logic replication (CN). The problem of clustering for delay minimization when logic replication is allowed (CA) has been well-studied and is known to be solvable in polynomial time (Lawler et al. in IEEE Trans Comput 18(1):47–57, 1969; Rajaraman and Wong, in: 30th ACM/IEEE design automation conference, pp 309–314, 1993). However, unbounded logic replication can be quite expensive. It follows that CN is an important problem. We show that selected variants of CN are NP-hard. We also obtain approximability and inapproximability results for some of these problems. A preliminary version of this paper appears in Donovan et al. (in: 9th International conference on combinatorial optimization and applications, COCOA 2015, Proceedings, pp 334–347, 2015).

An Effective Method for Interconnect Delay Optimization of ASIC’s

With the development of integrated circuit design into 65nm process, interconnect delay has become one of the key factors that hinder the convergence of time sequence. Firstly, the determinants of interconnect delay are analyzed by Elmore delay model, and then experiments are carried out at the stage of circuit physical design. Verify the metal layer, metal width, buffer driving ability and buffer number can effectively optimize the interconnect delay.

Database schema invariant to subject domains and its distinctive features

The desire to avoid unnecessary costs inherent in the traditional methodology of creating relational databases, not only at the stages of conceptual and logical design, but also at the stage of physical design, has actualized the task of developing a database schema that is invariant to subject domains. The main developed and distinguishing elements of this scheme are as follows: composition, structure of the basic relations; implementation of integrity constraints; means ensuring the database security.

ANALYSIS AND DESIGN CASH SALES ACCOUNTING INFORMATION SYSTEM AT UTAMA ALUMINIUM STORES

This research was conducted at Utama Aluminum Store which is a company engaged in general trading or general supplier and manufacture of various doors, frames, windows, X Panda, mosquito wire, and window displays. The purpose of this study was to determine and evaluate the cash sales accounting information system that was running at Utama Aluminum Store and to provide an alternative design of cash sales accounting information systems at Utama Aluminum Store. The data used in this study are primary data obtained directly from Utama Aluminum Store and secondary data obtained in the form that has been in the form of publications. The analytical tool used in this study is a qualitative descriptive analysis tool by analyzing the system using the COSO method, which then continues the conceptual design phase by designing a document flow chart (flowchart), Data Flow Diagram (DFD), Entity Relationship Diagram (ERD), Normalization. After that proceed to the physical design stage but only limited to designing database design, input, and output design. Based on the results of the study, the researchers found that the cash sales system run by the company was less effective because there were still a number of tasks in the sales section, and the warehouse section, and also the documents used were still not meeting the system requirements. In addition, the resulting report is a sales report that is only recorded in a book that can cause the resulting report to be ineffective and cause fraud. Furthermore, the researchers designed a cash sales accounting information system that is able to overcome these weaknesses and shortcomings. Keywords: Analysis, Accounting Information System, Cash Sales, Design

Perancangan Sistem Informasi Perpustakaan AMIK STIEKOM Sumatera Utara Berbasis Teknologi Radio Frekuensi Identification (RFID)

This study describes the data structure in designing and building an AMIK STIEKOM North Sumatra library information system using Radio Frequency Identification (RFID) based on client servers. The author hopes that readers will better understand the problem solving of parking that is more integrated and well-documented and efficient in its operations. The data structure that has been designed is able to identify the number of participants who have been equipped with Radio Frequency Identification (RFID) library system technology. Students who borrow or return books are selected through application technology in accordance with student data I recorded in the database. Only data on students / I who are registered in the database can borrow and return books to the AMIK STIEKOM North Sumatra library. The process of selecting data in the library system with RFID technology is carried out in three stages, namely the logical design stage, the physical design stage, and the interface design stage.

A Connectivity-Based Legalization Scheme for Standard Cell Placement

Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalization. In this step the manufacturability of the design is directly settled, and the quality of the solution, in terms of wirelength, congestion, timing and power consumption is indirectly defined. Since the heavy lifting regarding processing is performed by global placers, fast legalization solutions are protruded in state-of-the-art design flows. In this paper we propose and evaluate a legalization scheme that surpasses in execution speed two of the most widely used legalizers, without not only corrupting the quality of the final solution in terms of interconnection wirelength but improving it in the process.