Phase-locked Loop Research Articles

Overcoming the relative bandwidth limitations of single VCO frequency synthesizers by implementing a novel PLL architecture

Abstract Frequency-modulated continuous-wave radar systems profit from increasing the absolute bandwidths of the generated frequency chirps to improve range resolution. As the relative bandwidth of SiGe-voltage-controlled oscillators (VCOs) is limited to about 80%, increasing the center frequency fundamentally or via frequency multiplication is the most direct way to increase that absolute bandwidth. However, as some applications require penetration depth, which dramatically decreases with frequency, other solutions are necessary. Therefore, state-of-the-art concepts rely on the down-conversion of generated frequency chirps via two separately stabilized frequency sources. This article implements a novel architecture, offering relative bandwidths of >100% within a single phase-locked loop (PLL). Therefore, two VCOs at different center frequencies are fed into a down-conversion mixer, whose output is directly stabilized via that PLL with one loop filter generating both tuning voltages. Those circuit blocks can be summarized as one equivalent VCO, offering a higher relative bandwidth and a significantly more linear tuning curve. Thereby, a solution to limited relative bandwidths with high VCO gain variation of single VCO synthesizers is offered while substantially reducing the hardware and implementation effort compared to the state-of-the-art.

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications.

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is -80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

Improved flux linkage observer for position estimation of permanent magnet synchronous linear motor

Abstract. With the development of motor technology, sensorless control attracts more and more attention. In this paper, an improved flux linkage observer is proposed to overcome issues including inaccurate initial positions and sampling noise. The voltage and current models are combined, and a sliding-mode observer is designed based on the hybrid model to obtain the compensation voltage. Therefore, the estimated flux linkage after compensation can greatly resist the influence caused by inaccurate initial positions or sampling noise. Phase-locked loop technology is used to process the estimated flux linkage to get the stable estimated speed and position. The proposed scheme has a simple structure and only one parameter. It is easy to use and adjust in practice. The simulation and experimental results verify that the proposed algorithm is effective, and the estimated flux linkage and position is accurate with an inaccurate initial position.

Research on Implementation of a PWM Generation Algorithm for Train Stationary Stopping Frequency

In industrial electronic equipment or communication equipment, a reference clock should be generated for stable operation of the equipment, which requires precise and stable reference frequency generation. As a method for generating this reference frequency, an analog method called PLL (phase locked-loop) has been devised and widely used. However, in order to make a more precise and stable reference frequency simple and economical, a DDS (direct digital synthesizer) has been developed. In this paper, we propose a stable and accurate method to generate a low frequency of the PWM method via pure logic circuit configuration without a microprocessor for digital reference frequency generation. Depending on the electronic communication equipment, the required reference frequency varies from a low frequency to a very high frequency. The reference frequency synthesis required in these frequency bands has been studied in various ways, but in industries such as railways, the low-frequency band based on the DDS method is used. In particular, it is very important to operate without a single operating error or failure in order to obtain information for stopping the train. Therefore, it is necessary to design a pure logic method that excludes a stored program type processor that minimizes the possibility of temporary interruption due to disturbance such as surge or high voltage. Therefore, through this study, the algorithm is implemented so that the duty ratio is output at 50:50, the circuit is configured so that two target frequencies are generated at the same time, and the performance is verified by generating the low-frequency band used for stopping the railway train. It was confirmed that the accuracy and stability were improved compared to the analog method used for stopping the railway train, and it was verified that the frequency resolution was superior to the similar results obtained in the digital frequency synthesis field so far.

Stabilizing Fabry-Perot optical frequency comb with differential phase detection and bias compensation.

We present a stable optical frequency comb (OFC) that utilizes a Fabry-Perot phase modulator. The environmental-induced state variation of the OFC is accurately detected by measuring the relative phase changes of beat signals from its upper and lower sidebands. We then compensate for this variation by controlling OFC bias voltage through a homodyne phase-locked loop. The differential phase detection eliminates the common-mode detection noise, enabling long-term stability of the OFC without requiring any additional reference signal. The relative phase change is only 0.056° over 3800 s. Even under a drastic temperature change, the OFC remains stable, validating the effectiveness of the proposed stabilization method.

Doppler Parameters Estimation Using Digital PLL Based on SWIFT & αSWIFT Structures

A digital phase-locked loop (DPLL) based on sliding window infinite Fourier transform (SWIFT) and αSWIFT is proposed to extract the vibration and velocity parameters from the phase-modulated carrier signal. The phase of a carrier signal gets modulated when it is reflected from a vibration object due to the Doppler effect. Therefore, the phase-modulated carrier signal contains the Doppler signal that has the vibration information. The SWIFT or αSWIFT structure is designed from sliding discrete-time Fourier transform (DTFT) where the exponential window provides higher weightage to recent samples. It acts as a phase detector in the proposed DPLL, and its bandwidth can be varied based on the values of the time-constant. A controller unit, along with a bi-quad oscillator, is introduced in the proposed DPLL structure to remove any leakages in the system and to synchronize the system units in the parameter estimation. The proposed scheme is implemented in MATLAB/SIMULINK environment and validation for real-time applications is done using dSPACE 1202 MicrolabBox.

An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments

Among all the functions that electronics currently perform, clock synthesis has a backbone role. Charge pump phase-locked loops (CP-PLL) are widely used to accomplish clock synthesis thanks to their versatility. One of the most critical parts of CP-PLLs is the charge pump, which greatly influences the system’s performance. Even though several high-performance charge pumps have been proposed in the past, with the quick spread of electronics in all the engineering fields, the design of such electronic devices has encountered several additional challenges dictated by external environmental conditions. Examples of these engineering sectors are space, aerospace, industrial, and automotive applications, where the charge pump has to face high environmental temperatures and radiation effects. As a consequence, its design and experimental characterization have to be performed to ensure reliability when operating in harsh conditions. However, to the best of the authors’ knowledge, no works in the literature have ever presented a complete charge pump design and characterization in such harsh environments. Therefore, to fill this gap, this paper presents a charge pump for PLL applications specifically designed to reach operating temperatures up to 200 °C and total ionizing dose levels up to 100 Mrad. All design choices have been experimentally verified and are discussed throughout the paper in detail. With the proposed design, we obtained an output current variation of less than 8% at 200 °C and less than 2.5% at 100 Mrad. As opposed to the CPs that can be found in the literature, these results were measured on silicon. The performed measurements confirm that the current variation at 200 °C is better than that of the state-of-the-art CPs operating at lower temperatures, which, moreover, were only simulated.

Transient synchronization stability of photovoltaics integration by singular perturbation analysis

The integration of large-scale photovoltaics (PVs) into the power grid has significantly altered the transient synchronization dynamics of traditional power systems dominated by synchronous generators (SGs) and posed great challenges to modeling and analysis of PVs integration. In this paper, the transient synchronization stability of the PV-SG system is studied using the singular perturbation technique. Firstly, a nonlinear model of a PV-SG system is established to reveal the multiscale transient synchronization characteristics. Further, the full system is decomposed into a slow subsystem and a fast subsystem by the singular perturbation technique. The fast subsystem containing the dynamics of the DC voltage control, terminal voltage control, and phase-locked loop, and the slow subsystem containing the dynamics of rotor motion can perfectly reflect the dynamics of the full system within the electromagnetic and electromechanical timescales, respectively. The proposed model provides a clearer physical picture of dynamics in the PV-SG system within the electromagnetic and electromechanical timescales. Subsequently, the stability of the slow and fast subsystems is investigated using the energy function and eigenvalue analysis methods, respectively. Meanwhile, the impacts of various operating, control, and structural parameters on the transient synchronization stability are uncovered. Different from the most existing research endeavors on the wide simulations of the PVs integration, the impact of PVs on the synchronization dynamics of SGs without considering the dynamical characteristics of the PV system, and the transient synchronization stability analyses of the PLL-based voltage source converter systems, it is the key contribution to study the transient synchronization dynamical characteristics of the PV system and its interaction with the SG under different timescales. All these are helpful and easy to extend to more complicated PV-SG systems. Finally, the analysis results are validated by extensive simulations.

A current-configurable charge pump with current mismatch compensation for wide output frequency range phase-locked loop

To ensure the loop stability of a wide output frequency range phase-locked loop (PLL), a current-configurable technique for a charge pump (CP) is utilized to reduce the variation of PLL phase margin within a wide frequency range. An isolation transistor is inserted into a traditional current steering CP to improve the clock accuracy and reduce degradation of the PLL lock-in speed caused by switch control signal crosstalk on the output voltage. Furthermore, a feedback-based compensation technique is developed to reduce the mismatch between the charging and discharging currents of the proposed CP, thereby improving PLL output clock accuracy. Based on these techniques, a CP circuit is designed with 0.18 μm CMOS technology and occupies an active area of 0.005 mm2. Simulation results from different process corners operated at 1.8 V show that the maximum mismatch between the charging and discharging currents of the CP decrease from 2 % to 0.6 % when the CP current is 10 μA over a temperature range from −40 ℃ to 85 ℃. The CP is used in a PLL with input and output frequencies of 25–100 MHz and 25–500 MHz, respectively. The worst phase margin of the PLL is improved from 31° to 52.3° by configuring the CP current over a range from 10 to 40 μA. The output clock accuracy of the PLL is optimized from 600 to 100 Hz/MHz under input and output frequencies of 100 and 500 MHz, respectively.

A Clutter Identification and Removal Method Based on Long Delay Lines and Cross-Correlation in Through-Wall Detection

Life detection is important in earthquake rescue, but weak vital signal is susceptible to interference by clutters. Due to the undesirable characteristics of the hardware, there are two main types of clutter generated by the frequency modulation continuous wave (FMCW) radar when transmitting signals. One is generated by periodic nonlinearity during frequency modulation, and the other is generated by the phase-locked loop spuriousness (PLLS) in frequency division. They cause additional beat frequencies to appear beside those from the target, leading to false alarms. Since the suppression measures for them are different, it is necessary to distinguish the types of clutter and choose appropriate suppression methods. In this paper, the accurate theoretical modeling of the effects of the periodic nonlinearity and phase-locked loop spuriousness on the beat signal is performed to determine distinctions between them. The clutter occurring in the system used is identified as originating from phase-locked loop spuriousness through fiber-optic experiments. A method using long delay lines and cross-correlation is proposed to identify and remove it. In experiments, the false alarm rate is reduced from over 50 percent to nearly 0 percent, providing strong evidence for the effectiveness of the proposed method in through-wall detection.

Research on three-level PWM Rectifier without grid voltage sensor

Traditional three-level PWM rectification technology usually uses voltage sensors to sample the grid voltage, and then obtains the angle information of the voltage vector through a phase-locked loop, thereby achieving the d/q axis control function of voltage and current. However, the use of voltage sensors not only increases system costs, but also increases system volume and debugging difficulty. In addition, when the voltage sensor is damaged, it can cause system shutdown and affect system reliability. After analyzing the three-level control method of PWM rectifiers, a sensorless control strategy for grid voltage based on sliding mode observer method is proposed. By using the sliding mode observer method to estimate the amplitude and phase of the power grid voltage at the voltage and current values of each PWM cycle, a phase-locked loop is used to determine the position of its voltage vector. The simulation results all demonstrate that the proposed method can accurately and effectively estimate the voltage vector angle of the power grid, and ensure that the output of the rectification system meets the standard voltage waveform.

Self-Measurement of the Admittance Matrix of AC–DC Power Converter by Internal Harmonic Injection

Frequency-domain impedance or admittance model is widely applied to analyze harmonic stability of power electronic converters. Conventionally, the converter impedance is modeled holistically, without exhibiting the sole effect of different control and phase-locked loop (PLL). Besides, harmonic voltage or current injection external to the converter is usually adopted, which involves dedicated equipment and introduces unexpected inner impedance. In this paper, the response of voltage perturbation upon AC-DC power converter along various voltage signal flow paths is analyzed, based on superposition principle. Each part of admittance and its effect on stability can therefore be quantified explicitly. By injecting harmonic perturbation through the identified paths within the converter controller, each part of admittances, with and without the concerned control or PLL blocks, are measured and summed to be the total admittance. Harmonic voltage mitigation control implemented on a grid-forming converter creates an ideal grid with constant voltage and nearly zero inner impedance at the injected harmonic frequency. The proposed admittance analysis and measurement is successfully applied to power converter with different PLL, voltage feedforward, output power control, DC voltage control and grid-forming cascaded control. Effectiveness of the analysis and the proposed admittance measurement approach are validated by comprehensive simulation and hardware test.

A Variable Carrier Generation for Heterodyne LDV with an Optical Phase-locked Loop

A heterodyne laser Doppler vibrometer (LDV) requires a frequency shifter to generate a carrier for the vibration information in the detector signal. The carrier frequency should be carefully selected in order to obtain the intended measurement range with a demodulation bandwidth that avoids existing noise sources. The traditional frequency shift in heterodyne LDV is realized with an acoustooptical modulator, which can only generate a fixed carrier frequency. In this paper, a variable carrier generation method based on an optical phase locked loop (OPLL) is demonstrated. Our setup implements a feedback loop to control the phase of the second laser to synchronize a reference laser. In lock-in status the carrier for the vibration information associated with a local oscillator signal. In this paper, we obtain the laser diode parameters relevant to performance and on the design of the photodetector and loop filter. Finally, the performance of the lock-in OPLL, variable carrier as well as velocity measurement is reported and the reliability of the proposed method is evaluated.

Commutation Point Optimization Method for Sensorless BLdc Motor Control Using Vector Phase Difference of Back EMF and Current

Commutation error is a crucial factor that reduces the efficiency of brushless dc (BLdc) motors. This article presents a commutation point optimization method for a sensorless BLdc motor. First, the sources of commutation error under position sensorless control are analyzed, and a conclusion is drawn that the phase difference between the back electromotive force vector and phase current vector equals the total commutation error. Second, a fundamental waveform extractor is used to eliminate the influence of harmonics on the equivalent commutation error. Third, the phase difference of the fundamental waveforms is extracted by a combined phase-locked loop, and the real-time commutation error is obtained consequently. Finally, accurate commutation is achieved by compensating for the phase difference, and experimental results on a reaction flywheel prototype evaluate the presented method.

Hybrid Feedforward Single-Phase Phase-Locked Loop for Accurate Measurement Offset Rejection and Frequency–Ramp Tracking

Hybrid Feedforward Single-Phase Phase-Locked Loop for Accurate Measurement Offset Rejection and Frequency–Ramp Tracking

PMSM Field-Oriented Control with Independent Speed and Flux Controllers for Continuous Operation under Open-Circuit Fault at Light Load Conditions

Presented in this article is a permanent magnet synchronous motor (PMSM) control under open-circuit fault (OCF) operation using field-oriented control (FOC) with independent speed and flux controllers. The independent control allows the motor to operate efficiently under varying conditions. A simplified control approach is employed to control the PMSM under the OCF situation; the actual flux and torque of the PMSM are directly measured by the stator currents, eliminating the need for estimators or phase-locked-loop (PLL) systems. Matlab/Simulink is employed for the simulation, while hardware experiments are conducted using a dSPACE DS1104. The simulation and the hardware results demonstrate the control method’s effectiveness in maintaining continuous motor operation during OCF, its robustness against OCF conditions, and its ability to adapt under varying conditions, including speed, flux, and load torque change.

A control method for the single-phase three-leg unified power quality conditioner without a phase-locked loop

The single-phase three-leg unified power quality conditioner (UPQC) can achieve the functions of voltage compensation, reactive power compensation, and harmonic compensation. However, traditional control algorithms require a phase-locked loop to obtain the real-time phase angle of the grid voltage, which undoubtedly increases algorithm complexity. To simplify the phase-locked calculation, this paper proposes a control method without the phase-locked loop for the single-phase three-leg UPQC. In the proposed scheme, the instantaneous value of the grid voltage is employed to realize the grid integration control. Then, the load voltage reference is calculated in real time using a second-order generalized integrator. Moreover, a simple algorithm for reactive power and harmonic compensation is discussed, further simplifying the control algorithm. Finally, a small-scale experimental platform is built, and the effectiveness of the proposed method is verified by the experimental results.

Fast Tracking the Fundamental component in Synchrophasors applications using the Recursive Corrected Phase Wavelet Transform

This paper presents the use of Recursive Corrected Phase Wavelet Transform to track harmonic components (always present in Power Systems), in order to determine the fundamental frequency “as soon as possible”, to provide appropriate input values to a non-linear algorithm that can accurately approach in only one cycle the amplitude and phase of the fundamental frequency. This technique is useful in real-time synchrophasors applications, specially for load identification and characterization. Based on the deepest descend method, the algorithm has less computational effort in comparison with phased locked loop.

Simulation based study of Maximum Power Point Tracking and Frequency Regulation for Stand-alone Solar Photovoltaic Systems

The main objective of this paper is to develop a simulation model of stand-alone solar photovoltaic (PV) system based on mathematical models. A maximum power point tracking (MPPT) algorithm based on incremental conductance method is applied to extract the maximum power from solar PV energy conversion system. A DC/DC boost converter allows the MPPT to control the intermediate voltage. To regulate to voltage at load side a voltage source converter (VSC) based controller is applied to generate the pulse signal for three-phase inverter. The frequency regulation controller is developed based on conventional phase locked loop (PLL) system along with resistive dumping loads. A simulation model based on mathematical model Matlab®/Simulink®/SimPower® is constructed interface. Results using from simulation are stated to demonstrate the behaviour of stand alone solar PV energy conversion system.

A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response times for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operations has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12 GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2 kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60 GHz system, a wide-bandwidth baseband digital variable-gain amplifier (DVGA) with a 3 dB bandwidth of more than 4 GHz also supports frequency division duplex (FDD) operations. The transceiver chip is fabricated using the Tower Jazz 0.18 µm SiGe BiCMOS process. With an on-board antenna, the transceiver covers all four channels in the 802.11ad standard, with MCS-12 (7.04 Gbps under 1.76 GSym/s and 16-QAM) under 1.5 m. In the proposed system design, the RF frontend-based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54 dB. To achieve a practical FD application, the SI is further suppressed with the help of a digital SI compensation. The measured power consumption for the transmitter and receiver configurations are 194 mW and 231 mW, respectively, in HD mode and 398 mW for the FDD or FD operation mode.