Phase-locked Loop Frequency Synthesizer Research Articles

A new triple-controlled type frequency synthesizer using simplified DDFS-driven digital hybrid PLL system

It is very important for the triple-controlled type frequency synthesizer to have fast switching speed, stable operation, low power consumption and wide bandwidth. For this goal, a new design method for triple-controlled type frequency synthesizer using the simplified DDFS-driven digital hybrid PLL synthesizer is presented. The simplified DDFS (direct digital frequency synthesizer) is used for the high frequency resolution, circuit simplicity, low power and high-speed switching. The digital hybrid PLL (phase locked loop) provides performance improvements such as high-speed switching, stable operation and high frequency applications. The proposed PLL synthesizer part has a hybrid structure and uses a composite signal of both the D/A converter output and the loop filter output to drive the VCO (voltage controlled oscillator), which makes the PLL frequency synthesizer operate in ultra-fast switching speed. Simulation results show the performance improvements of this synthesizer, as compared with the conventional PLL and stability is verified. Three frequency control parameters are properly used to operate the frequency synthesizer in various electronic applications. The method and results of frequency control parameter assignment are shown for several applications such as GSM, IMT-2000, Bluetooth and PCS system.

A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop

A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-/spl mu/m CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (K/sub VCO/) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply.

7.35 GHz PLL frequency synthesiser in 0.8 [micro sign]m silicon bipolar production technology

A 7.35 GHz phase-locked loop frequency synthesiser in a low-cost 0.8 µm/25 GHz silicon bipolar production technology (B6HF) is presented. The synthesiser offers a tuning range from 7.23 to 7.35 GHz at the supply voltage of 3 V, and phase-noise performance of –100.7 dBc/Hz at 100 kHz offset from the carrier.

A 2 GHz Phase-Locked Loop Frequency Synthesizer with On-Chip VCO

This paper discusses the implementation of the building blocks for a 2 GHz phase-locked loop frequency synthesizer in a standard 0.5 μm BiCMOS process. These blocks include a low-power optimized dual modulus prescaler which is able to operate with input frequencies up to 2.7 GHz, a phase detector with extremely constant gain throughout the input phase difference range, a chargepump with a rail-to-rail output, and an on-chip voltage-controlled oscillator.

On the speed-up of lock up time in the PLL frequency synthesizer

A new speed-up method of lock up time is proposed for the phase locked loop (PLL) frequency synthesizer in the local oscillation circuit of a radio receiver. Doubling of reference frequency is achieved by using a new (NN+ 1/2) programmable divider which enables a half division ratio, compared with that of a conventional divider, and it leads to a bigger loop gain K and the speed-up of lock up time. The experimental results of lock up time will be given together with the spectrum of the output frequency.

A new PLL frequency synthesizer using multi-programmable divider

In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multiprogrammable divider are shown by theoretical considerations and experimental results.

A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application

This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-/spl mu/m CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of /spl plusmn/25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm/sup 2/, the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter.

Fast settling PLL frequency synthesizer utilizing the frequency detector method speedup circuit

We propose two items for the fast frequency settling in the phase locked loop (PLL) frequency synthesizer. One is a PLL frequency synthesizer utilizing a frequency detector method speedup circuit (FDMSC). From the experimental results, it is observed that fast frequency settling can be achieved. The other is a shortcut lowpass filter (LPF) method with the FDMSC in the PLL frequency synthesizer. The frequency settling time has been speeded up further by changing the time constant of the LPF to a smaller value only in the rising condition.

An ultralow power CMOS/SIMOX programmable counter LSI

We designed and fabricated an extremely low-power CMOS/SIMOX programmable counter large scale integrated circuits (LSI) for high-speed phase-locked loop (PLL) frequency synthesizer applications. This was to verify the potential usefulness of ultrathin-film 0.24-/spl mu/m-gate CMOS/SIMOX process technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. While operating at up to 2.2 GHz and consuming only 4.5 mW at 1.5 V, it is capable of 4-GHz performance with power consumption of 19 mW at 2.5 V. Even at a low supply voltage of 1.5 V, high input-sensitivity was also achieved in the 1- to 2-GHz frequency range. These low-power and high input-sensitivity characteristics outperform those of state-of-the-art BiCMOS PLL LSIs.

Performance of phase-locked loop frequency synthesiser using accumulative phase detector

The performance of phase-locked loop circuits is critically dependent on the phase detector design. The author considers the use of an unusual phase detector that is capable of linear operation over an arbitrarily wide operating range. This provides the benefits of analytically predictable transient behaviour, without cycle slipping, under all likely conditions of operation and with the prospect of improved acquisition speed. The behaviour of phase-locked loops incorporating such a design is demonstrated analytically and subsequently confirmed by experimental results.

Fast-acquisition PLL synthesizer using a parallel N-stage cycle swallower with low power consumption and low phase noise

A phase-locked loop (PLL) frequency synthesizer with an N-stage cycle swallower (NSCS) is one of the fastest frequency switching synthesizers, but the use of the NSCS results in high power consumption and phase noise in the UHF band. This paper elucidates these problems and proposes a fast-acquisition PLL synthesizer using a novel type of NSCS with low power consumption and low phase noise. Experimental results confirm that the use of a parallel NSCS and a prescalar results in greatly reduced power consumption and phase noise.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Measurement of capacitance transients with attoFarad resolution in a microwave varactor diode after Co/sup 60/ irradiation

A high resolution measurement system was constructed to investigate transient capacitance changes in varactor diodes after exposure to Co/sup 60/ photons. These capacitance transients, while small, adversely affect the phase settling times of phase lock loops used in spread spectrum communications systems. The measurement system has a resolution of better than 10 aF, and details are given concerning its design and operation. It was used to study planar and mesa type Si varactor diodes. Small but significant changes in the capacitive transients were observed after irradiation. The behavior has been ascribed to the generation of bulk defects caused by displacement damage in the active layer of the diodes, although interface state generation at the oxide interfaces has not been ruled out. The effect of the changes in the diode transient responses on the settling time of a typical phase lock loop frequency synthesizer has been modeled. The introduction rate of the bulk traps has been estimated to be 1/spl times/10/sup -3/ to 4/spl times/10/sup -3/ cm/sup -1/ rad/sup -1/. >

A new PLL frequency synthesizer with high switching speed

A phase-locked loop (PLL) frequency synthesizer with high switching speed is proposed. Mobile communication networks are evolving towards microcellulars operating in narrowband TDMA and microwave bands to meet the rapidly increasing demands for both voice and data services. Therefore, synthesizers with high switching speed are required for the realization. However, it will be difficult for conventional synthesizers to provide switching times of shorter than 1 ms. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage-controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase; therefore, it does not need the band-limited loop filter which limits the ability of the loop to switch fast. The experimental results show that it can provide switching times as short as 0.1 ms, which is 10/sup 2/ approximately 10/sup 3/ times higher than conventional PLL synthesizers, and spurs of less than -60 dB.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of a fractional phase locked-loop frequency synthesiser using a Motorola based microcontroller

A Motorola M58HC11EVB board [1] is used in the design of a frequency synthesiser using a fractional phase-locked loop technique which synthesises frequencies that are integer plus fractional times higher than the reference frequency. The method uses a 68HC11 microprocessor to generate very stable reference frequencies [1]. A software program is designed to give great flexibility in selecting the reference over a desired operating range of frequencies. The ability to operate at low reference frequencies (≈10 Hz) enables the system to step in 1 Hz increments. A frequency synthesiser over the bands of 10–150 Hz, 100–1500 Hz, 1–15 kHz, and 10–150 kHz in steps of ±1 Hz, ±10 Hz, ±100 Hz and ± 1 kHz, respectively, is accomplished. The spectrum purity of the waveform for different frequencies is measured. Sideband frequencies of up to 50 dB below the synthesised frequency are observed.

New Digital Synthesizer LSI for FM/AM Receivers

Digital synthesizer tuners that have electronized the tuning section of radio receivers are steadily penetrating the market, backed by advancements in LSI technology. Systems employed by digital synthesizer tuners on the market today may roughly be classified into two categories, PLL (phase locked loop) frequency synthesizers and DAC (digital to analog converter) voltage synthesizers.

PLL IC Capable of Direct Division of FM Local Oscillator Frequency

Recently, a PLL frequency synthesizer, one of the applications of a phase-locked loop ( PLL ), has become popular with the advancement of IC technologies. It is, however, considerably difficult to apply it to high frequency systems such as FM radio tuners. 1)

A Monolithic ECL/I2L Phase-Locked Loop Frequency Synthesizer for AM/FM TV

Digital tuning systems are fast replacing the conventional mechanical systems in AM/FM and television receivers. The desirability of the digital approach is mainly due to the following operational features: *Precise tuning of station frequencies *Exact digital frequency display *Keyboard entry of desired frequency *Virtually unlimited station memory *Up/down scanning through the band *Station search (stop on next active station) *Power on to the last station *Easy option for time-of-day clock

A Linear CB Synthesizer

The recent boom in Citizens Band radio popularity, coupled with a shortage of crystals, has caused phase locked loop frequency synthesizers to be incorporated into new radio designs. A number of digital integrated circuits have been introduced which contain a reference oscillator, an oscillator divider, a programmable divider, and a phase detector. This paper reviews the requirements for the complete phase locked loop frequency synthesizer and presents a linear integrated circuit to complement the existing digital circuits and complete the system. The new circuit contains a voltage controlled oscillator, a crystal oscillator or buffer, a mixer, and logic circuitry to control the receive or transmit condition with an out-of-lock override switch.