Phase-locked Loop Frequency Synthesizer Research Articles

Acoustic detection of bearing faults through fractional harmonics lock-in amplification

Bearing failure detection in induction motors is vital to prevent breakdowns and dead times in industrial processes. Non-invasive detection of bearing faults can be performed by analyzing sound signals and the associated spectral signature. However, measured sound often contains signals from other surrounding sources of vibrations, which can pollute analysis or degrade SNR. This work proposes the use of Lock-In Amplification (LIA) for bearing fault detection in order to overcome SNR limitations and allow specific detection.In practice, LIA is synchronized to the motor shaft frequency through a fractional Phase-locked loop (PLL) frequency synthesizer, delivering characteristic frequencies for bearing faults, which are fractional harmonics of the shaft rotation frequency, and phase-locked to the motor under study.Comparison with Fourier spectrum measurements confirms the superior ability of LIA for extracting small signals from noise, but also allows specific detection, even in the presence of external sources vibrating at the same frequencies as the motor of interest. Additionally, fractional harmonics LIA was able to detect characteristic frequencies from fault-free conditions, paving the way for earlier failure detection and continuous monitoring.This work is the first reported experimental implementation of fractional harmonics LIA for bearing fault detection purposes.

АНАЛИЗ ПЕРЕХОДНЫХ ПРОЦЕССОВ В СИНТЕЗАТОРАХ ЧАСТОТ С РАЗЛИЧНЫМИ ХАРАКТЕРИСТИКАМИ НЕЛИНЕЙНОГО ЗВЕНА В КОНТУРЕ ФАЗОВОЙ АВТОПОДСТРОЙКОЙ ЧАСТОТЫ

Phase-locked loop (PLL) frequency synthesizers that use phase detectors (PD) with variousnonlinear transfer characteristics have been considered. The goal of this work is comparative analysisof the frequency synthesizers operation speed depending on the type of the PD nonlinearity andmathematical description of the PD nonlinear characteristic which ensure the maximum operationspeed of the frequency synthesizer. In accordance with the present goal, the following problems aresolved in this work: the generalized model of the PLL frequency synthesizer is developed; mathematicalmodels of static characteristics of the PLL system nonlinear link are described when using varioustypes of known PDs and a modified PD with aperiodic characteristic; the analysis of the PLLsystem dynamics when changing the static characteristic of the nonlinear link is carried out. Themodified PD provides relay control of transient processes when a large phase difference occurs.Numerical evaluation of the PLL synthesizers operation speed depending on the initial frequencydeviation have been obtained when using known PDs and the modified PD. It is shown that the use ofthe modified PD allows to reduce frequency settling time about 1.5 times in comparison with the bestin operation speed conventional PD. Optimal values of the control signal ensuring the maximumoperation speed of the PLL synthesizer with the modified PD have been obtained for the specifiedfrequency deviations in the large disturbance mode. The results of this work are valid for PLL frequencysynthesizers of the UHF, L, S and C-bands (from 300 MHz to 8 GHz) which are used in wirelesscommunication systems of the fourth generation (4G) and the fifth generation (5G).

A 2–20-GHz Ultralow Phase Noise Signal Source Using a Microwave Oscillator Locked to a Mode-Locked Laser

In this article, we develop the theory of a special type of optoelectronic phase-locked loop (PLL). The output signal of this type of PLL is in the electrical domain and its reference oscillator, typically a mode-locked laser, operates in the optical domain. The PLL uses a balanced optical microwave phase detector (BOMPD). In order to model the optoelectronic PLL, the nonlinear characteristic function and the gain of the BOMPD are derived analytically. Using the results of the phase detector analysis, the theory of an optoelectronic PLL using such a phase detector is developed. Based on the theoretical analysis, a broadband optoelectronic frequency synthesizer with a programmable frequency range from 2 to 20 GHz is designed and implemented. Phase noise measurements show that the optoelectronic PLL frequency synthesizer achieves an integrated rms-jitter (1 kHz-100 MHz) of less than 4 fs in the frequency range from 5 to 20 GHz with a typical value of 4 fs and a minimum of 3 fs. This is the first reported wideband PLL frequency synthesizer achieving sub-10-fs integrated rms-jitter (1 kHz-100 MHz) in the frequency range from 3 to 20 GHz. A comparison with best-in-class laboratory-grade frequency synthesizers in this frequency range shows that this synthesizer achieves lower phase noise than any electronic frequency synthesizer for offset frequencies larger than 2 kHz.

A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets

In this article, we present a crystal-less Bluetooth low-energy (BLE) transmitter using RF reference recovery directly from GFSK-modulated BLE packets. In order to achieve fast frequency calibration from modulated signals and reduce interference from other BLE users, the transceiver consists of a back-channel wake-up receiver, a clock-recovery receiver, a transmitter, and a dual-all-digital phase-locked loop (ADPLL) frequency synthesizer for system wake-up, clock-recovery, packet transmission, and frequency calibration. An embedded averaging processing unit in the loop filter of the ADPLL is proposed to retrieve accurate frequency information from GFSK-modulated signals. A prototype chip is fabricated in 40-nm CMOS for verification. The crystal-less transmitter with clock recovery meets all BLE requirements for SIR, making this a robust solution for removing the crystal even in densely populated networks.

An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer

A fully integrated energy-efficient 10-Gb/s millimeter-wave transceiver with direct-modulation digital transmitter (TX) and I/ Q phase-coupled frequency synthesizer in 65 nm CMOS is presented. The transceiver consists of a direct-conversion receiver (RX), a digital TX with on-chip QPSK modulation, and a quadrature local-oscillation (LO) generation network with a 20-GHz phase-locked loop (PLL) frequency synthesizer. A T/R switch is integrated to interface with an E-shaped patch antenna. The QPSK modulation is directly realized in the I/ Q digital power amplifier (DPA), which simplifies the TX complexity and reduces the power consumption. A 20-GHz sub-sampling PLL (SSPLL) and a quadrature phased-coupled injection-locked oscillator (QILO) are integrated on-chip to generate 60-GHz quadrature LO signals. The QILO utilizes in-phase coupling technique to improve the LO I/ Q matching and phase noise performance. The RX achieves 7.1-dB noise figure (NF) and 25- to 47-dB dynamic gain range. The LO phase noise measured at the TX output is -115.6 dBc/Hz at 10 MHz offset from 60 GHz carrier. The measured error vector magnitude (EVM) of the TX is -23.9 dB for 10-Gb/s QPSK signals at 7-dBm output power. The EVM of the over-the-air (OTA) modulation-demodulation system is -13.8 dB for 10-Gb/s QPSK signals. The transceiver achieves the 10-Gb/s data rate while consuming 340.4 mW. The energy efficiency is 34 pJ/bit. This work demonstrates the fully functional wireless link based on the proposed mm-wave transceiver, which highlights the possibility of energy-efficient solution for future high throughputs mm-wave wireless systems.

Optimization of frequency settling time of PLL using 3rd MASH Sigma Delta Modulator

To reduce settling time of PLL, an attempt to optimize the parameters has been proposed in this paper. The transient responses of various Phase Locked Loop (PLL) frequency synthesizer have been comparied with their active and passive poles effect. These results are presented on a type-II 3rd order PLL frequency synthesizer employing a 3rd order MASH sigma delta modulator. The simulation results show the improved performance of the fractional frequency synthesizer for the communication system. These results have been simulated using Advanced Design System(ADS) tool.

Design of integer‐ N PLL frequency synthesiser for E‐band frequency for high phase noise performance in 5G communication systems

A phase-locked loop (PLL) frequency synthesiser is designed for 5G E-band frequency. ADF4155-PLL chip with an external (loop filter, prescaler, VCO and an external reference oscillator) is simulated using the ADIsimPLL tool. With a third-order passive filter having 1 MHz loop bandwidth and 45° phase margin, simulation results show that the proposed synthesiser achieves a total phase noise (PN) of -81.50 and -115.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for (71-76 GHz) and -80.39 and -114.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for the highest (81-86 GHz) 5G frequency range even if -160 dBc/Hz VCO noise floor and -170dBc/Hz reference PN floor are integrated in the design. Also, the performance of the system in terms of RMS jitter and reference spurs are verified. The proposed synthesiser for 5G application presents very low reference spurs (-113, -112 dBc) at 50 MHz offset frequency and low RMS jitter (0.39, 0.40 ps) for 70 and 80 GHz frequency band, respectively.

A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS

A fully integrated K-band dual down-conversion receiver for phased array radar applications in 90 nm CMOS is presented. The receiver utilizes the dual down-conversion architecture to achieve superior performance. The integrated 1.15 GHz image-rejection filter (IRF) provides enough wideband (22 MHz) image rejection ratio at 140 MHz offset before the second down-conversion by utilizing the Q-enhancing and frequency staggering techniques to compensate the component loss. The low noise amplifier realizes the single-to-differential-ended conversion at the input with a transformer and achieves good common-mode rejection. The 70 MHz intermediate frequency baseband consists of two cascaded 3rd-order band-pass active RC filters (BPFs) and one automatic gain control (AGC) loop, with the integrator frequency compensation technique to lower down the requirements on the embedded Op-Amps. Two phase-locked loop (PLL) frequency synthesizers are integrated to provide the local oscillation (LO) signals for the down-conversions, where the matching of the charge-pump is improved by adding one extra current compensation branch. The measurements of the prototype show that the receiver converts the targeted mm-wave signal to 70 MHz intermediate frequency while achieving 8.3 dB noise figure (NF), 51-95 dB variable gain range and >45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth. The receiver draws 74 mA current (excluding 2 PLLs) from the 1.2 V power supplies and occupies a core area of 4.58 × 0.53mm 2 (excluding 2 PLLs).

Low power LC-voltage controlled oscillator with −140 dBc/Hz @ 1 MHz offset using on-chip inductor design in 0.13 µm RF-CMOS process for S-Band application

Purpose The paper aims to present the novel design approach for a low power LC-voltage-controlled oscillators (VCO) design with low phase noise that too targeted at the most sought band of Bluetooth applications. Owing to their crucial role in a wide variety of modern applications, VCO and phase-locked loop (PLL) frequency synthesizers have been the subject of extensive research in recent years. In fact, VCO is one of the key components being used in a modern PLL to provide local frequency signal since a few decades. The complicated synthesizer requirements imposed by cellular phone applications have been a key driver for PLL research. Design/methodology/approach This paper first opted to present the recent developments on implemented techniques of LC-VCO designs in popular RF bands. An LC-VCO with a differential (cross-coupled) MOS structure is then presented which has aimed to compensate the losses of an on-chip inductor implemented in UMC’s 130 nm RF-CMOS process. The LC-VCO is finally targeted to embed onto the synthesizer chip, to address the narrowband (S-Band) applications where Bluetooth has been the most sought one. The stacked inductor topology has been adopted to get the benefit of its on-chip compatibility and low noise. The active differential architecture, which basically is a cross-coupled NMOS structure, has been then envisaged for the gain which counters the losses completely. Three major areas of LC-VCO design are considered and worked upon for the optimum design parameters, which includes Bluetooth coverage range of 2.410 GHz to 2.490 GHz, better linearity and high sensitivity and finally the most sought phase noise performance for an LC-VCO. Findings The work provides the complete design aspect of a novel LC-VCO design for low phase noise narrowband applications such as Bluetooth. Using tuned MOS varactor, in 130 nm-RF CMOS process, a high gain sensitivity of 194 MHz/Volt was obtained. Thus, the entire frequency range of 2415-2500 MHz for Bluetooth applications, supporting multiple standards from 3G to 5G, was covered by voltage tuning of 0.7-1.0 V. To achieve the low power dissipation, low bias (1.2 V) cross-coupled differential structure was adopted, which completely paid for the losses occurred in the LC resonator. The power dissipation comes out to be 8.56 mW which is a remarkably small value for such a high gain and low noise VCO. For the VCO frequencies in the presented LO-plan, the tank inductor was allowed to have a moderate value of inductance (8 nH), while maintaining a very high Q factor. The LC-VCO of the proposed LO-generator achieved extremely low phase noise of −140 dBc/Hz @ 1 MHz, as compared to the contemporary designs. Research limitations/implications Though a professional tool for inductor and circuit design (ADS-by Keysight Technologies) has been chosen, actual inductor and circuit implementation on silicon may still lead to various parasitic evolutions; therefore, one must have that margin pre-considered while finalizing the design and testing it. Practical implications The proposed LC-VCO architecture presented in this work shows low phase noise and wide tuning range with high gain sensitivity in S-Band, low power dissipation and narrowband nature of wireless applications. Originality/value The on-chip stacked inductor has uniquely been designed with the provided dimensions and other parameters. Though active design is in a conventional manner, its sizing and bias current selection are unique. The pool of results obtained completely preserves the originally to the full extent.

High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks

One of the most promising solutions for the future fifth generation communication systems is to utilize millimeter wave (mm-W) radio frequencies. There is, however, little works about Phase Locked Loop (PLL) frequency synthesizer designed for mm-W band frequency for 5G applications. This article discusses integer PLL architecture for frequency synthesis; it targets the highest range of 5G mmW [81–86] GHz using ultra-wide channel spacing of 1 GHz. This work investigates the design of a third passive loop filter for frequency synthesizer using a Phase Frequency Detector and a current switch Charge Pump such as analog devices ADF4155. The critical performance for the Charge Pump depends on the leakage current produced by the technology of its transistors. This undesirable current can have a high impact on the loop stability. However, by optimizing PLL filter parameters, the synthesizer was able to tolerate up to 117 nA. With such a high leakage current, a high performance of the system was achieved. As a result, less than −71 dBc reference spur level at 50 MHz offset frequency was ensured and 3.23 µs settling time for a hopping frequency of 5 GHz was achieved.

A Frequency Synthesizer Based Microwave Permittivity Sensor Using CMRC Structure

In this paper, a high-sensitive microwave dielectric sensor targeted for material permittivity characterization is proposed. A reflective voltage controlled oscillator is devised by virtue of the compact microstrip resonant cell (CMRC) and embedded into a fractional- $N$ phase-locked loop frequency synthesizer. The CMRC structure, covered with material under test, changes its resonating characteristics and, hence, the initial oscillating frequency. Due to the presence of the frequency synthesizer, this frequency shift is finally translated into the controlling voltage variation. In this paper, the material permittivity is extracted by measuring the voltage deviation. Several different samples with known permittivity values are tested to verify the effectiveness of the design sensing platform.

A 50–66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs

Digital phase-locked loop (DPLL) frequency synthesizers have become popular for wireless applications in the sub-10-GHz range. However, mm-wave synthesizers still rely on analog PLLs, predominantly of the sub-harmonic, integerN-type. This paper describes the design and implementation of a 50-66-GHz phase-domain DPLL that uses a fundamental frequency capacitively degenerated digitally controlled oscillator (DCO) with 40-kHz frequency step. Following frequency division with a modulus of only 4, a two-step 8-bit time-todigital converter (TDC) digitizes the phase of the 12.5-16.5-GHz divider output with 450-fs resolution. Digital calibration based on the statistical element selection technique augmented by mean adaptation is used to mitigate TDC nonlinearity that results from random mismatches. Additional digital calibration techniques are introduced to mitigate DCO non-linearity and phase mismatches in the digital phase extraction sub-system, and to ensure robust operation of the inductor-less 4× frequency divider over process, voltage and temperature (PVT) variations. A 65-nm CMOS prototype of the DPLL occupies 0.45 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> excluding pads and consumes 46 mA from a 1-V supply. The PLL achieves best (worst) case rms jitter of 220 (302) fs, best (worst) phase noise of -83/-94.5/-122 (-79/-88/ -116) dBc/Hz at 0.1/1/10 MHz offset, and -52.2(-48.3) dBc fractional spur.

A 30-GHz Power-Efficient PLL Frequency Synthesizer for 60-GHz Applications

This paper presents the design and verification of a proposed 30-GHz power-efficient phase-locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a commercial 0.18- $\mu \text{m}$ SiGe BiCMOS process, the synthesizer employs coupled LC tank voltage-controlled oscillator, high power-added efficiency amplifier, reconfigurable divider realizing fractional division ratios for choice of multiple reference frequencies and low operation power, a programmable charge pump, an internal loop filter, and an integrated slave serial peripheral interface. The PLL synthesizer (PLLS) provides output frequency from 29.5 to 33.4 GHz with phase noise of −97 dBc/Hz at 1-MHz offset. The integrated phase noise over the frequency of 10 kHz–10 MHz is 2.05° rms at a frequency of 30.24 GHz. Operating with a single 1.8-V supply voltage, the PLLS consumes a low power of 63 mW and occupies an area of 2.8 mm $\times$ 1.86 mm.

An Overview of Frequency Synthesizer Development and Application Prospect with Memristor Progress

This paper presents the important application of frequency synthesizer technology in the electronic information system, and introduces the four basic frequency synthesis technology, direct type, phase-locked type, direct digital type and hybrid type, then focusing on the most widely used phase-locked loop frequency synthesizer (PLL) and direct digital frequency synthesizer (DDS). The development situation of its application in frequency synthesis technology is prospected in the new memristor.

A 6.6 mW 1.25–2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO

A wide tuning range low phase noise phase-locked loop (PLL) frequency synthesizer based on Class-C voltage-controlled oscillator (VCO) for IEEE 802.11ah is presented. Feedback loop technique is adopted to provide dynamic gate bias to the core transistors of the Class-C VCO, guaranteeing robust start-up against process, voltage and temperature (PVT) variations. Automatic frequency control (AFC) algorithm with tail bias switching scheme is proposed to guarantee start-up condition and maintain optimum oscillation amplitude across the whole tuning range, avoiding the deterioration of figure-of-merit (FoM). Implemented in 65-nm CMOS, the presented frequency synthesizer prototype achieves a tuning range of 57%, from 1.25GHz to 2.25GHz. Drawing 5.5mA current from a 1.2-V power supply, the prototype demonstrates −127.8 dBc/Hz phase noise at 1-MHz offset and −94.6 dBc/Hz in-band phase noise from a carrier of 1.536GHz. With the proposed dynamic gate bias technique and AFC-assisted tail bias switching scheme, the wide tuning range Class-C VCO exhibits a peak FoM of 187.5 dBc/Hz, with only 2.5dB variation across the whole tuning range.

A Study on Active Inductor based VCO to Implement PLL Frequency Synthesizer for Zigbee Standard

This research paper is based on various comparative analysis on precise and wide tuning Voltage Controlled Oscillators (VCO) with minimum phase noise and power consumption, using an active inductor tank circuit for Phase Locked Loop (PLL) based frequency synthesizer to support Zigbee wireless LAN standard, operating on 2.4 GHz ISM band (Industrial, Scientific, Medical), supporting 16 channels of 75MHz bandwidth+5MHz guard-band. The performance of the On-chip passive inductor based LC-VCO (inductive-capacitive) for studying the phase noise characteristics as well the tuning range for locking to the reference signal frequency for supporting Zigbee application has been done. Then it has been compared with the VCO implemented with active inductors based on gyrator technology, as the above technique has certain drawbacks in terms of frequency tuning range, limitation in terms of inductor size and Quality-factor. The analysis has been carried out on 180 nm and 90 nm CMOS technology and simulations carried out in Cadence design environment. In this paper various merits and demerits of the different methods adopted in designing the most critical PLL block, the VCO has been reviewed along with the challenges faced while designing this oscillator block for synthesizer application.

Compact Modeling of Phase-Locked Loop Frequency Synthesizer for Transient Phase Noise and Jitter Simulation

Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process.

A Linearized Model for the Design of Fractional-&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$N$&lt;/tex&gt;&lt;/formula&gt; Digital PLLs Based on Dual-Mode Ring Oscillator FDCs

A digital fractional- N phase-locked loop (PLL) frequency synthesizer based on a second-order ΔΣ frequency-to-digital converter (FDC) without conventional analog components was recently proposed and demonstrated experimentally to have performance in line with state-of-the-art analog PLLs. However, unlike analog PLLs or prior PLLs based on second-order ΔΣ FDCs, it is highly digital and does not require an analog charge pump or ADC, so it is well-suited to implementation in highly-scaled CMOS technology. This paper derives a linearized model of the new architecture and key equations which are necessary for the design of PLLs based on the architecture.

A 1 V 0.18 μm fully integrated integer-N frequency synthesizer for 2.4 GHz wireless sensor network applications

A 1 V low voltage, low power integer-N frequency synthesizer applied for 2.4 GHz wireless sensor network (WSN) applications is presented. The loop parameters of proposed charge pump phase lock loop frequency synthesizer is calculated and verified on the basis of continuous linear model. The proposed voltage controlled oscillator (VCO) consists of a PMOS cross-coupled transistor pair, a NMOS tail current source and a LC resonator. Common-mode 2nd harmonic filters are employed to improve loaded Q factor and suppress noise. LC resonator is optimized and switched capacitor array is used to lower AM---PM noise conversion. Fabricated in TSMC 0.18 μm CMOS process, the measured phase noise of VCO is ?113.4 dBc/Hz@1 MHz, and ?124.5 dBc/Hz@3.5 MHz while the frequency tuning range covers 4.56---5.32 GHz with 1 V voltage supply. The power dissipation is 2.3 mW and corresponding FOM is about ?185 dBc/Hz. With other blocks of dividers, phase frequency detector, charge pump and auto frequency calibration, the die area of the whole fabricated frequency synthesizer is 1.33 mm2 with pads. With 1 V supply voltage and 9.1 mW power consumption, the measured phase noise of the frequency synthesizer is ?121.9 dBc/Hz@1 MHz and ?134.4 dBc/Hz@3.5 MHz respectively, and the reference spur is ?44.5 dBc. The performance of the designed 1 V integer-N frequency synthesizer is suitable for IEEE 802.15.4/ZigBee based 2.4 GHz WSN applications.

A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication

A 40-GHz phase-locked loop (PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator (VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector (PFD) and the charge pump (CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is −97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 mW, including all the buffers.