Phase-II Upgrade Research Articles

The ATLAS IBL CO2 cooling system

The ATLAS Pixel detector has been equipped with an extra pixel layer in the space obtained by a smaller radius beam pipe. This new pixel layer called the Insertable B-Layer (IBL) was installed in 2014 and is operational in the current ATLAS data taking. The IBL detector is cooled with evaporative CO2 and is the first of its kind in ATLAS. The ATLAS IBL CO2 cooling system is designed for lower temperature operation (< −35̂C) than the previous developed CO2 cooling systems in High Energy Physics experiments. The cold temperatures are required to protect the pixel sensors for the expected high radiation dose received at an integrated luminosity of 550 fb1. This paper describes the design, development, construction and commissioning of the IBL CO2 cooling system. It describes the challenges overcome and the important lessons learned for the development of future systems which are now under design for the Phase-II upgrade detectors.

Decision feedback equalization for radiation hard data link at 5 Gbps

The increased particle collision rate following the upgrade of the Large Hadron Collider (LHC) to an increased luminosity requires an increased readout data speed, especially for the ATLAS pixel detector, located closest to the particle interaction point. For this reason, during the Phase-II upgrade of the ATLAS experiment the output data speed of the pixel front-end chips will be increased from 160 Mbps to 5 Gbps. The increased radiation levels will require a radiation hard data transmission link to be designed to carry this data from the pixel front-end to the off-detector system where it will undergo optical conversion. We propose a receiver utilizing the concept of Decision Feedback Equalization (DFE) to be used in this link, where the number of filter taps can be determined from simulations using S-parameter data from measurements of various customized cable prototypes under characterization as candidates to function as transmission medium between the on-chip data driver and the receiver of the link. A dedicated framework has been set up in Matlab to analyze the S-parameter characteristics for the various cable prototypes and investigate the possibilities for signal recovery and maintained signal integrity using DFE, as well as pre-emphasis and different encoding schemes. The simulation results indicate that DFE could be an excellent choice for expanding the system bandwidth to reach required data speeds with minimal signal distortion.

Characterisation of strip silicon detectors for the ATLAS Phase-II Upgrade with a micro-focused X-ray beam

The planned HL-LHC (High Luminosity LHC) in 2025 is being designed to maximise the physics potential through a sizable increase in the luminosity up to 6·1034 cm−2s−1. A consequence of this increased luminosity is the expected radiation damage at 3000 fb−1 after ten years of operation, requiring the tracking detectors to withstand fluences to over 1·1016 1 MeV neq/cm2. In order to cope with the consequent increased readout rates, a complete re-design of the current ATLAS Inner Detector (ID) is being developed as the Inner Tracker (ITk).Two proposed detectors for the ATLAS strip tracker region of the ITk were characterized at the Diamond Light Source with a 3 μm FWHM 15 keV micro focused X-ray beam. The devices under test were a 320 μm thick silicon stereo (Barrel) ATLAS12 strip mini sensor wire bonded to a 130 nm CMOS binary readout chip (ABC130) and a 320 μm thick full size radial (end-cap) strip sensor - utilizing bi-metal readout layers - wire bonded to 250 nm CMOS binary readout chips (ABCN-25).A resolution better than the inter strip pitch of the 74.5 μm strips was achieved for both detectors. The effect of the p-stop diffusion layers between strips was investigated in detail for the wire bond pad regions.Inter strip charge collection measurements indicate that the effective width of the strip on the silicon sensors is determined by p-stop regions between the strips rather than the strip pitch.

Alternative glues for the production of ATLAS silicon strip modules for the Phase-II upgrade of the ATLAS Inner Detector

The Phase-II upgrade of the ATLAS detector for the High Luminosity Large Hadron Collider (HL-LHC) includes the replacement of the current Inner Detector with an all-silicon tracker consisting of pixel and strip detectors. The current Phase-II detector layout requires the construction of 20,000 strip detector modules consisting of sensor, circuit boards and readout chips, which are connected mechanically using adhesives. The adhesive used initially between readout chips and circuit board is a silver epoxy glue as was used in the current ATLAS SemiConductor Tracker (SCT). However, this glue has several disadvantages, which motivated the search for an alternative. This paper presents a study of six ultra-violet (UV) cure glues and a glue pad for possible use in the assembly of silicon strip detector modules for the ATLAS upgrade. Trials were carried out to determine the ease of use, thermal conduction and shear strength. Samples were thermally cycled, radiation hardness and corrosion resistance were also determined. These investigations led to the exclusion of three UV cure glues as well as the glue pad. Three UV cure glues were found to be possible better alternatives than silver loaded glue. Results from electrical tests of first prototype modules constructed using these glues are presented.

Development of a Standardised Readout System for Active Pixel Sensors in HV/HR-CMOS Technologies for ATLAS Inner Detector Upgrades

The LHC Phase-II Upgrade results in new challenges for tracking detectors for example in terms of cost effectiveness, resolution and radiation hardness. Active Pixel Sensors in HV/HR-CMOS technologies show promising results coping with these challenges. In order to demonstrate the feasibility of hybrid modules with active CMOS sensors and readout chips for the future ATLAS Inner Tracker, ATLAS R&D activities have started. After introducing the basic concepts and the demonstrator program, the development of an ATLAS compatible readout system will be presented as well as tuning procedures and measurements with demonstrator modules to test the readout system.

Performance of the new Amplifier-Shaper-Discriminator chip for the ATLAS MDT chambers at the HL-LHC

The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 × 2.9 mm2 size. We present results of detailed measurements as well as a comparison with simulation results of the chip behavior at three different levels of detail.

Prototype Active Silicon Sensor in 150 nm HR-CMOS technology for ATLAS Inner Detector Upgrade

The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R{&}D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation and measurement results.

The ATLAS experience and its relevance to the data acquisition of the BM@N experiment at the NICA complex

The quest to understand the world around us has increased the size of high energy physics experiments and the processing rate of the data output from high energy experiments. The Large Hadron Collider is the largest experimental set-up known, with ATLAS detector as one of the detectors built to record proton-proton collision at about 10 PB/s (Petabit/s) around the LHC interaction point. With the Phase-II upgrade in 2022 this data output will increase by at least 10 times higher than those of today due to luminosity increase, this poses a serious challenge on processing and storage of the data. Also the BM@N fixed target experiment is expected to have event size of about 80,000 bytes/Event, leading to huge amount of data output to be processed in real time. Experimentalists handle these challenges by developing High-throughput electronic, with the capability of processing and reducing big data to scientific data in real time. One of these high-throughput electronics is the Super Readout Driver (sROD) and ARM-based processing unit (PU) developed for ATLAS TileCal detector by the University of the Witwatersrand. The sROD is designed to process data from Tile Calorimeter at 40 MHz. This work takes a look at the architecture of the data acquisition (DAQ) system of the BM@N detectors and the adaptation of the high-throughput systems to last stage of the BM@N DAQ system.

Real time tracker based upon local hit correlation circuit for silicon strip sensors

For the planned high luminosity upgrade of the Large Hadron Collider (LHC), a significant performance improvement of the detectors is required, including new tracker and trigger systems that makes use of charged track information early on. In this note we explore the principle of real time track reconstruction integrated in the readout electronics. A prototype was built using the silicon strip sensor for the ATLAS phase-II upgrade. The real time tracker is not the baseline for ATLAS but is nevertheless of interest, as the upgraded trigger design has not yet been finalized. For this, a new readout scheme in parallel with conventional readout, called the Fast Cluster Finder (FCF), was included in the latest prototype of the ATLAS strip detector readout chip (ABC130). The FCF is capable of finding hits within 6ns and transmitting the found hit information synchronously every 25ns. Using the FCF together with external correlation logic makes it possible to look for pairs of hits consistent with tracks from the interaction point above a transverse momentum threshold. A correlator logic finds correlations between two closely spaced parallel sensors, a “doublet”, and can generate information used as input to a lowest level trigger decision. Such a correlator logic was developed as part of a demonstrator and was successfully tested in an electron beam. The results of this test beam experiment proved the concept of the real time track vector processor with FCF.

Development of a high data-throughput ADC board for the PROMETEO portable test-bench for the upgraded front-end electronics of the ATLAS TileCal

The Large Hadron Collider (LHC) is preparing for a major Phase-II upgrade scheduled for 2022 [1]. The upgrade will require a complete redesign of both on- and off-detector electronics systems in the ATLAS Tile hadron Calorimeter (TileCal) [2]. The PROMETEO (A Portable ReadOut ModulE for Tilecal ElectrOnics) stand-alone test-bench system is currently in development and will be used for the certification and quality checks of the new front- end electronics. The Prometeo is designed to read in digitized samples from 12 channels simultaneously at the bunch crossing frequency while accessing quality of information in realtime. The main board used for the design is a Xilinx VC707 evaluation board with a dual QSFP+ FMC (FPGA Mezzanine Card) module for read-out and control of the front-end electronics. All other functions are provided by a HV board, LED board and a 16 channel ADC daughter board. The paper relates to the development and testing of the ADC board that will be used in the new Prometeo system.

Silicon strip tracking detector development and prototyping for the Phase-II upgrade of the ATLAS experiment

In about ten years from now, the Phase-II upgrade of the LHC will be carried out. Due to increased luminosity, a severe radiation dose and high particle rates will occur for the experiments. In consequence, several detector components will have to be upgraded. In the ATLAS experiment, the current inner detector will be replaced by an all-silicon tracking detector with the goal of at least delivering the present detector performance also in the harsh Phase-II LHC conditions. This report presents the current planning and results from first prototype measurements of the upgrade silicon strip tracking detector.

The pixel detector for the CMS phase-II upgrade

The high luminosity phase of the Large Hadron Collider (HL-LHC) requires a major pixel detector R&D effort to develop both readout chip and sensor that are capable to withstand unprecedented extremely high radiation. The target integrated luminosity of 3000 fb−1, that the HL-LHC is expected to deliver over about 10 years of operation, translates into a hadron fluence of 2×1016 1 MeV eq.n. / cm2, or equivalently 10 MGy of radiation dose in silicon, at about 3 cm from the interaction region where the first layer of the pixel detector could be located. The CMS collaboration has undertaken two baseline sensor R&D programs on thin n-on-p planar and 3D silicon sensor technologies. Together with the ATLAS collaboration it has also been established a common R&D effort for the development of the readout chip in the 65 nm CMOS technology. Status, progresses, and prospects of the CMS R&D effort are presented and discussed in this article.

The development of a general purpose ARM-based processing unit for the ATLAS TileCal sROD

After Phase-II upgrades in 2022, the data output from the LHC ATLAS Tile Calorimeter will increase significantly. ARM processors are common in mobile devices due to their low cost, low energy consumption and high performance. It is proposed that a cost-effective, high data throughput Processing Unit (PU) can be developed by using several consumer ARM processors in a cluster configuration to allow aggregated processing performance and data throughput while maintaining minimal software design difficulty for the end-user. This PU could be used for a variety of high-level functions on the high-throughput raw data such as spectral analysis and histograms to detect possible issues in the detector at a low level. High-throughput I/O interfaces are not typical in consumer ARM System on Chips but high data throughput capabilities are feasible via the novel use of PCI-Express as the I/O interface to the ARM processors. An overview of the PU is given and the results for performance and throughput testing of four different ARM Cortex System on Chips are presented.

A double-sided, shield-less stave prototype for the ATLAS Upgrade strip tracker for the High Luminosity LHC

A detailed description of the integration structures for the barrel region of the silicon strips tracker of the ATLAS Phase-II upgrade for the upgrade of the Large Hadron Collider, the so-called High Luminosity LHC (HL-LHC), is presented. This paper focuses on one of the latest demonstrator prototypes recently assembled, with numerous unique features. It consists of a shortened, shield-less, and double sided stave, with two candidate power distributions implemented. Thermal and electrical performances of the prototype are presented, as well as a description of the assembly procedures and tools.

R\&amp;D for a Dedicated Fast Timing Layer in the CMS Endcap Upgrade

The PhaseII Upgrades of CMS are being planned for the High Luminosity LHC (HL-LHC) era when the mean number of interactions per beam crossing ("in-time pileup") is expected to reach ~140-200. The potential backgrounds arising from mis-associated jets and photon showers, for example, during event reconstruction could be reduced if physics objects are tagged with an "event time". This tag is fully complementary to the "event vertex" which is already commonly used to reduce mis-reconstruction. Since the tracking vertex resolution is typically ~10^{-3} (50 micron/4.8cm) of the rms vertex distribution, whereas only ~10^{-1} (i.e. 20 vs.170 picoseconds (psec)) is demonstrated for timing, it is often assumed that only photon (i.e. EM calorimeter or shower-max) timing is of interest. We show that the optimal solution will likely be a single timing layer which measures both charged particle and photon time (a pre-shower layer).

Silicon strip detectors for ATLAS at the HL-LHC upgrade

The present ATLAS silicon strip tracker (SCT) and transition radiation tracker (TRT) are to be replaced with new silicon strip detectors as part of the inner tracker system (ITK) for the Phase-II upgrade of the Large Hadron Collider, HL-LHC. We have carried out intensive R&D programs based on n+-on-p microstrip detectors to fabricate improved radiation hard strip detectors that can survive the radiation levels corresponding to the integrated luminosity of up to 3000fb−1. We describe the main specifications for this year's sensor fabrication and the related R&D results, followed by a description of the candidate schema for module integration.

Silicon strip staves and petals for the ATLAS Upgrade tracker of the HL-LHC

This paper describes the baseline integration structures for the silicon strip sensors to be used in the ATLAS detector for the Phase-II upgrade of the Large Hadron Collider (LHC) machine, the so-called High Luminosity LHC (HL-LHC). Highly modular structures have been developed for the integration of the silicon strips sensors, readout electronics, cooling, and support structures, called ‘staves’ for the barrel region and ‘petals’ for the end-caps of the ATLAS strips tracker. This work describes the status of the current prototypes, the building procedure, designed for mass production even at a prototyping stage, and their electrical performances.

Silicon for High-Luminosity Tracking Detectors -Recent RD50 Results

In order to harvest the maximum physics potential of the CERN Large Hadron Collider (LHC), it is foreseen to significantly increase the LHC luminosity by upgrading the LHC towards the HL-LHC (High Luminosity LHC) [1] . Especially the final upgrade (Phase-II Upgrade) foreseen beyond 2020 will mean unprecedented radiation levels. Due to the radiation damage limitations of the silicon sensors presently used, the physics experiments will require new tracking detectors for HL-LHC operation. All-silicon central trackers are being studied in ATLAS, CMS and LHCb, with extremely radiation hard silicon sensors to be used for the innermost layers. Within the CERN RD50 Collaboration, a massive R&D programme is underway across experimental boundaries to develop silicon sensors with sufficient radiation tolerance. One research topic is to gain a deeper understanding of the connection between the macroscopic sensor properties such as radiation-induced increase of leakage current, doping concentration and trapping, and the microscopic properties at the defect level. A further area of activity is the development of advanced sensor types like 3D silicon detectors designed for the extreme radiation levels expected for the vertexing layers at the HL-LHC. Results from irradiation with a mix of different particle types as expected for the sLHC are also given. Recent observations of charge multiplication effects in heavily irradiated detectors at very high bias voltages point towards a new way to achieve sizeable signals after high fluences. Results for several detector technologies and silicon materials at radiation levels corresponding to HL-LHC fluences are presented in this article, demonstrating the availabilty of silicon detectors with sufficient radiation hardness for the different radii of tracking systems in the LHC detector upgrades.

Design of a 120 mm Bore 15 T Quadrupole for the LHC Upgrade Phase II

Future upgrades to machines like the Large Hadron Collider (LHC) at CERN will push accelerator magnets beyond 10 T forcing the replacement of NbTi superconductors with advanced superconductors such as Nb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn. In support of the LHC Phase-II upgrade, the US LHC Accelerator Research Program (LARP) is developing a large bore (120 mm) Nb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn Interaction Region (IR) quadrupole (HQ) capable of reaching 15 T at its conductor limit and gradients of 199 T/m at 4.4 K and 219 T/m at 1.9 K. The 1 m long, two-layer magnet, addresses coil alignment and accelerator quality features while exploring the magnet performance limits in terms of gradient, stress and structure. This paper summarizes and reports on the design, mechanical structure, coil windings, reaction and impregnation processes.