Phase-II Upgrade Research Articles

Testbeam analysis of biasing structures for irradiated hybrid pixel detectors

Following the Phase-II upgrade during Long Shutdown (LS3), the LHC aims to reach a peak instantaneous luminosity of 7.5× 1034 cm-2 s-1, which corresponds to an average of around 200 inelastic proton-proton collisions per beam-crossing (every 25 ns). To cope with these conditions, the ATLAS Inner Detector will be replaced by a new all-silicon system — the Inner Tracker (ITk). The ITk will be operational for more than ten years, during which time ATLAS is expected to record approximately 4000 fb-1 of data. The ITk's pixel sub-system is based on hybrid pixel modules with new silicon sensors and readout chips. These studies focus on testbeam campaigns undertaken to study the spatial resolution and efficiencies of hybrid pixel detector modules based on the first large-structure prototype front-end readout chip — the RD53A — using planar silicon sensors. These devices have been irradiated to replicate the effect of the high radiation environment present during operation in the ATLAS detector. Results for devices using sensors with different punch-through bias structures and using different readout modes are summarised. Those with sensors incorporating a punch-through bias structure are found to exhibit systematically lower efficiency than those without, as a result of local areas of relative inefficiency around the punch-through dots. Despite this, all devices measured are found to satisfy the requirement of 97% efficiency at V bias = 400 V after being irradiated to end-of-life fluence.

R&D of the cluster finding algorithm for CMS iRPC detector

The Compact Muon Solenoid (CMS) experiment will undergo phase-II upgrade to enhance the capacity of detectors in the High-Luminosity Large Hadron Collider era. An important extension involves the installation of the Improved Resistive Plate Chambers (iRPC) in the most forward part of the endcap muon system. The iRPC detector addresses the efficiency drop experienced by the current CMS trigger system for single muon triggers in the high pseudorapidity region. It features a double-ended read-out method, allowing the determination of the hit position along the strip using the time difference between signals from both ends. This feature provides precise spatial information for clustering. To utilize this feature and integrate iRPC cluster information into the CMS trigger system, this paper proposes a 2-Dimensional (2D) cluster-finding algorithm. This algorithm provides the 2D coordinates to CMS trigger system, with each cluster being timestamped to reduce time ambiguity in endcap trajectory reconstruction. The proposed algorithm was implemented in the firmware of the iRPC Back-End Electronics and evaluated using a dedicated cosmic muon setup. The results show a position precision of 2.55 cm and an algorithm efficiency better than 99%, demonstrating the algorithm's potential to improve muon detection and trigger efficiency in the CMS endcap region.

Evaluation of the prototype Peripheral Electronics Board for the High Granularity Timing Detector

To mitigate the effects of pileup resulting from increased luminosity during the ATLAS Phase-II upgrade, the High Granularity Timing Detector (HGTD) was proposed to accurately measure the timing of tracks. The Peripheral Electronics Board (PEB) serves as a critical component of the HGTD, functioning as an intermediary between the front-end modules and off-detector electronics. A prototype PEB, designated 1F, was designed and produced by the end of 2023. Extensive evaluations of PEB 1F were conducted in 2024, encompassing both single board tests and collaborative tests with the demonstrator. These assessments well determined the quality of PEB 1F.

Improved Resistive Plate Chambers for Phase-II upgrade of the CMS detector in LHC

In anticipation of the High Luminosity LHC, an extensive upgrade is underway for the CMS Muon system to ensure its optimal performance in muon triggering and reconstruction. The indispensable role of Resistive Plate Chambers (RPC) as dedicated muon detectors stems from their exceptional timing resolution. To meet the requirements of Phase-II of the LHC, the RPC system will be expanded up to a pseudorapidity of 2.4. The forward Muon system’s upcoming RE3/1 and RE4/1 stations will feature improved Resistive Plate Chambers (iRPC). Distinguished by a unique design and geometry, including a 2D strip readout, these iRPCs represent a significant advancement over the current RPC system. The enhancements include the use of thinner electrodes, a narrower 1.4 mm gas gap, and improved Front-End Board (FEB) allowing a 30 fC threshold. Two iRPC chambers were installed in station 3 of CMS during the year end technical stop (YETS) 2023/2024 and other 70 are being assembled at CERN and being prepared for installation next YETS 2024/2025. This paper provides a comprehensive summary of quality control (QC) and future plans for iRPC chambers in CMS detector.

The ATLAS RPC Phase-II upgrade for High Luminosity LHC era

Resistive Plate Chambers (RPC) detectors play a crucial role in triggering events containing muons in the central region of ATLAS. In view of the High Luminosity-LHC program, the existing RPC system, consisting of six independent cylindrical detector layers each providing a full space time localization of hits, is currently undergoing a significant upgrade. In the next few years, 306 triplets of new generation RPCs will be installed in the innermost region of the ATLAS Muon Barrel Spectrometer, increasing from 6 to 9 the number of tracking layers, doubling the trigger lever arm. This allows a substantial enhancement of the present trigger redundancy, increasing the coverage from 76% to approximately 96%. Fitting new chambers in the narrow space left in ATLAS inner barrel was a challenge, achieved by optimizing RPC materials and thickness, featuring a 1 mm gas gap (instead of 2 mm), and 1.4 mm resistive electrodes (instead of 1.8 mm) while reaching an high rate capability. To achieve such results, a 100 ps precise Time-to-Digital Converter (TDC) has been integrated in the front-end electronics ASIC. The expected time resolution of a single 1 mm RPC gas gap is approximately 300 ps, and the possibility of a stand-alone Time of Flight measurement will have a huge impact on ATLAS searches for massive long-lived particles. An overview and the present status of the ATLAS RPC Phase-II project will be presented.

Progress of the RPC development towards the production for ATLAS Phase-II upgrade

Progress of the RPC development towards the production for ATLAS Phase-II upgrade

Threshold bounce — occupancy-dependent modulation of the discriminating threshold in silicon detectors

The front-end electronics of silicon detectors are typically designed to ensure optimal noise performance for the expected input charge. A combination of preamplifiers and shaper circuits result in a nontrivial response of the front-end to injected charge, and the magnitude of the response may be sizeable in readout windows subsequent to that in which the charge was initially injected. The modulation of the discriminator threshold due to the superposition of the front-end response across multiple readout windows is coined “threshold bounce”. In this paper, we report a measurement of threshold bounce using silicon modules built for the Phase-II Upgrade of the ATLAS detector at the Large Hadron Collider. These modules utilize ATLAS Binary Chips for their hit readout. The measurement was performed using a micro-focused 15 keV photon beam at the Diamond Light Source synchrotron. The effect of the choice of photon flux and discriminator threshold on the magnitude of the threshold bounce is studied. A Monte Carlo simulation which accounts for the front-end behaviour of the silicon modules is developed, and its predicted hit efficiency is found to be in good agreement with the measured hit efficiency.

The LHCb VELO Upgrade II: design and development of the readout electronics

The LHCb collaboration proposes a Phase-II Upgrade of the detector, to be installed during the LHC Long Shutdown 4 (2032–2034). Operating in the HL-LHC environment poses significant challenges to the design of the upgraded detector, and in particular to its tracking system. The primary and secondary vertices reconstruction will become more difficult due to the increase, by a factor of 7.5, of the average number of interactions per bunch crossing. The performance of the VErtex LOcator (VELO), which is the tracking detector surrounding the interaction region, is essential to the success of this Phase-II Upgrade. Data rates are especially critical for the LHCb full software trigger, and with the expected higher particle flux, the VELO Upgrade-II detector will have to tolerate a dramatically increased data rate: assuming the same hybrid pixel design and detector geometry, the front-end electronics (ASICs) of the VELO Upgrade-II will have to cope with rates as high as 8 Ghits/s, with the hottest pixels reaching up to 500 khits/s. With this input rate, the data output from the VELO will exceed 30 Tbit/s, with potentially a further increase if more information is added to the read-out. This paper outlines the challenges being addressed and the solutions under investigation for reading out the VELO sub-detector.

Test result of the new ASD2 chips for Phase-II upgrade of the ATLAS MDT chambers at HL-LHC

For the Phase-II upgrade of the ATLAS Muon Spectrometer to High-Luminosity LHC, new front-end readout electronics for the Monitored Drift Tube chambers is required, as the old one no longer meets the demands. The first stage in the Monitored Drift Tubes readout chain is the Amplifier-Shaper-Discriminator chip. For the upgrade, the new ASD2 ASIC chip in IBM 130 nm CMOS technology has been developed. For the ATLAS experiment, 80000 ASD2 chips are produced, which have to be tested before integration in order to obtain the required 50000 well-performing chips in the end. Using a prototype tester board and pre-production ASD2 chips, the overall performance and the influence on programmable parameters is investigated. Based on these results, 1775 production chips are tested to define final optimized cut values for the automated production testing of all chips in the company.

A high granularity timing detector for the ATLAS Phase-II upgrade: Project overview and status

A High Granularity Timing Detector (HGTD) has been proposed for the ATLAS Phase-II upgrade to mitigate the pile-up effects at the High-Luminosity Large Hadron Collider (HL-LHC). The HGTD is based on silicon devices, Low Gain Avalanche Detectors (LGAD), aiming to provide 30–50 ps time resolution per track. Significant progress has been made in the development of various detector components, particularly the radiation-resistant sensor and readout chip. This proceeding concisely summarizes the project overview and current status of the HGTD project.

ATLAS ITk strip detector for the Phase-II Upgrade

The inner detector of the present ATLAS experiment has been designed and developed to function in the environment of the present Large Hadron Collider (LHC). At the ATLAS Phase-II Upgrade, the particle densities and radiation levels will exceed current levels by a factor of ten. The instantaneous luminosity is expected to reach unprecedented values, resulting in up to 200 proton-proton interactions in a typical bunch crossing. The new detectors must be faster and they need to be more highly segmented. The sensors used also need to be far more resistant to radiation, and they require much greater power delivery to the front-end systems. At the same time, they cannot introduce excess material which could undermine tracking performance. For those reasons, the inner tracker of the ATLAS detector was redesigned and will be rebuilt completely. The ATLAS Upgrade Inner Tracker (ITk) consists of several layers of silicon particle detectors. The innermost layers will be composed of silicon pixel sensors, and the outer layers will consist of silicon microstrip sensors. This contribution focuses on the strip region of the ITk. The central part of the strip tracker (barrel) will be composed of rectangular short (∼2.5 cm) and long (∼5 cm) strip sensors. The forward regions of the strip tracker (end-caps) consist of six disks per side, with trapezoidal shaped sensors of various lengths and strip pitches. After the completion of final design reviews in key areas, such as Sensors, Modules, Front-End electronics, and ASICs, a large scale prototyping program has been completed in all areas successfully. We present an overview of the Strip System and highlight the final design choices of sensors, module designs and ASICs. We will summarise results achieved during prototyping and the current status of pre-production and production on various detector components, with an emphasis on QA and QC procedures.

Radiation tolerance of the MUX64 for the High Granularity Timing Detector of ATLAS

The MUX64 ASIC is a 64-to-1 analog multiplexer to accommodate 64 inputs, with one addressed to output for ADC readout. It is developed for monitoring of the Low-Gain Avalanche Detectors (LGAD) detector modules in the High Granularity Timing Detector (HGTD) of the ATLAS Phase-II upgrade. The MUX64 chips will be used in the radiation field of high-luminosity pp collisions at LHC to an integrated luminosity of 4000 fb-1. This work presents the radiation tolerance study for the MUX64 being tested with 80 MeV protons and X-ray exposures for damages caused by Non-Ionizing Energy Loss (NIEL) and Total Ionizing Dose (TID), respectively. The irradiated samples demonstrated tolerance to the NIEL to a fluence of 3.21 × 1015 (Si, 1 MeV) neq/cm2, and the TID of 7.46 × 105 Gy (Si).

The readout panels for the BI-RPC project for ATLAS Phase-II upgrade

To take full advantage from the LHC upgrade to high luminosity in 2029, the ATLAS community has approved an intensive detector upgrade program that includes the construction of an additional trigger layer positioned close to the BI MDT chambers of the muon spectrometer. These chambers are RPC with thin gas gap, thin High Pressure Laminate electrodes coated with graphite on one side, and only use strips orthogonal to the beam-axis to reconstruct the eta and phi coordinates of the detector point where an ionizing particle passes. A detailed description of the construction and validation of these strip panels in China and Italy assembly sites, is presented here.

A full-function Global Common Module prototype for ATLAS Phase-II upgrade

The High Luminosity Large Hadron Collider (HL-LHC [1]), an upgrade of the LHC, is set to become operational in 2029, aiming to achieve instantaneous luminosities 5–7.5 times larger than the nominal value of the LHC. However, unlocking the full physics potential at this much higher luminosity level necessitates a tenfold increase in the data bandwidth processed by ATLAS. This poses significant challenges to the design of the Trigger and Data Acquisition systems. To address these challenges, a baseline architecture has been chosen for the ATLAS Phase-II upgrade, relying on a single-level hardware trigger known as the Level-0 Trigger. This trigger has a maximum rate of 1 MHz and a latency of 10 μs. Central to this upgrade is the inclusion of a new subsystem — the Global Trigger [2]. This component performs complex algorithms, akin to those currently used in Phase-I high-level trigger software (such as Topoclustering), on full-granularity calorimeter data. The Global Trigger is divided into three sublayers: the Multiplexer Processor (MUX) layer, the Global Event Processor (GEP) layer, and the Global to Central Trigger Processor [3] interface (gCTPi). A full-function Global Common Module (GCM) hardware prototype has been designed to fulfill the requirements of all three sublayers of the Global Trigger, featuring different firmware loads. This GCM prototype, based on the ATCA [4] front board form factor, incorporates two of the latest AMD (Xilinx) Versal Premium devices VP1802 [5]. These devices boast double the density of the Virtex UltraScale+ FPGA VU13P used in the previous design [6] and include an integrated SoC with a completely new architecture. To handle high-speed I/Os, this GCM prototype employs twenty 12-channel 25.7 Gb/s FireFly [7] optical engines. The estimated maximum power consumption of this GCM prototype is 400 W, which falls within the cooling capabilities of the ATLAS ATCA shelf. To ensure power integrity, signal integrity, and thermal performance, extensive PCB simulations and thermal simulations have been done to guide the layout design of the GCM prototype. This paper provides an in-depth overview of the design process for this full-function GCM prototype hardware, with a particular focus on technology choices and simulation results.

The optimization, design and performance of the FBCM23 ASIC for the upgraded CMS beam monitoring system

We present the development of the FBCM23 ASIC designed for the Phase-II upgrade of the Fast Beam Condition Monitoring (FBCM) system built at the CMS experiment which will replace the present luminometer based on the BCM1F ASIC [1]. The FBCM system should provide reliable luminosity measurement with 1 ns time resolution enabling the detection of beam-induced background. The FBCM23 ASIC comprises 6 channels of the fast front-end amplifier working in transimpedance configuration, booster amplifier, and leading edge discriminator. The complete processing chain provides an overall shaping function equivalent to the CR-RC3 filter. The paper will show the optimization of the design, overall architecture, and the detailed implementation in a CMOS 65 nm process as well as preliminary electrical performance.

Simulation of the signal propagation for thin-gap RPC in the ATLAS Phase-II upgrade

Thin-gap Resistive Plate Chambers (RPCs) with a 1 mm gap size are introduced in the ATLAS Phase-II upgrade. Smaller avalanche charge due to the reduced gap size raises concerns for signal integrity. This work focuses on the RPC signal propagation process in lossless conditions, and an analytical study is implemented for the ATLAS RPC. Detector modeling is presented, and the simulation of the RPC signal is discussed in detail. Simulated characteristic impedance and crosstalk have been compared with the measured value to validate this model. This method is applied to different RPC design geometries, including the newly proposed η−η readout scheme.

Hardware design and testing of the generic rear transition module for the global trigger subsystem of ATLAS Phase-II Upgrade

In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). The GRM, which was developed to mitigate the risks deriving from the complex design and power management of the GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25.8 Gb/s transceiver links, for readout and control. Additionally, the GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This paper presents the GRM hardware design and its testing.

Global trigger versatile module for ATLAS phase-II upgrade

The Global Trigger Versatile Module (GVM) has been developed within the framework of the ATLAS detector Phase-II upgrade. The GVM acts as an auxiliary hardware component that can be used for development, testing and operational purposes within and beyond the ATLAS Global Trigger in projects requiring high bandwidth and processing capabilities. The module is designed to host an advanced Xilinx Ultrascale+ VU13P FPGA and Finisar BOA optical modules, running at high data rates up to 25.8 Gb/s, as well as other hardware resources needed for the Global Trigger, located on a high-density PCB, optimized for high-speed data transmission. A testing program of the Global Trigger Versatile Module includes verification of the main hardware functionality of the module, performance evaluation of the high-speed optical modules and the FPGA, and Global Common Module development firmware tests.

The DAQ and clock distribution system of CMS MIP Timing Detector

The Compact Muon Solenoid (CMS) detector at the CERN Large Hadron Collider (LHC) is undergoing an extensive Phase-II upgrade program to cope with the challenging conditions of the High-Luminosity LHC (HL-LHC). A new timing detector is designed to measure minimum ionizing particles (MIPs) with a time resolution of 30–60 ps during the entire HL-LHC phase. A common data acquisition (DAQ) system will collect data from readout chips, reconstruct timing information, and send data to the event builder. The MIP timing detector (MTD) DAQ system is built around the state-of-the-art ATCA-form-factor Serenity board with two high-speed FPGAs. The precision clock is synchronized to the LHC collision rate of 40 MHz and is received at the subsystem and transmitted to the detector via high-speed data links. The detector system with a full-readout chain has been tested using prototypes of the DAQ, on-detector electronics, and sensors, showing that the system can successfully achieve timing resolution below 30 ps.

Status of the Level-0 ATLAS barrel muon trigger for High-Luminosity LHC

The Muon Spectrometer of the ATLAS detector will be substantially modified during the Phase-II Upgrade to cope with the higher particle rates and radiation levels of the High-Luminosity LHC. The entire trigger and readout electronics of the Resistive Plates Chambers will be replaced. The Resistive Plate Chambers’ hit data will be collected by on-detector Data Transmitter and Collector boards and will be sent off-detector to the Sector Logic boards, which will perform the Level-0 barrel muon trigger algorithm and the readout logic. This contribution presents the design of the Phase-II barrel muon trigger and data acquisition system and the development of the barrel Sector Logic board firmware and its challenges.