Phase Disposition Pulse Width Modulation Research Articles

Performance evaluation of seven level grid-tied PV inverter employs seven switches with the triple gain

Abstract In this paper, a novel switched capacitor converter has been proposed to generate 7-levels using seven semiconductor switches (7S7L) to get triple gain in the output voltage which is supplied by a single dc source. A PWM technique, phase disposition pulse width modulation (PD-PWM) has been designed to achieve a suitable switching operation for the 7S7L inverter. In addition, the capacitor voltage is balanced and the suggested inverter uses a charging inductor to decrease the capacitor inrush current, which is a shortcoming in the switched-capacitor multilevel inverters. Moreover, the 7S7L inverter is used to interface the solar panels with the utility grid using a synchronous reference frame-based controller. To check the efficiency, taking actual data, power loss calculation has been discussed for the 7S7L inverter. To illustrate the better performance of the proposed 7S7L inverter than the existing seven-level SC-MLI presented in the literature, a comparative study is also undertaken. To verify the feasibility and effectiveness of the proposed topology, a converter is simulated using Matlab/Simulink. To validate the simulation results, a real-time study is completed using the OPAL-RT 4510 real-time platform.

An Improved Phase-Disposition Pulse Width Modulation Method for Hybrid Modular Multilevel Converter

The hybrid modular multilevel converter (MMC) consisting of half-bridge submodules (HBSMs) and full-bridge submodules (FBSMs) is a promising solution for overhead lines high-voltage direct current systems (HVDC) due to the advantages of direct current short circuit fault ride-through (DC-FRT) capability. This paper proposes an improved phase-disposition pulse width modulation (PDPWM) method for the hybrid modular multilevel converter. The number of carriers can be reduced from 3N (N is the number of submodules in each arm) to 6. The theoretical harmonic analysis of the improved PDPWM method for hybrid MMC is performed by using double Fourier integral analysis. The influence of three carrier displacement angles between HBSMs and FBSMs in the upper and lower arms on harmonic characteristics is investigated. The output voltage harmonics minimization PDPWM scheme and circulating current harmonics cancellation PDPWM scheme can be achieved by selecting the optimum carrier displacement angles, respectively. The proposed method for hybrid MMC is verified by the simulation and experimental results.

Single-Phase 9L Switched-Capacitor Boost Multilevel Inverter (9L-SC-BMLI) Topology

The boosting factor has become a vital feature for a multilevel inverter to be connected with the low voltage PV system. In this paper, an inverter topology with 9 levels has been introduced. With the use of 10 switches and one switched capacitor unit, the proposed 9L-SC-BMLI has achieved nine different voltage states, and it has twice voltage gain. Without any auxiliary circuits, the voltage of the floating capacitor can maintain self-balanced. The additional feature of the proposed 9L-SC-BMLI has been the lower number of switches, voltage stress of reduced magnitude, and inherent polarity reversal of the output voltage without any H-bridge. The 9L-SC-BMLI has been controlled using the PD-PWM technique, i.e., phase-disposition pulse width modulation technique. In order to show the merits of the 9L-SC-BMLI, a detailed comparative study has been provided in the paper with several similar topologies. A number of simulation results have been provided in the paper with different working environments, and these results have been validated with the real-time results accomplished from a laboratory prototype.

A level enhanced voltage balancing method for modular multilevel converter without using sensors

SummaryThe intrinsic characteristics such as modular structure, filterless operation, and absence of DC‐link capacitor have made the modular multilevel converter (MMC) superior to the conventional multilevel converters. However, the submodule (SM) capacitor voltage balancing is crucial. This paper presents a voltage balance control method for MMC. The proposed method generates 2N + 1 levels (where N is the number of SMs per arm) which halves the step size of output voltage and improves the harmonic performance as compared to N + 1 level generation. It requires only one carrier per phase and no voltage and current measurements are needed for the implementation. Therefore, the proposed method makes the system cost‐effective and reduces the implementation issues related with carrier‐based methods substantially. It also alleviates the non‐uniform charge distribution problem with the phase disposition pulse width modulation (PDPWM) technique. Further, a detailed mathematical analysis is presented which enhances the understanding of balancing algorithm. In addition to this, the circulating current with 2N + 1 modulation is analyzed and a control technique is presented. The proposed voltage balancing method is simulated comprehensively in MATLAB/SIMULINK software and validated by the experimental results obtained from a laboratory prototype.

Carrier Redistribution Pulsewidth Modulation for Five-Level Stacked Multicell Converter

This article presents a modified carrier redistribution pulsewidth modulation (CRPWM) method for the five-level stacked multicell converter (SMC). The proposed CRPWM method is modified by exchanging the arrangement of the carriers of phase disposition pulsewidth modulation (PDPWM). With the ingenious carrier arrangement, the proposed PWM technique equalizes the utilization of phase leg voltage redundancies corresponding to the charging and the discharging state of each floating capacitor during one switching period of all the switches. The proposed modulation strategy has the same harmonic performance of line-to-line voltage with PDPWM, while the switch utilization is the same as phase-shifted pulsewidth modulation (PSPWM). Therefore, the voltage balancing of floating capacitors is achieved during a minimum switching period even with the influence of load current change and inappropriate carrier ratio is considered. The modified CRPWM is analyzed in theory and the voltage balancing ability and output harmonics performance are compared with PSPWM and traditional CRPWM. Simulation and experimental results on the laboratory prototype five-level SMC confirm the validity of the proposed CRPWM technique.

A Phase-Disposition PWM-Enabled Model Predictive Control for a Nine-Level Inner-Interleaved Hybrid Multilevel Converter

This article brings forward a phase-disposition pulsewidth modulation-enabled model predictive control (PDPWM-MPC) for a nine-level inner-interleaved hybrid multilevel converter (9L-IHMC). First, three layers of virtual space vector diagrams (VSVDs) are established based on the sign patterns of the original and virtual reference vectors in the abc-frame to achieve the phase-disposition pulsewidth modulation (PD-PWM) in a nonindependent three-phase way. Then, three adjacent virtual vectors in the third-layer VSVD, together with their optimized duty cycles, are applied to guarantee the optimal current tracking. Finally, through the use of the duty-cycle alternation approach, dc-link and floating capacitors voltages are balanced and circulating currents are mitigated as well. The proposed PDPWM-MPC can not only enable the decoupling of the low- and high-frequency stages in the 9L-IHMC but also reduce both output current ripples and computational burden. In addition, it can achieve a constant equivalent switching frequency and address the disproportion of power losses associated with the PD-PWM. Both simulations and experiments on a silicon carbide device-based prototype substantiate the effectiveness of the proposed control strategy.

A Carrier-Based Discontinuous PWM Scheme With Optimal PWM Sequences for a Five-Level Flying Capacitor Rectifier

Five-level flying capacitor (5L-FC) rectifier is advantageous in unidirectional power applications due to its less power devices, higher power density, better reliability, etc. To further improve the efficiency, discontinuous PWM (DPWM) methods are preferred. This article investigates a carrier-based implementation of DPWM for the 5L-FC rectifier to reduce the switching losses. Since there is always a pair of redundant switching modes that have opposite effects on the neutral point (NP) in each region of the space-vector diagram, the NP voltage regulation can be easily realized by selecting suitable clamping modes in each control period, even with unbalanced dc loads. The generated PWM sequences based on the phase disposition PWM are also optimally redistributed to realize minimal switching loss with FC voltage balancing in two consecutive carrier periods. In addition, the permissible range of unbalanced dc loads is theoretically deduced. Finally, simulations and experiments are conducted to verify the performance of the proposed carrier-based DPWM scheme.

A Nine-Level T-Type Converter for Grid-Connected Distributed Generation

This article presents a new high-efficiency nine-level T-type converter (9L-T2C) for grid-connected applications based on the three-level T-type converter (3L-T2C). The proposed 9L-T2C outperforms other common dc-link nine-level converters in terms of the required number of active switches and capacitors, flying capacitors (FCs) voltage ratings, and efficiency. Only ten power switches, eight gate drivers, and two FCs are required for each phase. Exploiting the available pole-redundant states, an FCs balancing algorithm is developed to stabilize the two FCs with one voltage sensor in steady-state and dynamic operation. Moreover, an effective balancing method is proposed for dc-link capacitors without the need for further redundant states and integrated into FCs balancing. The FCs and dc-link balance are integrated into the phase-disposition pulsewidth modulation (PD-PWM) method, eliminating the need for an additional controller. Considering the designed PD-PWM method, a mathematical analysis is performed to establish the relationship between the FCs size and the desired ripple. A comprehensive comparison with other converters is provided to demonstrate the merits and application areas of 9L-T2C. The operation of the proposed 9L-T2C with the capacitors’ balancing scheme is validated for stand-alone and grid-connected operation via simulation investigations and experimental setup.

A modified seven-level cross-connected PUC boost multilevel inverter with reduced cost factor and device count

Abstract The device count (dC) and cost factor (CF) with the boosting feature are the main challenges in the packed u-cell multilevel inverters as the number of levels are increased in the output voltage. In this paper, to mitigate these problems, a new topology of a 7-level modified packed u-cell boost multilevel inverter (PUC-BMLI) is designed to improve the cost factor and device count. Further, it can be used for a wide range of switching frequencies since only one capacitor is required and the voltage across the capacitor is balanced. To generate a 7-level stepped-up voltage across the load, the PUC-BMLI needs only eight power switches and one capacitor. The proposed topology can boost the input voltage by 1.5 times. To generate a 7-level stepped-up voltage across the output multicarrier phase-disposition pulse width modulation (PD-PWM) has been used. To prove the superior performance of the PUC-BMLI, a comparative analysis with existing single DC source boost MLI has been done. The device count (dC) and cost factor (CF) are the lowest compared to the recently proposed topology employing one dc source and producing 7-level across the output. The dC and CF are 10 and 22.33. All the switches are two-quadrant switches, thus reducing the cost of the overall circuit. THD is found to be 4.10% for output current. The feasibility of the 7-level modified topology is evaluated by Matlab/Simulink simulation and verified by an experimental study using the OPAL-RT 4510 real-time platform.

A Hybrid Model Predictive Control With Integrated Phase-Disposition and Phase-Shifted PWM for an Inner-Interleaved Hybrid Multilevel Converter

This article puts forward a hybrid model predictive control (H-MPC) for an inner-interleaved hybrid multilevel converter (IHMC). The sign patterns of the original and shifted reference vectors in the original and virtual space vector diagrams (VSVDs) are used, respectively, to realize the phase-disposition pulsewidth modulation (PWM) and determine the low-frequency switching states. Then, the three adjacent vectors are selected in the second-layer VSVD and the optimal current tracking is safeguarded by the duty cycle optimization of the three adjacent vectors. Finally, through applying the phase-shifted PWM to the two interleaved legs, a constant and doubled equivalent switching frequency can be achieved, which further paves the way for dc-link and floating capacitor voltages balancing and circulating current mitigation with the use of the straightforward duty cycle adjustments. The proposed H-MPC enables the decoupling of the low- and high-frequency stages in the IHMC and also reduces both output current ripples and computational burden while achieving a constant switching frequency simultaneously. Comprehensive simulation and experimental studies on an all silicon carbide prototype verify the effectiveness of the proposed control strategy.

Modeling and Analysis of Voltage Harmonic for Three-Level Neutral-Point-Clamped H-Bridge Inverter Considering Dead-Time

The advantages of three-level neutral-point-clamped (NPC) H-bridge inverters, such as simple topological structure, low device voltage stress, high equivalent switching frequency, and highly expansible capacity, have made them the preferred choice for inverters matching with medium voltage high-capacity multi-phase open-end winding vessel propulsion motors. To quantitatively evaluate the propulsion motors’ harmonics, electromagnetic vibration, and noise caused by pulse-width modulation (PWM) and device dead-time, it is necessary to research the mathematical modeling of pulse-width modulated output voltage harmonics in consideration of dead-time. In this paper, the principle of the phase-disposition PWM method of the 3L-NPC H-bridge inverters was firstly introduced. Then, the analytical models of output voltage harmonics with and without considering the effect of dead-time were established based on the double Fourier series approach and the harmonic distribution of the dead-time effect was accurately characterized. On the basis of the above, the experimental platform was established to verify the proposed analytical model. Simulation and experimental results are consistent with the theoretical analysis in low and high-frequency output voltage harmonics, which proves the correctness and the feasibility of the analytical modeling method researched by this paper. This will provide a theoretical basis for subsequent studies, which include the quantitative analysis and the suppression of output harmonics of the H-bridge inverter considering dead-time.

A SiC and Si Hybrid Five-Level Unidirectional Rectifier for Medium Voltage Applications

Following the continuous development of wide bandgap (WBG) devices and multilevel converter technology, medium voltage active front ends are becoming promising in future high-power-density and high-power applications. However, the cost issue is one of the major drawbacks, which stops the WBG devices from being widely applied in high-power areas. This article proposes a silicon carbide (SiC) and silicon (Si) hybrid five-level unidirectional rectifier. It requires only four SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MOSFET</small> s with relatively low blocking voltage and four Si diodes. Meanwhile, by adding snubber capacitors, all the Si devices are with low-speed switching, and the voltage stresses of fast SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MOSFET</small> s are minimized. In this article, operational analysis and carrier-based phase-disposition pulsewidth modulation scheme for this circuit are discussed in detail. The capacitor voltage balancing and unity power factor are both realized. Simulation and scaled-down experimental results are demonstrated to verify the proposed rectifier. Furthermore, the comparison of the hybrid five-level rectifiers is given to show the advantages of the proposed rectifier in terms of voltage stress, efficiency, and cost.

A Nine-Level Split-Capacitor Active-Neutral-Point-Clamped Inverter and Its Optimal Modulation Technique

This article proposes a novel hybrid nine-level inverter for high-efficiency applications based on the popular five-level active-neutral-point-clamped (5L-ANPC) topology. Compared with conventional ANPC-based topologies, this inverter reduces the required number of active and passive components while avoiding the use of higher voltage switches. Only nine active switches with eight gate drivers and two discrete diodes are used in each phase leg. Moreover, the proposed inverter not only reduces the number of flying capacitors (FCs) but also their rated voltages, which has a positive impact on the reliability, volume, and cost of the converter. Based on switching state redundancies, a voltage control strategy for FCs and neutral points is developed and incorporated into the phase-disposition pulsewidth modulation technique. The developed control method is able to balance the voltages of the FCs with only one sensor under active and reactive power operation. Based on the designed modulation strategy, a mathematical analysis is carried out to determine the capacitance of the FCs. A comprehensive comparison with other nine-level ANPC-based topologies is included to highlight the advantages of the proposed inverter. The performance of the proposed topology with its control strategy is validated through simulation studies and experimental implementation under different conditions.

Open-circuit fault resilient ability multi level inverter with reduced switch count for off grid applications

&lt;p&gt;In a multi-level inverter (MLI), the switching component number effect on volume and reliability is a major concern in on-grid and off-grid applications. The recent trend in MLI, reduced component number of power switches, and capacitors in multi-level inverter topologies have been driven for power conversion. The concept of fault tolerance is not considered in many such configurations; due to this the reliability of the MLI is very low. So now it is a major research concern, to develop a strong fault resilient ability power electronic converter. In this work, a novel configuration of a multilevel inverter with a lower switch count is proposed and analyzed with fault tolerance operation for improvement of reliability. Generally, the fault-tolerant operation is analyzed in only any one of the switches in MLI. But the proposed topology is concerned with multiple switch fault tolerance. Further, the phase disposition pulse width modulation (PDPWM) control scheme is utilized for the operation of the proposed inverter topology. The proposed inverter topology is simulated in MATLAB/Simulink environment under normal and faulty condition; the results are obtained and validated.&lt;/p&gt;

A hybrid reference pulse width modulation technique for binary source multilevel inverter

The article presents a seven-level reduced switch asymmetrical multilevel inverter with two different methods of pulse width modulation (PWM) techniques. Phase disposition (PD) PWM and hybrid variable-frequency phase disposition PWM (HVFPD-PWM) are the two different PWM methods for making the quality of output voltage waveform. In the first method, the unipolar sine reference with triangular carriers is used. In the second method, the hybrid unipolar reference (sinusoidal with trapezoidal) is proposed with variable frequency carriers to generate the switching pulses for asymmetric multilevel inverter (MLI). The main objective of this proposed method is to reduce the total harmonic distortion in the output voltage waveforms. A comprehensive comparison of the proposed HVFPD-PWM and the conventional PD-PWM with asymmetrical seven-level inverter is presented to show the enriched performances of the proposed method. The performance and viability of the suggested PWM are evaluated through simulation and experimental results using an asymmetrical seven-level inverter. The total harmonic distortion for the proposed PWM method (16.95%) is significantly reduced as compared with the conventional PWM method (18.01%) at the modulation index of one.

Low-Voltage Stress Seven-Level Inverter Based on Symmetrical Capacitors

A step-up single-phase seven-level inverter is proposed in this article. The proposed multilevel inverter (MLI) uses one voltage source and two symmetrical capacitors. Two capacitors are provided with self-voltage balancing ability, eliminating the requirement for sensors or additional control loop. The proposed topology generates bipolar levels inherently without the use of inverting H-bridge, so that the total standing voltage of switches is greatly reduced. The blocking voltages of all the switches are limited to the input voltage, and thus the proposed topology has low-voltage stress. Furthermore, the proposed structure has the advantages of voltage-boosting capability and high efficiency. The maximum output voltage is 1.5 times the input voltage. The prominent merits make it suitable for distributed generation applications. In this article, the circuit configuration of the proposed topology, operation principle, and the phase disposition pulsewidth modulation (PD PWM) strategy are presented. Furthermore, the mathematical calculations of power loss and parameter comparisons are performed to demonstrate the superiority. Finally, the experimental results are presented to verify the feasibility of the proposed topology.

A reconfigurable integrated level shifted carrier based PWM method for modular multilevel converters

This article presents a reconfigurable integrated level shifted carrier‐based pulse width modulation (ILSC‐PWM) method for modular multilevel converters (MMCs). The principles of basic level shifted carrier‐based PWM (LSC‐PWM) methods such as phase disposition PWM (PD‐PWM), phase opposition disposition PWM (POD‐PWM) and alternate phase opposition disposition PWM (APOD‐PWM) methods are combined to develop the concept of reconfigurable ILSC‐PWM method. The main objectives of the proposed reconfigurable ILSC‐PWM method is to develop the pulse width modulated output voltage with both half‐wave and quarter‐wave symmetries and to reduce the total harmonic distortion (THD). A simplified mathematical approach is developed to formulate reconfigurable single ILSC wave for MMC with N number of submodules (SMs) per arm. The functionality and performance of the reconfigurable ILSC‐PWM method are carried out on three‐phase five‐level MMC in MATLAB/Simulink. A hardware prototype of single‐phase five‐level MMC is designed for experimental validation. The proposed ILSC‐PWM method is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field programmable gate array (FPGA). Computer Simulations and laboratory experimental results are presented. © 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

A Compensation Component Injection Method Based on a Hybrid Modulation for Minimizing the Neutral-Point Voltage Oscillations in a Five-Level Flying Capacitor Rectifier

Neutral-point (NP) voltage oscillating is an inherent problem for multilevel converters with split dc-link capacitors. In this article, a compensation component injection method based on a hybrid modulation for minimizing the NP voltage oscillations in a five-level flying capacitor rectifier is proposed. In specific, the equivalent modulation waves are first obtained by adopting an existing simplified space-vector modulation method. And a hybrid modulation which gives both the same optimal harmonic performance as phase-disposition pulse width modulation (PWM) and the same superiority of flying capacitor voltage regulation as phase-shifted PWM is adopted. Meanwhile, the solved optimal compensation component in each subsector is injected to make the average NP current equal to zero for minimizing the NP voltage oscillations. Simulations and experiments were conducted to verify the performance of the proposed compensation method based on the hybrid modulation.

Evaluation of a grid‐connected reduced‐component boost multilevel inverter (BMLI) topology

AbstractIn this paper, a reduced‐component switched‐capacitor boost multilevel inverter (SC‐BMLI) topology is proposed for off‐grid and on‐grid applications. Recently, switched‐capacitor‐based multilevel inverter (MLI) topologies have been employed to avoid the need for multiple isolated direct current (DC) sources when compared with traditional cascaded MLIs. To generate a nine‐level stepped‐up voltage across the load, the SC‐BMLI needs only eight power switches and two capacitors. To get the appropriate nine‐level switching pattern, phase disposition pulse width modulation (PD‐PWM) has been used. An extended 13‐level boost multilevel inverter (BMLI) is also discussed in this paper. The proposed topology is connected to the grid to control the grid current using synchronous reference frame‐based proportional–integral controller. A small‐signal modeling and analysis has been discussed in detail for the phase‐locked‐loop (PLL). Moreover, to prove the superior performance of the SC‐BMLI, comparative analysis with an existing single DC source MLI has also been performed. The feasibility of the 9‐level and 13‐level proposed topologies, with and without the grid‐connection, is evaluated by Matlab/Simulink simulation and verified by an experimental study using the OPAL‐RT 4510 real‐time platform. Further, prototype model of nine‐level BMLI has been developed in the laboratory using DSpace 1103 controller and results are compared with simulation.

Sensorless voltage balancing method for modular multilevel converter

AbstractModular multilevel converters (MMCs) have become prominent for high and medium power applications. The phase‐disposition pulse width modulation (PDPWM) technique is a carrier‐based method that generates good quality output. However, it has the inherent problem of uneven power distribution. Conventionally, this is solved by expensive voltage and current measurements. In this paper, a capacitor voltage balancing method is presented for MMC, which eliminates the need for voltage and current sensors. It also ensures uniform power distribution among the submodules (SMs). In addition, it needs only one carrier per phase, and one PWM reference, for either upper arm or lower arm to produce N + 1 level with N SMs per arm. The capacitor voltage balancing method is analyzed mathematically and verified for the MMC with two‐level half‐bridge SMs. The same method is also extended to the MMC with three‐level flying capacitor SMs. MATLAB/SIMULINK simulations and experimental results on a laboratory prototype are presented to verify the theoretical concepts.