Phase Change Memory Research Articles

Impact of process-induced variability on multi-bit phase change memory devices

Phase change memory (PCM) shows great potential for multi-bit data storage for the next-generation non-volatile, high-speed, high-density memories. However, the process-induced variability poses a serious threat to the performance of multi-bit switching in nano-scale PCM devices. In this study, the impact of structural and interfacial parameters are studied systematically on the multi-level RESET programming of mushroom-type Ge2Sb2Te5 (GST) PCM devices by using TCAD simulations. Here, the impact of unintentionally varying structural and interfacial input parameters is investigated for the optimized multi-bit PCM device of 60 nm heater diameter (HD) using the Plackett-Burman design of experiment. The quantitative analysis of input parameters shows that HD, GST thickness, and interfacial thermal resistance between GST and heater are the most sensitive parameters for the output parameter, RESET resistance (RRESET), while considering all the resistance levels from 1 to 7. Similarly, HD, heater height, and GST diameter are found to be the most governing parameters for RESET power (PRESET).

Impact of process-induced ellipticity on the RESET process of cylindrical phase change memory devices

Phase change memory (PCM) is one of the promising candidates for the next-generation high-speed non-volatile memory which exhibits excellent scalability. The cylindrical-type PCM devices entering the nano-scale regime should show their tolerance to the variation in the manufacturing process. However, it is highly challenging to fabricate cylindrical-type nano-scale devices ideally with circular cross-sections. In general, the degree of variation in circular cross-section is dictated by a geometrical parameter called aspect ratio (AR). In this study, the impact of variation in AR of heater (ARheater) and active material, Ge2Sb2Te5 (ARGST) on the RESET programming of the mushroom-type cylindrical PCM device is systematically investigated by using 3D TCAD simulations. The simulation results reveal that the RESET current (IRESET) of the reference device (100 nm heater diameter) consisting of elliptical cross-sections increases significantly to ∼67% when ARheater = 2 and 1 ≤ ARGST ≤ 2, whereas for the scaled-down devices of 20 nm and 10 nm heater diameter with elliptical cross-sections, the IRESET increases to ∼35% and ∼38% when ARheater = 2 and ARGST = 1, and further IRESET increases to ∼54% and ∼63% when ARheater = 2 and ARGST = 2 leading to high-power RESET programming. In the case of the reference device, the ARGST did not play any significant role on IRESET. However, in the scaled-down devices, both ARheater and ARGST significantly affect the IRESET. Furthermore, the device employing a vertically-oriented elliptical heater and horizontally-oriented elliptical GST (where ARheater = 2 and ARGST = 0.5) shows the peculiar re-amorphization among all the cases considered in this study. Hence, the miniaturized cylindrical PCM devices comprising elliptical cross-sections due to process-induced variability require an accurate understanding of the programming characteristics for reliable modeling and simulations.

Ultrafast phase change speed and high thermal stability of antimony and zinc co-sputtering thin film for phase change random access memory application

In this work, we fabricate the Sb54Zn46 thin film by pure antimony and zinc targets co-sputtering and analyze its phase change properties. The ten-years data retention of Sb54Zn46 thin film, being a good reflection of thermal stability, is improved to 119 °C from 24 °C of pristine antimony thin film, which is much higher than that of the traditional phase change material Ge2Sb2Te5 (85 °C). The increased thermal stability of Sb54Zn46 thin film mainly derives from the formation of the strong Sb-Zn bond stretching mode during crystallization. In addition, the phase change speed of Sb54Zn46 thin film measured in device test increases to 10 ns, which is also much faster than that of the traditional phase change material Ge2Sb2Te5 (100 ns). These results illustrate that the fast phase change speed of Sb54Zn46 thin film is mainly ascribed to the Sb-rich atomic environment and the growth-dominant crystallization mechanism. Our work substantiates the co-sputtering Sb54Zn46 thin film can ensure fast phase change speed while effectively increasing its thermal stability.

Electron localization in recrystallized models of the Ge2Sb2Te5 phase-change memory material

Understanding the relation between the structural disorder in the atomic geometry of the recrystallized state of phase-change memory materials and the localized states in the electronic structure is necessary not only for technological advances, but also essential to achieve a fundamental understanding of these materials. In this computational study, hybrid density-functional theory simulations are employed to ascertain the impact of antisite defects on the spatial localization of the electronic states in the bottom of the conduction band in recrystallized models of the prototypical phase-change material ${\mathrm{Ge}}_{2}{\mathrm{Sb}}_{2}{\mathrm{Te}}_{5}$. $\mathrm{Te}\text{\ensuremath{-}}\mathrm{Te}$ homopolar bonds are the local defective atomic environments mainly responsible for the electron localization of the conduction-band-edge states in the simulated structures, while $\mathrm{Sb}\text{\ensuremath{-}}\mathrm{Te}$ chains can also induce spatial localization. Unoccupied defect-related electronic states can emerge in the band gap during a crystallization event, while $\mathrm{Sb}\text{\ensuremath{-}}\mathrm{Sb}$ homopolar bonds have been identified in the defect environment of a deep localized state.

Atomic Layer Deposition of Sb2 Te3 /GeTe Superlattice Film and Its Melt-Quenching-Free Phase-Transition Mechanism for Phase-Change Memory.

Atomic layer deposition (ALD) of Sb2 Te3 /GeTe superlattice (SL) film on planar and vertical sidewall areas containing TiN metal and SiO2 insulator is demonstrated. The peculiar chemical affinity of the ALD precursor to the substrate surface and the 2D nature of the Sb2 Te3 enable the growth of an in situ crystallized SL film with a preferred orientation. The SL film shows a reduced reset current of ≈1/7 of the randomly oriented Ge2 Sb2 Te5 alloy. The reset switching is induced by the transition from the SL to the (111)-oriented face-centered-cubic (FCC) Ge2 Sb2 Te5 alloy and subsequent melt-quenching-free amorphization. The in-plane compressive stress, induced by the SL-to-FCC structural transition, enhances the electromigration of Ge along the [111] direction of FCC structure, which enables such a significant improvement. Set operation switches the amorphous to the (111)-oriented FCC structure.

Exploration of Scandium Doping in SbTe for Phase Change Memory Application

In this work, we fabricate and electrically demonstrate a 65-nm technology-compatible Phase change memory (PCM) pillar device using Sc-doped SbTe (ST) instead of GeSbTe (GST), for the first time fabricated on a 300-mm wafer in the 1T1R configuration. ST was chosen over GST to achieve a higher speed and endurance due to its faster crystallization speed and reduced volume variation during switching. Detailed knobs on how to improve stack in terms of CD, thickness (of electrode and chalcogenide material), and Sc doping are presented. The optimized stack shows ac switching from 300 ns to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~\mu \text{s}$ </tex-math></inline-formula> for SET and RESET with current in the order of milliamperes and programming voltage less than 2.5 V. The endurance shows marginal memory window degradation up to 1E8 cycles and more than 1-h retention at 85° is achieved for the optimized stack of C:Si/50-nm ST:Sc 6%. The fabricated devices show the potential to extend the PCM technology toward high-speed storage class memory (SCM) applications.

ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator

Always-on TinyML perception tasks in Internet of Things applications require very high energy efficiency. Analog compute-in-memory (CiM) using nonvolatile memory (NVM) promises high energy efficiency and self-contained on-chip model storage. However, analog CiM introduces new practical challenges, including conductance drift, read/write noise, fixed analog-to-digital (ADC) converter gain, etc. These must be addressed to achieve models that can be deployed on analog CiM with acceptable accuracy loss. This article describes AnalogNets: TinyML models for the popular always-on tasks of keyword spotting (KWS) and visual wake word (VWW). The model architectures are specifically designed for analog CiM, and we detail a comprehensive training methodology, to retain accuracy in the face of analog nonidealities, and low-precision data converters at inference time. We also describe AON-CiM, a programmable, minimal-area phase-change memory (PCM) analog CiM accelerator, with a layer-serial approach to remove the cost of complex interconnects associated with a fully pipelined design. We evaluate the AnalogNets on a calibrated simulator, as well as real hardware, and find that accuracy degradation is limited to 0.8%/1.2% after 24 h of PCM drift (8 bits) for KWS/VWW. AnalogNets running on the 14-nm AON-CiM accelerator demonstrate 8.55/26.55/56.67 and 4.34/12.64/25.2 TOPS/W for KWS and VWWs with 8-/6-/4-bit activations, respectively.

Design space exploration for balanced MLC-PCM programming

Multi-Level Cell Phase Change Memory (MLC PCM) is a non-volatile memory technology that promises high-density data storage. However, MLC PCM suffers from long write latency because changing the state of each memory cell takes a long time and the number of cells that can be written concurrently is limited due to the relatively large size and power consumption of the write drivers. MLC PCM typically divides the write data into multiple cell groups to program cells in batches. The group mapping has a significant impact on the overall latency of write requests. Prior work proposed a group mapping technique for single-level cell (SLC) PCM based on the data pattern of a set of applications. In this work, a larger design space of group mapping is explored for MLC PCM. The specific group mapping for each benchmark is dynamically customized. Our technique leads to a 13.14% reduction in write latency compared to the state-of-the-art method (Du et al., 2013) and shows good temporal consistence in different benchmarks.

Monolithic TCAD simulation of phase-change memory (PCM/PRAM) + Ovonic Threshold Switch (OTS) selector device

Owing to the increasing interest in the commercialization of phase-change memory (PCM) devices, a number of TCAD models have been developed for their simulation. These models formulate the melting, amorphization and crystallization of phase-change materials as well as their extreme conductivity dependence on both electric field and temperature into a set of self-consistently-solved thermoelectric and phase-field partial-differential equations. However, demonstrations of the ability of such models to match actual experimental results are rare. In addition, such PCM devices also require a so-called selector device – such as an Ovonic Threshold Switching (OTS) device – in series for proper memory operation. However, monolithic simulation of both the PCM and OTS selector device in a single simulation is largely absent from the literature, despite its potential value for material- and design-space explorations. It is the goal of this work to first characterize a PCM device in isolation against experimental data, then to demonstrate the qualitative behavior of a simulated OTS device in isolation and finally to perform a single monolithic simulation of the PCM + OTS device within the confines of a commercially available TCAD solver: GTS Framework.

Ferroelectric Devices for Neuromorphic Computing

Neuromorphic computing inspired by the neural network systems of the human brain enables energy efficient computing for big-data processing. A neural network is formed by thousands or even millions of neurons which are connected by even a higher number of synapses. Neurons communicate with each other through the connected synapses. The main responsibility of synapses is to transfer information from the pre-synaptic to the postsynaptic neurons. Synapses can memorize and process the information simultaneously. The plasticity of a synapse to strengthen or weaken their activity over time make it capable of learning and computing. Thus, artificial synapses which can emulate functionalities and the plasticity of bio-synapses form the backbones of neuromorphic computing.Alternative artificial synapses have been successfully demonstrated. The classical two-terminal memristor devices, like resistive random access memory (ReRAM), phase change memory (PCM) and ferroelectric tunnel junctions (FTJs) with one terminal connected to the pre-synaptic neuron and another connected with the post-synaptic neuron, own advantages of simple structure, easy processing with high density, and capability of integration with CMOS. However, signal processing and learning cannot be performed simultaneously in 2-terminal devices, thus limiting their synaptic functionalities. Ferroelectric field effect transistors (FeFET) which uses ferroelectric as the gate oxide are the most interesting three-terminal artificial synapse devices, in which the gate or the source is connected to the pre-synaptic neuron while the drain is used for the terminal of the post-synaptic neuron , thus can perform signal transmission and learning simultaneously. However, traps at the channel interface can degrade the device performance causing low endurance. Focuses of those abovementioned devices have been mainly put on the homosynaptic plasticity, which is input specific, meaning that the plasticity occurs only at the synapse with a pre-synaptic activation . The homosynaptic plasticity has a drawback of positive feedback loop: when a synapse is potentiated, the probability of the synapse to be further potentiated is increased. Similarly, when a synapse is depressed the probability of the synapse of being further depressed is higher. Therefore, synaptic weights tend to be either strengthened to the maximum value or weakened to zero, causing the system to be unstable. In contrast, heterosynaptic plasticity can be induced at any synapse at the same time after episodes of strong postsynaptic activity, avoiding the positive feedback problem and stabilize the activity of the post-synaptic neuron. To address the above challenges we proposed a very simple 4-terminal synapse structure based on gated Schottky diodes on silicon (FEMOD) with a ferroelectric layer. The conductance of the Schottky diode is modulated by the polarization of the ferroelectric layer. With this simple synapse structure we can achieve multiple hetero-synaptic functions, including excitatory/ inhibitory post-synaptic current (EPSC/IPSC), paired-pulse facilitation/depression (PPF/PPD), long-term potentiation/depression (LTP/LTD), as well as biological neuron-like spike-timing-dependent plasticity (STDP) characteristics. The modulatory synapse can modify the weight of another synapse with a very low voltage. Furthermore, logic gates, like AND and NAND which are highly desired for in-memory computing can be realized with such simple structure. Figure 1

Understanding Interface-Controlled Resistance Drift in Superlattice Phase Change Memory

Resistance drift in phase change memory (PCM) reduces the accuracy of analog computing applications such as neural network inference. Recently, PCMs based on superlattice (SL) phase change layers have shown low resistance drift, however the origin of this low drift remains unexplored. Here, we uncover that resistance drift in SL-PCM based on alternating layers of Sb2Te3 and Ge2Sb2Te5 (GST) is controlled by the number of SL interfaces as well as the degree of SL intermixing. Temperature-dependent measurements reveal smaller and more stable activation energy upon annealing (thus suppressed structural relaxation) in our SL-PCM vs. control GST devices, accounting for the low resistance drift. By controlling SL interfaces, we achieve low resistance drift coefficient <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${v} &lt; 0.01$ </tex-math></inline-formula> in these SL-PCMs, maintained after extensive cycling and at various read voltages and intervals - showing robustness required for analog computing with PCM.

Read Optimization Enables Ultralow Resistance Drift for Phase Change Memory

Phase change memory (PCM) has been proven to have unique advantages in embedded applications, mass storage, and in-memory computing areas. To further improve the reliability of data reading for PCM, numerous studies have shown that the spontaneous structural relaxation of the amorphous phase material causes resistance drift and finally affects the reliability. By studying the effect of different read voltages on the resistance stability of PCM cells with various electrode sizes, a read optimization method on low drift property has been presented in this article. The average drift coefficient decreased by one order of magnitude to 0.0034 and, thus, promising higher data reliability of data reading.

Ultra-Stable, Endurable, and Flexible Sb2TexSe3–x Phase Change Devices for Memory Application and Wearable Electronics

Flexible memory and wearable electronics represent an emerging technology, thanks to their reliability, compatibility, and superior performance. Here, an Sb2TexSe3-x (STSe) phase change material was grown on flexible mica, which not only exhibited superior nature in thermal stability for phase change memory application but also revealed novel function performance in wearable electronics, thanks to its excellent mechanical reliability and endurance. The thermal stability of Sb2Te3 was improved obviously with the crystallization temperature elevated 60 K after Se doping, for the enhanced charge localization and stronger bonding energy, which was validated by the Vienna ab initio simulation package calculations. Based on the ultra-stability of STSe, the STSe-based phase change memory shows 65 000 reversible phase change ability. Moreover, the assembled flexible device can show real-time monitoring and recoverability response in sensing human activities in different parts of the body, which proves its effective reusability and potential as wearable electronics. Most importantly, the STSe device presents remarkable working reliability, reflected by excellent endurance over 100 s and long retention over 100 h. These results paved a novel way to utilize STSe phase change materials for flexible memory and wearable electronics with extreme thermal and mechanical stability and brilliant performance.

In situ characterization of vacancy ordering in Ge-Sb-Te phase-change memory alloys

Tailoring the degree of structural disorder in Ge-Sb-Te alloys is important for the development of non-volatile phase-change memory and neuro-inspired computing. Upon crystallization from the amorphous phase, these alloys form a cubic rocksalt-like structure with a high content of intrinsic vacancies. Further thermal annealing results in a gradual structural transition towards a layered structure and an insulator-to-metal transition. In this work, we elucidate the atomic-level details of the structural transition in crystalline GeSb2Te4 by in situ high-resolution transmission electron microscopy experiments and ab initio density functional theory calculations, providing a comprehensive real-time and real-space view of the vacancy ordering process. We also discuss the impact of vacancy ordering on altering the electronic and optical properties of GeSb2Te4, which is relevant to multilevel storage applications. The phase evolution paths in Ge-Sb-Te alloys and Sb2Te3 are illustrated using a summary diagram, which serves as a guide for designing phase-change memory devices.

Ge1−xSx chalcogenide alloys for OTS applications using magnetron sputtering

3D cross (X)–point memory arrays have attracted attention for future memory architecture due to their cost efficiency and high density. Chalcogenide–based materials are suitable candidates for 3D X–point memory because they can be stacked to form both memory and selector with a simple process. Conventional binary chalcogenide ovonic threshold switching (OTS) selectors such as GeXSe1−x or GeTe suffer from thermal instability. Furthermore, ternary OTS selectors are being investigated by doping various materials to overcome thermal instability. Here, we introduce a wide range of Ge1−xSx films to analyze and confirm the selector behavior for future applications. S–rich region (0.5 ≤ x ≤ 0.67) devices behaved as OTS selector with low leakage current (1.3 nA) and high thermal stability (amorphous up to 600 °C). To study the mechanism of devices with different compositions, the modified PF–model was used to calculate trap density, activation energy, subthreshold swing, and distance between traps. Additionally, extracted optical bandgap (1.65 – 3.45 eV) and urbach energy (166 – 103 meV) had good accordance with electrical characteristics of each device. This innovative research has potential to enable 3D X–point memory by combining conformal OTS selector and chalcogenide–based phase change memory.

Low-power phase-change memory cell based on a doped GeTe/InP heterostructure: a first-principles study

Low-power phase-change memory cell based on a doped GeTe/InP heterostructure: a first-principles study

Gray counters for non-volatile memories

New technologies for non-volatile memories combine the speed and byte addressability of current memory technologies with the low cost, density, and non-volatility of current storage technologies. They use energy only when writing or reading data. While some newer technologies have practically unlimited endurance, others, such as Phase Change Memory do not. However, this limited endurance surpasses that of solid state drives by several orders of magnitude. They can be integrated into the current memory storage hierarchy as a replacement for DRAM. To manage limited endurance, age-based wear leveling divides the memory into pages and counts the number of writes to a page. Pages with high counts can then be relegated to store more stable data. Counters experience “write concentration” as they are incremented as frequently as a page is written, but the changes are concentrated in a much smaller area around the least significant bit. Current designs store page write counters with the page table in the main memory unit.We propose and investigate an alternative counter design based on Gray codes that distributes the bit-flips resulting from the increments over the vast majority of the bits making up the counter. This is a bit-flip aware data structure that can be used in other contexts as well. We show that this design allows us to integrate the page counters into the phase change memory device. We also investigate counters using error control codes.

Design of plasmonic enhanced all-optical phase-change memory for secondary storage applications

Phase-change optical device has recently gained tremendous interest due to its ultra-fast transmitting speed, multiplexing and large bandwidth. However, majority of phase-change optical devices are only devoted to on-chip components such as optical tensor core and optical main memory, while developing a secondary storage memory in an optical manner is rarely reported. To address this issue, we propose a novel phase-change optical memory based on plasmonic resonance effects for secondary storage applications. Such design makes use of the plasmonic dimer nanoantenna to generate plasmonic resonance inside the chalcogenide alloy, and thus enables the performance improvements in terms of energy consumption and switching speed. It is found that choosing height, radius, and separation of the plasmonic nanoantenna as 10 nm, 150 nm, and 10 nm, respectively, allows for a write/erase energies of 100 and 240 pJ and a write/erase speed of 10 ns for crystallization and amorphization processes, respectively. Such performance merits encouragingly prevail conventional secondary storage memories and thus pave a route towards the advent of all-optical computer in near future.

Understanding the switching mechanism of oxygen-doped Sb phase-change material: Insights from first principles

The crystalline–amorphous–crystalline transition process of an oxygen-tuned Sb phase-change material has been obtained by employing ab initio molecular dynamic calculations. By analyzing the local atomic arrangement and the electron structure of the SbO system, the intrinsic mechanism is explored to comprehend the material function: (1) ultrafast crystallization and difficulty in creating a glassy state of a pure Sb material might be caused by the resonance bonding of linear arrangement Sb atoms in the rhombohedral phase; (2) the impurity oxygen atoms break the medium and long-range linear arrangement of the Sb network by steric effects and change the electronic structure of these Sb atoms bonded to oxygen atoms, i.e., the obvious increase in electron localization and the great decrease in state distribution around the Fermi surface due to the high electronegativity of oxygen. These factors set an effective barrier for crystallization and improve the amorphous stability and, thus, data retention. The present research and scheme provide important insights into the engineering and manipulation of a phase-change material through first-principles calculations toward non-volatile phase change memory.

Design of projected phase-change memory mushroom cells for low-resistance drift

Design of projected phase-change memory mushroom cells for low-resistance drift