Phase Accumulator Research Articles

FPGA-based Serial Port-controlled Frequency Adjustable Waveform Generator

This article explores the design, optimization, and applications of FPGA-based Direct Digital Synthesis (DDS) waveform generators. The DDS technology is widely used in signal generation and processing and is favored for its flexibility and precision. The paper discusses performance optimization strategies, focusing on enhancing frequency resolution, waveform quality, and phase accumulation speed. Suggestions include increasing phase accumulator’s bit width, optimizing the size of the phase lookup table, introducing frequency interpolation, and employing fast accumulation algorithms. Additionally, it delves into more applications such as high-precision testing, high-speed communication systems, multi-channel data synchronization, and multi-waveform outputs. The conclusion emphasizes the ongoing need for performance improvements and application advancements. Future directions include exploring higher-precision phase lookup table designs, sophisticated filtering, efficient accumulation algorithms, and leveraging advanced FPGA chips for broader application scope. Overall, FPGA-based DDS waveform generators exhibit significant potential across various domains, promising enhanced signal accuracy and adaptability.

Progress in new environmental friendly low temperature detector cooling systems development for the ATLAS and CMS experiments

In the frame of the progress towards the High Luminosity Program of the Large Hadron Collider at CERN, the ATLAS and CMS experiments are boosting the preparation of their new environmental friendly low temperature detector cooling systems. This paper will present a general overview of the progress in development and construction of the future CO2 cooling systems for silicon detectors at ATLAS and CMS (trackers, calorimeters and timing layers), due for implementation during the 3rd Long Shut Down of LHC (LS3). We will describe the selected technology for the primary chillers, based on an innovative transcritical cycle of R744 (refrigerant grade CO2) as coolant, and the oil-free secondary “on detector” CO2 pumped loop, based on the evolution of the successful 2 Phase Accumulator Control Loop (2PACL) concept. Different detector layers will profit from an homogenized infrastructure and will share multi-level redundancy that we will describe in details. The technical progresses achieved by the EP-DT group at CERN over the last years will be discussed in view of the challenges and key solutions developed to cope with the unprecedented scale of the systems. We will finally present how mechanics- and controls-related problems have been addressed via a vigorous prototyping programme, aiming at cost- and resource-effective construction of the final systems, which is starting now.

Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder

Improved speed, reduced delay, reduced size and reduced power are the most important requirements of integrated circuits. The carry select adder (CSA) is one of the most important adders in most data processors for performing arithmetic operations. The speed of parallel adders can be enhanced CSA, which widens the area to speed and eliminates propagation delays. The major problem faced in CSA is inefficient area due to the usage of multiple pairs of Ripple carry adders (RCAs) for generating the sums and carry. This research paper proposes the modified 32-bit square root carry select adder (MSCSLA) to improve the direct digital synthesizer’s performance (DDS). DDS plays an effective role in the digital system due to its ability of broad frequency generation. Phase accumulator is the main component in the DDS synthesizer, where the speed of the adder is enhanced through MSCSLA. The general square root CSA still consumes more power due to the assembly of more RCAs. Hence, in the proposed approach, certain sets of RCAs are replaced with BEC1 (Binary to excess 1 convertor) to improve the speed and reduce the delay of the adder. Finally, the continuous sinusoidal waveform is attained by attenuating the high-frequency components by adopting a low pass filter. The entire structure of DDS is designed using Xilinx Verilog coding. The Simulation result shows better outcomes in terms of area, delay, power, and high performance in the DDS synthesizer compared to the existing CSAs. When compared to the existing adders, the area occupied by the proposed MSCSLA model is attained to be 636[Formula: see text][Formula: see text]m2, the power is achieved as 50.125[Formula: see text][Formula: see text]W and delay is attained to be 1.280[Formula: see text]ns, which are comparatively less. When comparing delay and maximum frequency with the existing techniques, the proposed model obtained minimum delay and maximum frequency. The overall power consumption by the proposed model is also attained to be lower than the existing techniques.

Low power pipeline-parallel phase accumulator

Low power pipeline-parallel phase accumulator

An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering

This brief proposes a high spurious-free dynamic range (SFDR) pulse output direct digital frequency synthesizer (PDDS) with low complexity and low power consumption. Independent and uniformly distributed (IUD) high-pass-shaped dither is added to the phase accumulator output, resulting in a wideband spurious-free and low close-in noise floor. The power efficiency and speed are increased by reducing the sampling frequency of the ${m}$ -sequence generator and the high-pass filter (HPF). The SFDR improves by 29 dB as a result of the HPF, which is confirmed with a field-programmable gate array (FPGA) implementation. The application specified integrated circuit (ASIC) occupies $1168~{\mu \text {m}^{2}}$ on nangate 45-nm CMOS process and consumes 80.2 and $398~{\mu }\text{W}$ from a 1.2-V supply with the dither generator running at ${({1}/{4})f_{\text {clk}}}$ and ${f_{\text {clk}}}$ ( ${f_{\text {clk}}}=2$ GHz), respectively.

Implementation of the Configuration Structure of an Integrated Computational Core of a Pulsed NQR Sensor Based on FPGA.

This paper presents a method for implementing the configuration structure of an integrated computational core of a pulsed nuclear quadrupole resonance (NQR) sensor based on a field-programmable gate array (FPGA), which comprises the following modules: a three-channel direct digital synthesizer (DDS), a pulse sequence shaper and a software-defined radio. Experimental studies carried out using the in-circuit analyzer SignalTap Logic Analyzer have confirmed the reliability of the correct and stable operation of the functional modules of the configuration structure at all stages of signal transformations, starting from the formation of the envelope of the excitation pulses and ending with the obtainment of low-frequency quadrature signals at the outlet of the compensating filters. The time and frequency dependences of the amplitude of the output signals generated using the DDS based on a 48 bit phase accumulator are investigated. This development can be used when creating pulsed coherent NQR sensors in the frequency range of 1 MHz–50 MHz.

An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

Hardware Implementation of Amplitude Shift Keying and Quadrature Amplitude Modulators Using FPGA

In our paper, we present the implementation of two kinds of FPGA-based modulators: ASK and QAM signal modulators. The ASK modulators we implemented are OOK, ASK, and 4ASK, then the QAM modulators implemented are 4QAM and 16QAM. The generation of the sine wave carrier is the main task when implementing any digital transmitter including ASK and QAM modulators. For us to implement these modulators, a sine function with floating-point operation as per IEEE754 standards is used based on Hardware Description Language technique. When the carrier is generated, the digital message modulates the amplitude of the carrier. To implement the QAM modulator, we need two sinusoidal carriers. A cosine function and a sine function are built to get the two carriers. Alongside to this work, ASK and QAM signal modulators are implemented using 26-bit phase accumulator and Look Up Table to generate the sine and cosine functions, then comparison of speed, occupied area and estimated power consume are done with the proposed modulators. Without using DSP builder tools or an Altera system generator, we implemented the whole systems using VHDL on cyclone IV-E-EP4CE115F29C7N of the board DE2-115. In general, the proposed modulator design present low area and power consummation than modulator using LUT or CORDIC.

Design of DDS Multi-waveform Generator Based on CPLD

Traditional Direct Digital Synthesis (DDS) waveform generators were usually completed by DDS chips, which were expensive and poorly customizable. This paper proposed a CPLD-based DDS multi-waveform generator design. DDS was independently developed and programmed by VHDL language. The system could be interfaced with PC. The system was mainly divided into two parts: upper computer and lower computer. The upper computer part mainly included the main interface design of the system, the sending of control commands and the receiving part of data. The sending and receiving of commands and data was realized by serial communication. The upper computer part was programmed by High-level programming language named DELPHI. The lower computer part mainly included DDS design part, the reception of control commands and the transmission of data, etc., the lower computer part mainly adopt VHDL language to be programmed in CPLD. The DDS design part mainly included the design of the phase accumulator, the design of the ROM, the design of the D/A part, and the design of the low-pass filter. The system could adjust the frequency of the output waveform by adjusting the size of the frequency word, and adjust the waveform shape of the system output by adjusting the internal data of the ROM. Simulation and experimental results showed that: the DDS multi-waveform generator designed by CPLD could achieve the expected goal, and the work effect was good.

DIRECT DIGITAL SYNTHESIZER IN A NEW MATHEMATICAL BASIS

The principles of the construction and operation of a digital synthesizer for direct frequency synthesis with acceleration of computational operations by using a residual class system (RNS) are considered. The specifics of the implementation of the operation of direct and inverse transformations from the positional number system to the number system of the residual classes are described. A mathematical model of a synthesizer with a phase accumulator in the system of residual classes is considered. The ways of designing a digital synthesizer of direct synthesis with a phase accumulator in the RNS system and a sinusoidal DAC are considered. In traditional schemes, the conversion of residuals to the value of an analog signal occurs in several stages, where conversion to a binary system is one of the stages. This procedure degrades the speed of the RNS system, adding additional constraints and increasing the waiting time for the conversion result. Methods of converting from RNS to binary number system for basic operations are considered. A DDS design with a phase accumulator in the residual class system and a converter to an analog signal form without using a slow ROM is proposed. The problems of efficient use of the synthesizer crystal area and reduction of delays in the formation of the output signal are considered. A study of one of the main functional blocks of a direct digital frequency synthesizer, a digital-to-analog converter, has been carried out. The architecture of a direct digital frequency synthesizer with a DAC direct conversion from a non-positional number system to an analog signal is proposed. The main sources of noise generation in digital computational synthesizers of the proposed type are investigated. A mathematical model is proposed for calculating the power spectral density of phase noise, which will allow analyzing the noise characteristics in synthesizers built on the indicated principles.

Development of a Non-invasive Deep Brain Stimulator With Precise Positioning and Real-Time Monitoring of Bioimpedance

Methods by which to achieve non-invasive deep brain stimulation via temporally interfering with electric fields have been proposed, but the precision of the positioning of the stimulation and the reliability and stability of the outputs require improvement. In this study, a temporally interfering electrical stimulator was developed based on a neuromodulation technique using the interference modulation waveform produced by several high-frequency electrical stimuli to treat neurodegenerative diseases. The device and auxiliary software constitute a non-invasive neuromodulation system. The technical problems related to the multichannel high-precision output of the device were solved by an analog phase accumulator and a special driving circuit to reduce crosstalk. The function of measuring bioimpedance in real time was integrated into the stimulator to improve effectiveness. Finite element simulation and phantom measurements were performed to find the functional relations among the target coordinates, current ratio, and electrode position in the simplified model. Then, an appropriate approach was proposed to find electrode configurations for desired target locations in a detailed and realistic mouse model. A mouse validation experiment was carried out under the guidance of a simulation, and the reliability and positioning accuracy of temporally interfering electric stimulators were verified. Stimulator improvement and precision positioning solutions promise opportunities for further studies of temporally interfering electrical stimulation.

Review of high-speed phase accumulator for direct digital frequency synthesizer

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.

Impedance Cytometry for Detection of Particle and Counting using Low Phase Noise DDFS – LUT

The biotechnology is widely growing with many technologies, still we see a large gap in real-time implementation of complete blood counting. To increase the resolution and accuracy of the measurements advanced communication DDFS can be used. The elements in Direct Digital Frequency Synthesizers (DDFS) involved are: phase accumulator, a phase to amplitude converter which also called look up table (LUT), a digital to analog converter along with active filter. Direct digital frequency synthesis is a method for generating complex high - frequency waveforms for specific applications. This DDFS generates frequency resolution which makes it ideal components use in radar system, software defined radio, modern wireless communicating system, advanced satellite navigation purpose. Use cases for high frequency we get interrupt with spurious noise, larger ROM size, and high power consumption of DDFS signal. In this paper we are proposing the use of signal generated from DDFS to impedance cytometry in which the number of particles gets detected by getting the output frequency different from the input frequency. Due to use of small frequency range of signal spurious noise, power consumption and ROM size will be less with effective performance.

DIRECT DIGITAL FREQUENCY SYNTHESIZER IN THE RESIDUE NUMBER SYSTEM

The principles of construction and operation of direct digital frequency synthesizers are considered in order to speed up computational operations using Residue Number System. The problems of forming the output signals are considered. The specifics of the implementation of the operation of direct and reverse transformations from positional to non-positional number systems are described. A mathematical model of a synthesizer with a phase accumulator in a Residue Number System is considered. Methods for converting from RNS (Residue Number System) to binary system for problematic operations are considered. The design of a DDS (Direct Digital Synthesizer) with a phase accumulator in a Residue Number System and a converter to an analogue signal form is proposed without the use of slow ROM (Read Only Memory). The article deals with the issues of efficiency of the crystal area of the synthesizer and the reduction of the delays in the formation of the output signal.

Comparative Study of DDS with Different Types of Phase Accumulators

The paper deals with the problems of delayed transfer signals in the direct digital synthesizer (DDS) phase accumulator adders. Transfer delay is one of the factors that affect the maximum output frequency of the DDS synthesizer. The main types of adders used in DDS synthesizers are described. Separately, attention was paid to the adder with a consistent transfer of the transfer signal, adders with a transmission carry signal with a fixed block length, adders with a signal transmission delay with a variable block length, and a mathematical analysis of the origin and duration of the delay of the transfer signal in them. It was found that the use of a transfer adder with a variable length of a block in the core of a direct digital synthesizer would increase the maximum output frequency by 2.4 times compared to the adder with a parallel transfer, and by 1.43 times as compared with the adder with a fixed length the block.

FPGA implementation of an arbitrary resample rate, FOH, pulse width modulator

This study presents a field-programmable gate array implementation of an advanced pulse-width modulator which combines a first-order hold (FOH) with phase accumulator carrier pulse-width modulation (PACPWM) for significantly reduced phase delay, and bandwidth extension in multi-level applications. The FOH block supports arbitrary resampling rates and operates in a single clock cycle for simple integration into multi-rate or asynchronous systems. The proposed modulator is validated experimentally, with performance matching that predicted for both FOH and a zero-order hold (ZOH). For PWM with 8 kHz carrier frequency and 50.4 kHz resampling frequency, a 15 degree phase delay advantage is demonstrated for FOH compared with ZOH across the 5–10 kHz modulation band.

Synchronisation of a distributed control and data acquisition system for modular multi‐level PHIL amplifiers

This research presents a novel technique to synchronise a modular control and data acquisition system for the testing of multi-level power hardware-in-the-loop (PHIL) amplifiers. The methodology is inspired by the precision timing protocol, used to compensate for communications latency between distributed control nodes. It uses a non-conventional digital pulse-width modulation (PWM) technique, phase accumulator carrier pulse-width modulation to achieve carrier synchronisation across the system. A prototype design has been demonstrated on a three-node test bench, showing single clock cycle (10 ns) precision when synchronising a 25 kHz PWM carrier wave, with minimal sensitivity to communications link propagation delays.

Neutrosophic data formation using Gaussian filter based costas coding for wireless communication systems

Outstanding advantages of OFDM helps high data rate communication systems such as Digital Video Broadcasting (DVB) and mobile worldwide interoperability for microwave access (mobile Wi-MAX). But, OFDM system grieves from grave issue of high PAPR. In OFDM system data output is superposition of multiple sub-carriers and leads to big data. In this case some instantaneous power output might increase greatly and become far higher than the mean power of system. In order to make Neutrosophic data for less PAPR criteria, Gaussian filter based Costas coding is proposed. This paper also proposes feeding the Orthogonal Frequency Division Multiplexed signal (OFDM) into a phase accumulator to obtain frequency modulation, with the aim of reducing the peak to average power ratio (PAPR). For associated radar with modulated waveform mentioned here can be used to enhance the performance. It is widely used to analyze the variation of the output waveform further, the implementation results using MATLAB show that the ratio of average power to peak power is reducing considerably in comparing with the conventional method. Consequently; the signal can assume to fade in a frequency selective channel without an equalizer.

Design and Implementation of Modified DDS Based on FPGA

Frequency synthesizer is known as the "heart" of electronic systems, direct digital frequency synthesizer (DDS) relative to the first two generation of frequency synthesis technology has obvious advantages, but also existing traditional structure of the DDS output stray too, shortage of output frequency is limited. Aiming at these two problems, the overall structure of DDS is improved by compression algorithm, phase jitter and balanced DAC structure. The parallel phase accumulator is designed with parallel and flow technology, and the output frequency of the system is improved. At the same time, using the FPGA technology, the various modules were implemented by Verilog HDL language design, and finally the modified DDS model was completed based on FPGA design.

Development of ROACH Firmware for Microwave Multiplexed X-Ray TES Microcalorimeters

We are developing room temperature electronics based upon the ROACH platform to readout microwave multiplexed X-ray TES. ROACH is an open-source hardware and software platform featuring a large Xilinx Field Programmable Gate Array (FPGA), Power PC processor, several 10 GB Ethernet SFP+ interfaces, and a collection of daughter boards for analog signal generation and acquisition. The combination of a ROACH board, ADC/DAC conversion daughter boards, and hardware for RF mixing allows for the generation and capture of multiple RF tones for reading out microwave multiplexed X-ray TES microcalorimeters. The FPGA is used to generate multiple tones in base band, from 10 MHz to 250 MHz, which are subsequently mixed to RF in the multiple GHz range and sent through the microwave multiplexer. The tones are generated in the FPGA by storing a large lookup table in Quad Data Rate SRAM modules and playing out the waveform to a DAC board. Once the signal has been modulated to RF, passed through the microwave multiplexer, and has been modulated back to base band, the signal is digitized by an ADC board. The tones are modulated to 0 Hz by using a FPGA circuit consisting of a polyphase filter bank, several Xilinx FFT blocks, Xilinx CORDIC blocks (for converting to magnitude and phase), and special phase accumulator circuit for mixing to exactly 0 Hz. Upwards of 256 channels can be simultaneously captured and written into a bank of 256 First-In-First-Out (FIFO) memories, with each FIFO corresponding to a channel. Individual channel data can be further processed in the FPGA before being streamed through a 10 GB Ethernet fiber-optic interface to a Linux system. The Linux system runs software written in Python and QT C++ for controlling the ROACH system, capturing data, and processing data.