Peripheral Circuits Research Articles

Approaching the Ideal Linearity in Epitaxial Crystalline-Type Memristor by Controlling Filament Growth.

Brain-inspired neuromorphic computing has attracted widespread attention owing to its ability to perform parallel and energy-efficient computation. However, the synaptic weight of amorphous/polycrystalline oxide based memristor usually exhibits large nonlinear behavior with high asymmetry, which aggravates the complexity of peripheral circuit system. Controllable growth of conductive filaments is highly demanded for achieving the highly linear conductance modulation. However, the stochastic behavior of the filament growth in commonly used amorphous/polycrystalline oxide memristor makes it very challenging. Here, the epitaxially grown Hf0.5Zr0.5O2-based memristor with the linearity and symmetry approaching ideal case is reported. A layer of Cu nanoparticles is inserted into epitaxially grown Hf0.5Zr0.5O2 film to form the grain boundaries due to the breaking of the epitaxial growth. By combining with the local electric field enhancement, the growth of filament is confined in the grain boundaries due to the fact that the diffusion of oxygen vacancy in crystalline lattice is more difficult than that in the grain boundaries. Furthermore, the decimal operation and high-accuracy neural network are demonstrated by utilizing the highly linear and multi-level conductance modulation capacity. This method opens an avenue to control the filament growth for the application of resistance random access memory (RRAM) and neuromorphic computing.

A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network

A programmable logic device based on a memristor-diode crossbar and CMOS logic has been developed. The crossbar implements NAND logic gates using memristor ratioed logic and CMOS inverters. The digitally controlled peripheral circuit provides digital signals transmission and allows modification and evaluation memristor states in the crossbar. The proposed logic device circuit requires fewer transistors than known analogues and less area on the chip.The maximum size of the crossbar in a logic device is estimated by numerical simulation at the level of electrical circuits. The limited size is caused by the degradation of the logic levels voltages in the memristor-diode crossbar. The operability of peripheral circuits as part of a complete electrical circuit of a logic device is demonstrated during the simulation of the execution of logical operations, the processes of modification and evaluation states of individual memristors.

Optimization Design of Variable Reluctance Resolver Based on Three-phase Symmetrical Winding

Optimization Design of Variable Reluctance Resolver Based on Three-phase Symmetrical Winding

Design and Application of Indoor Intelligent Light Emitting Diode Lighting

In this research, an indoor intelligent light emitting diode (LED) lighting device is designed, which includes environmental brightness detection module, temperature detection module, display module and LED driving module. S5052 photodiode is selected for environmental brightness level, which can work normally in the environment of −25 °C to 75 °C, and the analog signal is converted into recognizable digital signal through MCP3204 A/D converter. The DS18B20 sensor is selected to measure the temperature, which is connected with the single chip microcomputer to collect the indoor temperature signal. Adopting constant current drive mode, HV9910 LED driver chip is selected to convert 220 V AC power supply into 5 V DC power supply, and AD1585 chip is used as reference power supply to suppress the fluctuation of DC power supply. The display module takes STC12C5A60S2 single chip microcomputer as the control module, and integrates MAX810 special reset circuit, 2-channel PWM and 8-channel 10-bit A/D converter, thus simplifying the peripheral circuit. During the test, the single chip microcomputer is initialized, the intelligent control part is embedded with data analysis technology, and the modular debugging method is adopted, and the illumination brightness value meets the expectations under different conditions. The ambient temperature is compared with the test temperature to keep consistent. Based on PWM method, dimming is carried out, and two environments are set (the first one is to maintain the ambient light illumination of 300lx, and the other one is to maintain the ambient light illumination of 100lx). The results show that the designed system is suitable for different lighting environments and can adjust the indoor lighting brightness adaptively.

Architecture-level energy model for high-capacity STT-MRAM memory

ABSTRACT Nowadays, STT-MRAM has emerged as one of the leading contenders for next-generation memory technologies. However, STT-MRAM still exhibits high energy consumption due to its peripheral circuits, including the read/write and the sample amplifier (SA) circuits. Therefore, it is crucial to accurately evaluate the energy consumption of memory architectures during the early stages of the design process. Traditionally, energy evaluation can be conducted using the NVSim platform. However, the peripheral read/write circuitry of STT-MRAM undergoes iterative improvements, which cannot be promptly incorporated into NVSim. To addreGss this limitation and to enable comprehensive energy consumption evaluations spanning from device-level to architecture-level for STT-MRAM, an architecture-level energy consumption model is proposed in this paper. The model offers high accuracy and flexibility for the STT-MRAM memory array structure, abstracting the influences of read/write circuits for power evaluations. Comparative analysis is performed between the proposed model and the traditional approaches. When estimating a memory array with 128 × 64, the deviation using the proposed model is less than 2%, showing improved accuracy compared to that with analytical formulas. Notably, the proposed model offers up to 97% time savings in the whole circuit simulation, thus enhancing efficiency in the design and evaluation process.

Research on Intelligent Monitoring System of Intelligent Transmission Line Based on Computer Internet of Things Technology

The author proposes an intelligent early-warning system for preventing external damage of transmission lines. The system uses TI-TMS320DM6446 as the core, the peripheral circuit configuration and video monitoring; The moving objects captured by PTZ camera are detected and identified by using mixed Gaussian model, background difference and minimum tangent matrix, and alarm signals are provided. According to the particularity of the power supply of the equipment on the transmission line, the basic power management of the system is analyzed in detail. A reliable power management scheme is designed. The practical application proves that this method has good real-time performance and has obvious effect on preventing power cable damage by force.

Hardware Implementation of a Fully Functional Stochastic p‐STT Neuron for Probabilistic Computing

AbstractA stochastic binary neuron is developed for probabilistic computing using a perpendicular spin‐transfer torque (p‐STT) neuron device and its associated peripheral circuits. The p‐STT neuron device, featuring a 300‐nm‐diameter pillar structure and a perpendicular magnetic‐tunnelling‐junction spin valve, is fabricated to exhibit stochastic switching behavior characterized by a sigmoidal function. The stochastic switching mechanism is influenced by the presence of defect sites within the device. The hardware implementation encompasses the construction of the neuron peripheral circuit, including the fire‐spike generation, sensing amplifier, and reset circuit, using a 28‐nm‐design‐rule complementary metal‐oxide‐semiconductor (C‐MOSFET) process. This hardware realization also demonstrates stochastic switching behavior with a sigmoidal function. However, a slight shift toward higher input voltage spike amplitudes is observed compared to the p‐STT neuron device alone, owing to voltage drop within the peripheral circuit. Furthermore, the software‐based investigation focuses on validating the feasibility of a spiking neural network. The temporal correlation detection is estimated using the stochastic switching probability derived from the hardware implementation, indicating successful synchronization between the correlated input neuron and the output p‐STT neuron.

Bidirectional brain-body interactions during natural story listening

Narratives can synchronize neural and physiological signals between individuals, but the relationship between these signals, and the underlying mechanism, is unclear. We hypothesized a top-down effect of cognition on arousal and predicted that auditory narratives will drive not only brain signals but also peripheral physiological signals. We find that auditory narratives entrained gaze variation, saccade initiation, pupil size, and heart rate. This is consistent with a top-down effect of cognition on autonomic function. We also hypothesized a bottom-up effect, whereby autonomic physiology affects arousal. Controlled breathing affected pupil size, and heart rate was entrained by controlled saccades. Additionally, fluctuations in heart rate preceded fluctuations of pupil size and brain signals. Gaze variation, pupil size, and heart rate were all associated with anterior-central brain signals. Together, these results suggest bidirectional causal effects between peripheral autonomic function and central brain circuits involved in the control of arousal.

Long‐term and short‐term plasticity independently mimicked in highly reliable Ru‐doped Ge2Sb2Te5 electronic synapses

AbstractIn order to fulfill the complex cognitive behaviors in neuromorphic systems with reduced peripheral circuits, the reliable electronic synapses mimicked by single device that achieves diverse long‐term and short‐term plasticity are essential. Phase change random access memory (PCRAM) is of great potential for artificial synapses, which faces, however, difficulty to realize short‐term plasticity due to the long‐lasting resistance drift. This work reports the ruthenium‐doped Ge2Sb2Te5 (RuGST) based PCRAM, demonstrating a series of synaptic behaviors of short‐term potentiation, pair‐pulse facilitation, long‐term depression, and short‐term plasticity in the same single device. The optimized RuGST electronic synapse with the high transformation temperature of hexagonal phase >380°C, the outstanding endurance >108 cycles, the low resistance drift factor of 0.092, as well as the extremely high linearity with correlation coefficients of 0.999 and 0.976 in parts of potentiation and depression. Further investigations also go insight to mechanisms of Ru doping according to thorough microstructure characterization, revealing that Ru dopant is able to enter GST lattices thus changing and stabilizing atomic arrangement of GST. This leads to the short‐term plasticity realized by RuGST PCRAM. Eventually, the proposed RuGST electronic synapses performs a high accuracy of ~94.1% in a task of image recognition of CIFAR‐100 database using ResNet 101. This work promotes the development of PCRAM platforms for large‐scale neuromorphic systems.

A Self-Oscillated Organic Synapse for In-Memory Two-Factor Authentication.

Entering the era of AI 2.0, bio-inspired target recognition facilitates life. However, target recognition may suffer from some risks when the target is hijacked. Therefore, it is significantly important to provide an encryption process prior to neuromorphic computing. In this work, enlightened from time-varied synaptic rule, an in-memory asymmetric encryption as pre-authentication is utilized with subsequent convolutional neural network (ConvNet) for target recognition, achieving in-memory two-factor authentication (IM-2FA). The unipolar self-oscillated synaptic behavior is adopted to function as in-memory asymmetric encryption, which can greatly decrease the complexity of the peripheral circuit compared to bipolar stimulation. Results show that without passing the encryption process with suitable weights at the correct time, the ConvNet for target recognition will not work properly with an extremely low accuracy lower than 0.86%, thus effectively blocking out the potential risks of involuntary access. When a set of correct weights is evolved at a suitable time, a recognition rate as high as 99.82% can be implemented for target recognition, which verifies the effectiveness of the IM-2FA strategy.

Vertically Stackable Ovonic Threshold Switch Oscillator Using Atomic Layer Deposited Ge0.6Se0.4 Film for High-Density Artificial Neural Networks.

Nanodevice oscillators (nano-oscillators) have received considerable attention to implement in neuromorphic computing as hardware because they can significantly improve the device integration density and energy efficiency compared to complementary metal oxide semiconductor circuit-based oscillators. This work demonstrates vertically stackable nano-oscillators using an ovonic threshold switch (OTS) for high-density neuromorphic hardware. A vertically stackable Ge0.6Se0.4 OTS-oscillator (VOTS-OSC) is fabricated with a vertical crossbar array structure by growing Ge0.6Se0.4 film conformally on a contact hole structure using atomic layer deposition. The VOTS-OSC can be vertically integrated onto peripheral circuits without causing thermal damage because the fabrication temperature is <400 °C. The fabricated device exhibits oscillation characteristics, which can serve as leaky integrate-and-fire neurons in spiking neural networks (SNNs) and coupled oscillators in oscillatory neural networks (ONNs). For practical applications, pattern recognition and vertex coloring are demonstrated with SNNs and ONNs, respectively, using semiempirical simulations. This structure increases the oscillator integration density significantly, enabling complex tasks with a large number of oscillators. Moreover, it can enhance the computational speed of neural networks due to its rapid switching speed.

Development and Implementation of an FPGA-Embedded Multimedia Remote Monitoring System for Information Technology Server Room Management

Conventional data acquisition systems face challenges in achieving high acquisition speeds and rapid storage of large data volumes using microcontrollers. In contrast, field-programmable gate arrays (FPGAs) offer numerous advantages, including high clock frequencies, minimal internal delays, fast operational speeds, abundant internal RAM resources, and simplified control of complex peripheral circuits. This study presents the design of an FPGA-based multimedia remote monitoring system for information technology server rooms. The proposed system utilizes an FPGA as the primary controller and incorporates environmental sensors, electrical energy sensors, carbon monoxide sensors, smoke sensors, and A/D converter modules to monitor multiple locations within the server room. Simultaneously, the FPGA transmits the collected data from each monitoring point via a serial port to an LCD serial screen for display. An alarm is triggered if any environmental anomalies are detected, indicating abnormal statuses. Additionally, the system employs the fast Fourier transform algorithm and butterfly operations to derive voltage and current AC quantities, while utilizing relative temperature differences to identify equipment faults within the server room. The system is evaluated in terms of functionality, user-friendliness, and reliability. Experimental results demonstrate that all performance measures align with expectations, fulfilling the initial design objectives and highlighting the potential applicability and relevance of FPGA technology in the monitoring field. In addition, a comparison between FPGA and traditional microcontroller systems is performed, showcasing the superior processing speed and performance of the FPGA-based system. This comparative analysis further validates the advantages of using FPGA technology in high-speed data acquisition and monitoring applications.

Design and preliminary test results of the charge sensitive amplifier for gain-less charge readout in high-pressure TPC

This paper presents the design and electrical test results of a low-noise front-end chip (named Topmetal-S) in a High-pressure Time Projection Chamber (TPC) for searching the neutrinoless double beta decay. The Topmetal-S has been fabricated in a 130 nm CMOS technology. The proposed front-end chip consists of a charge collection electrode, a Charge Sensitive Amplifier (CSA) and peripheral circuits. The test results indicate that the CSA features an input linear dynamic range of approximately 6.64 fC, a charge-conversion gain of about 220 mV/fC and an Equivalent Noise Charge (ENC) of approximately 115 e - after a digital trapezoidal pulse shaper.

Cryogenic flip-chip interconnection for silicon qubit devices

Interfacing qubits with peripheral control circuitry poses one of the major common challenges toward realization of large-scale quantum computation. Spin qubits in silicon quantum dots (QDs)are particularly promising for scaling up, owing to the potential benefits from the know-how of the semiconductor industry. In this paper, we focus on the interposer technique as one of the potential solutions for the quantum–classical interface problem and report DC and RF characterization of a silicon QD device mounted on an interposer. We demonstrate flip-chip interconnection with the qubit device down to 4.2 K by observing Coulomb diamonds. We furthermore propose and demonstrate a laser-cut technique to disconnect peripheral circuits no longer in need. These results may pave the way toward system-on-a-chip quantum–classical integration for future quantum processors.

In-sensor nonlinear convolutional processing based on hybrid MTJ/CMOS arrays

In-sensor computing implemented by novel neuromorphic devices has been regarded as the potential technology to break the acquisition wall. Moreover, the nonlinear convolution inspired by the biological neural system outperforms the traditional linear convolution. Therefore, realizing the in-sensor nonlinear convolutional processing with the intrinsic nonlinearity of novel neuromorphic devices would be exciting and hardware friendly. Here, a new type of in-sensor nonlinear convolutional processing architecture is proposed based on STT-MTJ (spin transfer torque-magnetic tunnel junction) devices and simple peripheral circuits. The nonlinear dynamic characters of the STT-MTJ device are regulated by bias currents and magnetic fields. Meanwhile, the hybrid STT-MTJ/CMOS (complementary metal oxide semiconductor) circuit exhibits nonlinear dependence of the output voltage on bias currents and magnetic fields. In this way, a nonlinear convolutional unit is developed by the inherent property of hardware. Based on the in-sensor nonlinear convolutional unit, a convolutional network is simulated to perform the classification task, and a high accuracy is realized. This work indicates that the in-sensor nonlinear convolution offers a promising way to develop in-sensor computing at the edge intelligence devices.

Hardware‐Level Image Recognition System Based on ZnO Photo‐Synapse Array with the Self‐Denoising Function

AbstractThe emerging optoelectronic neuromorphic devices are widely concerned due to their capability to integrate the functions of signal sensing, memory, and processing. Although significant advancements have been made in the study of individual optoelectronic synaptic devices, the development of hardware‐level image recognition systems based on photo‐synapse arrays remains a challenge. In this study, a crosstalk‐free, easy‐to‐integrate, and scalable 8 × 8 crossbar array for optical image sensing and storage is demonstrated using vertical two‐terminal ZnO photo‐synapses with the self‐denoising function. By designing peripheral circuits, a complete hardware‐level artificial visual system is constructed that successfully implements the real‐time pattern recognition tasks for 8 × 8 pixel images. The excellent performance of the photo‐synapse array shows its remarkable ability in highly efficient optic neuromorphic computing. Additionally, an in‐sensor reservoir computing (RC) system is constructed for image recognition of handwritten digits. The system achieves a high classification accuracy of 95.1%.

Quantized Magnetic Domain Wall Synapse for Efficient Deep Neural Networks.

The quantization of synaptic weights using emerging nonvolatile memory (NVM) devices has emerged as a promising solution to implement computationally efficient neural networks on resource constrained hardware. However, the practical implementation of such synaptic weights is hampered by the imperfect memory characteristics, specifically the availability of limited number of quantized states and the presence of large intrinsic device variation and stochasticity involved in writing the synaptic states. This article presents on-chip training and inference of a neural network using quantized magnetic domain wall (DW)-based synaptic array and CMOS peripheral circuits. A rigorous model of the magnetic DW device considering stochasticity and process variations has been utilized for the synapse. To achieve stable quantized weights, DW pinning has been achieved by means of physical constrictions. Finally, VGG8 architecture for CIFAR-10 image classification has been simulated by using the extracted synaptic device characteristics. The performance in terms of accuracy, energy, latency, and area consumption has been evaluated while considering the process variations and nonidealities in the DW device as well as the peripheral circuits. The proposed quantized neural network (QNN) architecture achieves efficient on-chip learning with 92.4% and 90.4% training and inference accuracy, respectively. In comparison to pure CMOS-based design, it demonstrates an overall improvement in area, energy, and latency by 13.8 × , 9.6 × , and 3.5 × , respectively.

Protease-Induced Excitation of Dorsal Root Ganglion Neurons in Response to Acute Perturbation of the Gut Microbiota Is Associated With Visceral and Somatic Hypersensitivity

Abdominal pain is a major symptom of diseases that are associated with microbial dysbiosis, including irritable bowel syndrome and inflammatory bowel disease. Germ-free mice are more prone to abdominal pain than conventionally-housed mice, and reconstitution of the microbiota in germ-free mice reduces abdominal pain sensitivity. However, the mechanisms underlying microbial modulation of pain remain elusive. We hypothesized that disruption of the intestinal microbiota modulates the excitability of peripheral nociceptive neurons. In vivo and in vitro assays of visceral sensation were performed on mice treated with the non-absorbable antibiotic vancomycin (50 μg/mL in drinking water) for 7 days and water-treated control mice. Bacterial dysbiosis was verified by 16s rRNA analysis of stool microbial composition. Treatment of mice with vancomycin led to an increased sensitivity to colonic distension in vivo and in vitro, and hyperexcitability of dorsal root ganglion (DRG) neurons in vitro, compared to controls. Interestingly, hyperexcitability of DRG neurons was not restricted to those that innervated the gut, suggesting a widespread effect of gut dysbiosis on peripheral pain circuits. Consistent with this, mice treated with vancomycin were more sensitive than control mice to thermal stimuli applied to hind paws. Incubation of DRG neurons from naïve mice in serum from vancomycin-treated mice increased DRG neuron excitability, suggesting that microbial dysbiosis alters circulating mediators that influence nociception. The cysteine protease inhibitor E64 (30 nM) and the protease-activated receptor 2 (PAR-2) antagonist GB-83 (10 μM) each blocked the increase in DRG neuron excitability in response to serum from vancomycin-treated mice, as did the knockout of PAR-2 in NaV1.8-expressing neurons. Stool supernatant, but not colonic supernatant, from mice treated with vancomycin increased DRG neuron excitability via cysteine protease activation of PAR-2. Together, these data suggest that gut microbial dysbiosis alters pain sensitivity and identify cysteine proteases as a potential mediator of this effect.

A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations

Artificial intelligence algorithms play important roles in image classification to speech recognition, which contains enormous Boolean logic and multiplication operations. Traditional von Neumann architecture separates computing and storage units, which leads to “power walls” and “memory walls” problems. In-memory computing (IMC) is a promising method to solve these problems. In this work, we propose an IMC macro based on customed 9T-SRAM, which can be configured in memory, Boolean logic and multiply-and-accumulate (MAC) modes. The 9T-SRAM adopts read/write decoupled and a tail transistor structure, which enhances the read stability and reduces power consumption. With the bias rows, Boolean logic results are obtained from the differential voltages on two bitlines, reducing the peripheral circuit for reference voltage generation. Furthermore, the bias rows replace analog to digital converter (ADC) to binarize the MAC result, reducing the area overhead. In a 55 nm process, simulations manifest the 9T-SRAM shows enhanced read static noise margin, and the macro exhibits stable IMC operations and high energy-efficiency.

A novel time-domain in-memory computing unit using STT-MRAM

Advancements in technologies like Big Data, IoT, and AI have revealed a bottleneck in traditional von-Neumann architecture, resulting in high energy consumption and limited memory bandwidth. In-memory computing (IMC) presents a promising solution by enabling computations directly within the memory, enhancing energy-efficient computing. The existing time-domain (TD)-based IMC computations either require multiple cycles for computation through a successive read/write approach or contribute to the complexity of the peripheral circuit by adopting a cumulative delay approach. In this paper, we present a novel array architecture that utilizes spin transfer torque magnetic random access memory (STT-MRAM) bit-cells, mitigating source degeneration issue. By leveraging this advanced technology and employing a TD computing scheme, we have successfully implemented various arithmetic operations, alongside a comprehensive set of Boolean logic operations. Our design demonstrates improved area and energy efficiency compared to other existing TD computing schemes. Furthermore, despite the higher delay, our parameter-driven optimization approach efficiently minimizes it. To validate our proposal, we performed simulations using the 45 nm CMOS process and the Verilog-A based magnetic tunnel junction (MTJ) compact model. Through meticulous Monte-Carlo simulations, considering CMOS variations, the results demonstrate enhanced computational accuracy with increasing Tunnel Magnetoresistance (TMR) ratio, showcasing the potential of our architecture in advancing the field of computing.