Period Jitter Research Articles

High precision low jitter pulse generator implemented with FPGA transceiver

Precisely controlled digital pulse plays a crucial role in various cutting-edge testing applications. This paper introduces an innovative approach to digital pulse generation utilizing an FPGA transceiver, with the AMD evaluation board ZCU102 serving as a demonstrative platform. In the normal mode, the transmitter generates a serial bit stream, enabling the generation of single or repeated pulses with configurable width and period. In the high precision mode, an internal dedicated phase interpolator enhances the configuration step size for width and period by up to 64 times, providing finer phase shift capability. The demonstration system operates at a line rate of 10Gbps, achieving a resolution of 100ps in normal mode and 1.5625ps in high precision mode. This paper details the design methodology, presents test results for pulse width uncertainty and non-linearity, and showcases achieved period jitter and time interval error jitter as small as around 1ps.

Design of a high-precision clock distribution and synchronization system

In large-scale nuclear and particle physics experiments, there is a high demand for high precision clock distribution and synchronization. In this paper, the design and testing of a high precision clock distribution and synchronization system for the CSR External Target Experiment (CEE) is presented. To achieve high synchronization precision, a dedicated high-quality clock distribution network is designed, while the timestamp synchronization is achieved over the existing trigger link in CEE with a customized protocol in order to simplify the system structure. Automatic metastability elimination and real-time monitoring of both the timestamps on the front end nodes and the clock electronics status are also implemented. The test results indicate that the period jitter of the clock network is better than 4 ps rms, and all the expected functionalities have been achieved successfully.

Using asynchronous optical sampling to measure timing jitter of electro-optic frequency combs

<sec>Electro-optic frequency combs (EOCs) are optical frequency combs constructed by phase modulation of single frequency lasers. The electro-optic modulated optical frequency combs have shown their unique advantages in many application fields due to their high repetition frequencies, high stabilities and other advantages, especially in precision measurement applications. Through accurate dispersion control, the electro-optical frequency combs can output ultra-short pulse laser sequences in the time domain, and their timing jitter characteristic is very important for precision measurement and other applications. This work presents a scheme to measure the timing jitter of the electro-optic combs directly in the time domain based on the principle of dual-comb asynchronous optical sampling method(ASOPS), which relies on temporal cross-correlation between the high repetition rate electro-optic combs and a low repetition rate passively mode-locked fiber laser. The ASOPS process allows timing jitter measurement in a magnified time scale where the timing jitter at a femtosecond level can be received and visualized by standard low speed electronics. We build a theoretical model for timing jitter measurement, conduct a numerical study to verify the model, and also construct an experimental system to characterize the period jitter of a 10-GHz electro-optic comb.</sec><sec>Firstly, the theoretical model for measuring timing jitter is established. In this work, the basic theory of measuring the timing jitter is discussed by analyzing the histogram directly in time domain through using the obtained ASOPS signal. Subsequently, numerical simulations are conducted to simulate the ASOPS process after establishing a sequence of Gaussian pulse train with quantum limited timing jitter. Another pulse train without timing jitter serves as a local oscillator. Through the square law optical detection after sum-frequency generation between LO and LUT, the ASOPS process can be realized and periodic jitter can be obtained directly through histogram statistical analysis. The simulation result is consistent with the theoretical result very well. Finally, an EOC system with cascaded modulators at a repetition rate of 10 GHz is designed and built, and a timing jitter measurement system is designed and built with an all-fiber configuration. The period jitter of 10-GHz EOC is measured by using a 161-MHz mode-locked fiber laser as local oscillator. Histogram analysis shows that the period jitter of the EOC is 3.86 fs.</sec><sec>This measurement technique does not require to use the intricate electrical phase-locked circuits or a high-speed photodetector to receive ultrashort pulses of EOC. Like the eye map analysis method commonly used in telecommunication, the histogram analysis can be used to determine the timing jitter approaching the quantum limit. This approach is easy to set up and operate, and it is anticipated to become a standard method of measuring period jitter of ultrashort pulse with high repetition frequency in a laboratory setting. It will be particularly useful for measuring timing jitters of the sources of novel high repetition rate optical frequency combs, such as micro-resonators and electro-optic frequency combs.</sec>

An Optimized Temperature Compensated Ring Oscillator with Low Power Consumption and Low Variation

In this paper a low power ring oscillator with three differential delay stages and one output buffer stage is designed for Radio Frequency Identification (RFID) applications. The proposed oscillator is designed with neural network model and its parameters are optimized with Teaching–Learning Based Optimization (TLBO) algorithm. The central frequency of the oscillator becomes independent of the temperature with the help of two temperature compensation techniques. In the first technique, the PMOS load transistor of each stage is connected to the NMOS diode connected - in series - transistor. Since these two transistors work in complement of each other, the temperature variation of each stage’s output voltage is decreased. In the second technique, the current variation of oscillator stages versus temperature is reduced since the diode connected transistor is employed in the current source structure. The simulation is done in 0.18 µm Complementary Metal-Oxide Semiconductor (CMOS) technology with the help of Cadence software and the chip area of the layout designed with this software is 19×25 µm2. The designed oscillator exhibits the following parameters: a central frequency of 7.5 MHz, the power dissipation is 238 nW and the frequency deviation is 210 ppm/̊C in the temperature range of 0 to 120ºC, the noise phase and the period jitter are -87.05 dBc/Hz and 0.578 ns (rms), respectively, at 100 KHz offset frequency and 10000 clock cycle.

Screening of Voice Pathologies: Identifying the Predictive Value of Voice Acoustic Parameters for Common Voice Pathologies

Voice acoustic analysis is important for objectively assessing voice production and diagnosing voice disorders. This study aimed to investigate the sensitivity of various voice acoustic parameters in differentiating common voice pathology types. Data from the publicly available Perceptual Voice Qualities Database were analyzed; the database includes recordings of participants with and without voice disorders. A wide range of acoustic parameters was estimated from the recordings, such as alpha ratio, harmonics-to-noise ratio (HNR), cepstral peak prominence smoothed (CPPS), pitch period entropy (PPE), fundamental frequency, jitter, shimmer, and sound pressure levels. The predictive capabilities of the parameters were evaluated using receiver operating characteristic curves. Linear regression analysis determined the associations between parameters and voice disorders. Principal component analysis was conducted to identify important parameters for distinguishing voice disorders. This study has identified significant differences in acoustic parameters between those with and without voice disorders. Notably, the combination of five parameters-namely, PPE, shimmer, jitter, CPPS, and HNR-was identified as a strong predictor in voice disorder screening. These findings contribute substantially to the field of voice disorders, offering valuable insights for screening and diagnosis.

A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming

This Brief presents a process-scaling-friendly frequency-locked-loop (FLL)-based RC oscillator. It features an R-R-C frequency-to-voltage converter that entails resistors with only the same-sign temperature coefficients. Together with a low-leakage switched-capacitor resistor and a delta-sigma-modulator-based trimming, our 71.8-MHz RC oscillator in 28-nm CMOS achieves a frequency inaccuracy of 77.6 ppm/0C, a 0.43%/V supply sensitivity, and an 11-psrms period jitter. The energy efficiency is 368 fJ/cycle.

Design of novel hybrid - digitally controlled oscillator for ADPLL

Digitally Controlled Oscillators (DCOs) are an integral part of All Digital Phase Locked Loops (ADPLLs). It is used to generate output frequency corresponding to the applied digital input. But, due to practical limitations in circuit design, DCOs resolution will be highly limited. Delta Sigma Modulator (DSM) is generally used in DCOs/ADPLLs to obtain a greater resolution. However, using DSM will lead to introduction of frequency spurs in the output spectrum. In this work we propose an alternate method to increase the frequency resolution of DCO without introducing frequency spurs. Novel Hybrid DCO architecture is proposed in this work to increase the resolution. Hybrid DCO proposed in this work has both digital and analog control for tuning frequency. Digital control input of the proposed DCO provides coarse frequency control and the analog control input provides fine frequency control. It has been demonstrated in this work that by integrating Hybrid DCO and DSM with an analog low pass filter (LPF), resolution can be greatly increased, without introducing spurs in the spectrum. As a proof of concept, two Hybrid Digitally controlled Ring Oscillators (DCROs) are designed in 90 nm CMOS process, and their period Jitter performance is compared.

A 20-μs Turn-On Time, 24-kHz Resolution, 1.5–100-MHz Digitally Programmable Temperature-Compensated Clock Generator

A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce delta-sigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the range of 1.5–100 MHz with a resolution of 24-kHz, 140-ps peak-to-peak period jitter, 6.8-ppm/°C inaccuracy, and can be turned on within 20 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> .

Effect of Jitter on Digital Mass Filter Analysis in Higher Stability Zones

Waveform reproducibility is a critical factor for performing high resolution mass analysis with digitally operated quadrupole mass filters and traps operating in higher stability zones. In this work, Hill equation-based stability calculations were used to define the effect of period jitter on mass analysis in higher stability zones. These calculations correlate well with experimental observations in higher stability zones. Comparison of experiment to theory supplies the basis for defining jitter-based expectations and limits for mass analysis in higher zones.

Jitter Detection Method Based on Sequence CMOS Images Captured by Rolling Shutter Mode for High-Resolution Remote Sensing Satellite

Satellite platform jitter is a non-negligible factor that affects the image quality of optical cameras. Considering the limitations of traditional platform jitter detection methods that are based on attitude sensors and remote sensing images, this paper proposed a jitter detection method using sequence CMOS images captured by rolling shutter for high-resolution remote sensing satellite. Through the three main steps of dense matching, relative jitter error analysis, and absolute jitter error modeling using sequence CMOS images, the periodic jitter error on the imaging focal plane of the spaceborne camera was able to be measured accurately. The experiments using three datasets with different jitter frequencies simulated from real remote sensing data were conducted. The experimental results showed that the jitter detection method using sequence CMOS images proposed in this paper can accurately recover the frequency, amplitude, and initial phase information of satellite jitter at 100 Hz, 10 Hz, and 2 Hz. Additionally, the detection accuracy reached 0.02 pixels, which can provide a reliable data basis for remote sensing image jitter error compensation.

Measuring the Performance of FreeRTOS on ESP32 Multi-Core

Real-Time Operating System (RTOS) executing on multi-core architectures still links to a lot of unresolved issues. The article presents potential problems and discusses measurement techniques indicating the performance and determinism. The advantages and disadvantages of individual measurement approaches are discussed, which cover a range from non-invasive techniques to techniques that require the cooperation of a monitored application. On top of that, the parameters indicating the performance and properties of RTOS running on multi-core are defined. Among them, the measuring of the semaphore taking, and task period jitter are described deeply. The operations are measured on ESP32-WROOM-32 development kit equipped with XTENSA dual-core processor running FreeRTOS. The results show unexpectedly high values of the switching context time and jitter when the rescheduling to another core was forced compared to time values measured on single core. Consequently, the unexpected rescheduling to other core increases the execution time of FreeRTOS operations. The work should facilitate the improvement of FreeRTOS implementation when running on multi-core architecture.

A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications

A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate (DDR1)–DDR5 applications is proposed. The proposed architecture combines the advantages of synchronous mirror delay and delay-locked loop (DLL), which can solve the dynamic tracking problem without requiring a long locking time. In addition, the operating range of the aforementioned architecture is extended through harmonic locking detection and autocalibration technologies. For verification, an experimental chip was fabricated using a 90-nm standard CMOS process with a 1-V power supply. The core area occupies 381 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text {m} \times 234\,\,\mu \text{m}$ </tex-math></inline-formula> . The measurement results indicate that the operating range of the proposed ADDLL was from 0.1 to 2.7 GHz, and the peak-to-peak period jitter was less than 5 ps. The output error was less than 1.9%, and the maximum quadrature phase error was 3.61°.

Nonlinear analysis of radio‐frequency quadrature two‐stage ring oscillators

AbstractWe provide a rigorous nonlinear analysis of a large class of radio‐frequency (RF) two‐stage differential ring oscillators. We show that the oscillator's behavior can be recast into the classical Hopf planar dynamical system. Relying on well‐known results for such systems, we give a thorough investigation of the oscillator behavior under noise. We also provide compact analytical expressions for all relevant design measures, offering the designer straightforward guidelines for two‐stage ring oscillators. These expressions predict amplitude, frequency, period jitter, and phase noise very accurately. The formulas are validated for three popular differential delay cells using SPICE simulations.

TESS Observations of Cepheid Stars: First Light Results

Abstract We present the first analysis of Cepheid stars observed by the TESS space mission in Sectors 1–5. Our sample consists of 25 pulsators: ten fundamental mode, three overtone and two double-mode classical Cepheids, plus three type II and seven anomalous Cepheids. The targets were chosen from fields with different stellar densities, both from the Galactic field and from the Magellanic System. Three targets have 2 minutes cadence light curves available by the TESS Science Processing Operations Center: for the rest, we prepared custom light curves from the full-frame images with our own differential photometric FITSH pipeline. Our main goal was to explore the potential and the limitations of TESS concerning the various subtypes of Cepheids. We detected many low-amplitude features: weak modulation, period jitter, and timing variations due to light-time effect. We also report signs of nonradial modes and the first discovery of such a mode in an anomalous Cepheid, the overtone star XZ Cet, which we then confirmed with ground-based multicolor photometric measurements. We prepared a custom photometric solution to minimize saturation effects in the bright fundamental-mode classical Cepheid, β Dor with the lightkurve software, and we revealed strong evidence of cycle-to-cycle variations in the star. In several cases, however, fluctuations in the pulsation could not be distinguished from instrumental effects, such as contamination from nearby sources, which also varies between sectors. Finally, we discuss how precise light-curve shapes will be crucial not only for classification purposes but also to determine physical properties of these stars.

Phase noise limited frequency shift impulsive Raman spectroscopy

We introduce a method to enable optical amplification of a coherent Raman spectroscopy signal, which we call radio frequency (RF) Doppler Raman spectroscopy. In this article, we consider the perturbation of a probe pulse in a sample due to an excited Raman vibrational coherence as a generalized Doppler shift, which connects a time-varying optical path length (the product of the propagation length and refractive index, OPL = n ℓ) with an optical frequency shift. Amplification of a Raman signal outside of the focused interaction is enabled by converting the Doppler frequency shift experienced by a laser probe pulse into a periodic timing jitter. This transit time perturbation is detected through the phase of a RF electronic signal measured at a harmonic of the probe pulse train with a method adapted from precision metrology techniques used to measure laser pulse train timing jitter. Measurement of a timing jitter allows access to much lower noise floors than other coherent Raman techniques, and by exploiting the new capability to scale the signal of a coherent Raman spectroscopic signal, this method opens the potential to detect very weak Raman signals that are currently not observable due to limits of illumination intensity imposed by laser damage to the specimen and noise.

Fiber-Based Clock Synchronization Method for Medical Ultrasound System.

Brain ultrasound has attracted great attention recently due to its noninvasive treatment function for brain diseases. However, ultrasound is still difficult to pass through an intact skull. Phase correction is recognized as an effective method for skull compensation. Half-wavelength pitch transducer is important for the phase correction and, hence, thousands of elements array is required to cover large area human tissue. The clock synchronization between elements is crucial for the phase correction; however, the traditional clock scheme which is designed for 128- or 256-element system is not suitable for thousands of elements. In addition, the clock scheme needs to be magnetic resonance imaging (MRI) compatible since MRI-guided intervention is becoming a routine operation for the brain ultrasound. This study is the first to propose an optical fiber-based clock synchronization method for MRI-guided ultrasound array system. The optical fiber not only distributes the clock but also sets up a link to transmit the data for ultrasound beamformer. The link is full-duplex so both the clock and the data can be transmitted and received simultaneously. The precision of clock synchronization is less than 557 ps when using 50 MHz clock, and the period jitter of the clock is less than 10 ps (rms). Multiple 128- or 256-channel ultrasonic systems can be synchronized, and the error between the channels can be less than 10 ns when using 1-MHz ultrasound transducer. The system can work in an MRI scanning room and communicate with a console via only one fiber. In vivo primate animal study has been achieved, and it has been proven that the proposed clock scheme is suitable for MRI-guided large-scale ultrasound array system.

Stable Subnanosecond Passively Q-Switched Laser End-Pumped by Intense Pulse with Compact Design

We demonstrate a stable compact passively Q-switched laser generating 40 μJ, subnanosecond (< 1 ns) duration, 1064 nm pulses at a repetition rate of 10 kHz. With a composite Nd:YAG/Cr4+:YAG crystal in a simple and compact resonator end-pumped by intense 808 nm pulse, we effectively improve the stability of output laser pulses corresponding to the interpulse amplitude instability less 1% (rms) and the period jitter less 1 μs. These measured pulse-time characteristics agree with numerical simulations and the beam is close to the diffraction limit, with M2 < 1.2. The excellent optical properties and structure make this laser to be an attractive source for high-resolution 3D imaging radars or other widespread applications.

Characterization of On-Foil Sensors and Ultra-Thin Chips for HySiF Integration

The characterization of multiple mechanically flexible passive and active electronic components, namely on-foil temperature sensor, relative humidity sensor, and ultra-thin microcontroller unit (MCU) integrated circuit (IC) is presented. These components are readily available for Hybrid System-in-Foil (HySiF) integration, which combines the merits of the high-performance silicon chips with the large-area electronics. The 60-nm thin-film resistance temperature detector (RTD) is fabricated on different substrates and the extracted temperature coefficient ranges from 0.002 to 0.003( $\Omega/\Omega$ )/°C. Furthermore, the capacitive relative humidity sensor is fabricated by utilizing a polymeric sensing dielectric material that is compatible with those polyimides used in ultra-thin chip embedding. The $1-\mu \text {m}$ thick sensor achieves a fast adsorption rise time of $\text {54 ms}$ and a spontaneous desorption fall time of $\text {750 ms}$ . For flexible ICs packaging and HySiF integration, microcontroller chips are back-thinned to a thickness of about ${30}~\mu \text {m}$ . The characterization of the MCU after the thinning process step showed undegraded performance of the integrated analog-to-digital converter in terms of linearity. However, a drop in the on-chip temperature sensor sensitivity is observed for the thin chips and significant degradation in the period jitter of the high-frequency RC oscillator is measured. Finally, continuity tests are performed to validate the functionality of the ultra-thin MCUs when embedded using the Chip-Film Patch (CFP) flexible package.

A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC

In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance. The proposed ADPLL utilizes a low power and high resolution 3-bit flash TDC with foreground calibration to suppress the issues of process, voltage and temperature (PVT) spreads and achieves low jitter and low power ADPLL. To obtain the fast locking, a proposed dynamic bang-bang PFD is used. The proposed ADPLL takes only 5 iterations to achieve the locking from unlocked state. Additionally, ADPLL employs a wide range and low phase noise voltage controlled oscillator (VCO) based on inverters to obtain a reduced jitter in ADPLL. The proposed ADPLL is designed in 180-nm SCL digital CMOS technology at 1.8 V supply. It consumes a total power of 5.94 mW at 1.8 V. From the post layout simulations, the achieved FoM and periodic jitter is −227.6 dB and 1.71 ps respectively at an output frequency of 1.6 GHz. The achieved phase noise of proposed ADPLL is −131.2 dBc/Hz at offset of 100 MHz.

0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop

This brief presents a quadrature resonant clock generator for driving four 4.3-mm load wires with tuning capacitors and an amplitude control feedback loop. By using frequency tuning capacitors, which reduce the mismatch in operation and LC resonant frequencies, the proposed clock generator offers power reduction by 20-25% compared with conventional CMOS clock driver and by 23-34% compared with conventional CML clock driver over a wide voltage swing. The amplitude control feedback loop, which determines the bias current of the negative gm cell, maintains the constant optimized clock swing over wide PVT variations. Measurement result from the prototype chip fabricated in 65 nm CMOS shows that total power consumption of the proposed quadrature resonant clock is 11.92 mW in 7-GHz operation with four 559-fF load wire capacitances. Measured period jitter is 573.6 fsrms and phase noise at 1MHz offset is -138.37 dBc/Hz.