An Optimized Temperature Compensated Ring Oscillator with Low Power Consumption and Low Variation

Abstract

In this paper a low power ring oscillator with three differential delay stages and one output buffer stage is designed for Radio Frequency Identification (RFID) applications. The proposed oscillator is designed with neural network model and its parameters are optimized with Teaching–Learning Based Optimization (TLBO) algorithm. The central frequency of the oscillator becomes independent of the temperature with the help of two temperature compensation techniques. In the first technique, the PMOS load transistor of each stage is connected to the NMOS diode connected - in series - transistor. Since these two transistors work in complement of each other, the temperature variation of each stage’s output voltage is decreased. In the second technique, the current variation of oscillator stages versus temperature is reduced since the diode connected transistor is employed in the current source structure. The simulation is done in 0.18 µm Complementary Metal-Oxide Semiconductor (CMOS) technology with the help of Cadence software and the chip area of the layout designed with this software is 19×25 µm2. The designed oscillator exhibits the following parameters: a central frequency of 7.5 MHz, the power dissipation is 238 nW and the frequency deviation is 210 ppm/̊C in the temperature range of 0 to 120ºC, the noise phase and the period jitter are -87.05 dBc/Hz and 0.578 ns (rms), respectively, at 100 KHz offset frequency and 10000 clock cycle.