Performance Optimization Techniques Research Articles

Communication optimization for RDMA-based science data transmission tools

Big data has raised new challenges to data communication and transmission capacity. RDMA (Remote Direct Memory Access) Transport Protocol can reduce the communication delay of big data through kernel memory bypass technology and zero-copy technology. This paper introduced RDMA technology for the network performance optimization of BBCP (Babar Copy Program), a big data network file copy tool. Also, transmission queue-oriented Tetris Scheduler algorithm, I/O performance optimization and buffer memory optimization technique were introduced to realize RDMA-based file transfer tool, OBCP (Optimized Babar Copy Program). The experiment results verified that the optimization method could decrease the file transmission time to one-tenth of original BBCP and improve the performance by 50 % compared with related works.

Optimizing Memory Translation Emulation in Full System Emulators

The emulation speed of a full system emulator (FSE) determines its usefulness. This work quantitatively measures where time is spent in QEMU [Bellard 2005], an industrial-strength FSE. The analysis finds that memory emulation is one of the most heavily exercised emulator components. For workloads studied, 38.1% of the emulation time is spent in memory emulation on average, even though QEMU implements a software translation lookaside buffer (STLB) to accelerate dynamic address translation. Despite the amount of time spent in memory emulation, there has been no study on how to further improve its speed. This work analyzes where time is spent in memory emulation and studies the performance impact of a number of STLB optimizations. Although there are several performance optimization techniques for hardware TLBs, this work finds that the trade-offs with an STLB are quite different compared to those with hardware TLBs. As a result, not all hardware TLB performance optimization techniques are applicable to STLBs and vice versa. The evaluated STLB optimizations target STLB lookups, as well as refills, and result in an average emulator performance improvement of 24.4% over the baseline.

Robust Adaptive Beamforming Based on Worst-Case and Norm Constraint

A novel robust adaptive beamforming based on worst-case and norm constraint (RAB-WC-NC) is presented. The proposed beamforming possesses superior robustness against array steering vector (ASV) error with finite snapshots by using the norm constraint and worst-case performance optimization (WCPO) techniques. Simulation results demonstrate the validity and superiority of the proposed algorithm.

Performance Optimisations for a Numerical Solution to a 3D Model of Tumour-Induced Angiogenesis on a Parallel Programming Platform

The challenging issues of cancer prevention and cure lie in the need for a more detailed knowledge of the dynamic processes and mechanisms of cellular behaviour and tumour growth dynamics. In this paper we extend a previous 2D parallel implementation of a continuous-discrete model of tumour-induced angiogenesis to the more realistic 3D case. In particular, we look in-depth at available performance optimisation techniques to further improve the computational method and explore in more detail the hardware architecture. Recent evidence clearly indicates that GPU-accelerated computing can greatly facilitate researchers, clinicians and oncologists by performing time-saving <i>in-silico</i> experiments that have the potential to assist in quantifying cellular parameters, highlight model features, and help explore new cancer treatments and therapies.

Optimising query execution time in LHCb Bookkeeping System using partition pruning and Partition-Wise joins

The LHCb experiment produces a huge amount of data which has associated metadata such as run number, data taking condition (detector status when the data was taken), simulation condition, etc. The data are stored in files, replicated on the Computing Grid around the world. The LHCb Bookkeeping System provides methods for retrieving datasets based on their metadata. The metadata is stored in a hybrid database model, which is a mixture of Relational and Hierarchical database models and is based on the Oracle Relational Database Management System (RDBMS). The database access has to be reliable and fast. In order to achieve a high timing performance, the tables are partitioned and the queries are executed in parallel. When we store large amounts of data the partition pruning is essential for database performance, because it reduces the amount of data retrieved from the disk and optimises the resource utilisation. This research presented here is focusing on the extended composite partitioning strategy such as range-hash partition, partition pruning and usage of the Partition-Wise joins. The system has to serve thousands of queries per minute, the performance and capability of the system is measured when the above performance optimization techniques are used.

PuReMD-GPU: A reactive molecular dynamics simulation package for GPUs

We present an efficient and highly accurate GP-GPU implementation of our community code, PuReMD, for reactive molecular dynamics simulations using the ReaxFF force field. PuReMD and its incorporation into LAMMPS (Reax/C) is used by a large number of research groups worldwide for simulating diverse systems ranging from biomembranes to explosives (RDX) at atomistic level of detail. The sub-femtosecond time-steps associated with ReaxFF strongly motivate significant improvements to per-timestep simulation time through effective use of GPUs. This paper presents, in detail, the design and implementation of PuReMD-GPU, which enables ReaxFF simulations on GPUs, as well as various performance optimization techniques we developed to obtain high performance on state-of-the-art hardware. Comprehensive experiments on model systems (bulk water and amorphous silica) are presented to quantify the performance improvements achieved by PuReMD-GPU and to verify its accuracy. In particular, our experiments show up to 16× improvement in runtime compared to our highly optimized CPU-only single-core ReaxFF implementation. PuReMD-GPU is a unique production code, and is currently available on request from the authors.

Robust Blind Algorithm based on Oblique Projection and Worst-Case Optimization

When adaptive arrays are applied to practical systems, the performance of the convention constant modulus algorithm degrades severely in the presence of array steering vector errors. The similar situation of performance degradation can occur even when the array steering vector is known exactly, but the training sample size is sm all. In this paper, we propose a novel doubly constrained robust constant modulus algorithm based on the worst case performance optimization and oblique projection technique. The proposed algorithm uses explicit modeling of uncertainties in the desired signal array response and in data snapshots, which provides sufficiently robustness to uncertainty in source DOA, and makes the mean output array SINR consistently close to the optimal one. The array weight vector is derived iteratively by the Lagrange multiplier approach and descent gradient technique, in which the factors can be precisely obtained at each step. A theoretical analysis for our propose d algorithm in terms of the optimal step size, convergence and array output SINR performance is presented in this paper. As compared with the linearly constrained constant modulus algorithm, our proposed robust constant modulus algorithm resolves the interference capture problem, has faster convergence speed, and enhances the array output performance under practical situations. Computer simulation results are presented to show the superiority of our proposed algorithm on output SINR enhancement and signal sampling resolution.

Robust Fixed Frequency Invariant Beamformer Design Subject to Norm-Bounded Errors

A novel robust fixed frequency invariant beamformer (FIB) against arbitrary array manifold errors is proposed, by employing the worst-case performance optimization technique with norm-bounded error matrices. A closed-form solution is provided by finding the minimum generalized eigenvector of a pair of matrices. Design examples show that our proposed design significantly outperforms previously proposed FIBs in terms of both frequency invariant property and sidelobe attenuation in the presence of array manifold errors.

A Fast Optimization Method for Reliability and Performance of Cloud Services Composition Application

At present the cloud computing is one of the newest trends of distributed computation, which is propelling another important revolution of software industry. The cloud services composition is one of the key techniques in software development. The optimization for reliability and performance of cloud services composition application, which is a typical stochastic optimization problem, is confronted with severe challenges due to its randomness and long transaction, as well as the characteristics of the cloud computing resources such as openness and dynamic. The traditional reliability and performance optimization techniques, for example, Markov model and state space analysis and so forth, have some defects such as being too time consuming and easy to cause state space explosion and unsatisfied the assumptions of component execution independence. To overcome these defects, we propose a fast optimization method for reliability and performance of cloud services composition application based on universal generating function and genetic algorithm in this paper. At first, a reliability and performance model for cloud service composition application based on the multiple state system theory is presented. Then the reliability and performance definition based on universal generating function is proposed. Based on this, a fast reliability and performance optimization algorithm is presented. In the end, the illustrative examples are given.

Efficient Retiming of Multirate DSP Algorithms

Multirate digital signal processing (DSP) algorithms are often modeled with synchronous dataflow graphs (SDFGs). A lower iteration period implies a faster execution of a DSP algorithm. Retiming is a simple but efficient graph transformation technique for performance optimization, which can decrease the iteration period without affecting functionality. In this paper, we deal with two problems: feasible retiming-retiming a SDFG to meet a given iteration period constraint, and optimal retiming-retiming a SDFG to achieve the smallest iteration period. We present a novel algorithm for feasible retiming and based on that one, a new algorithm for optimal retiming, and prove their correctness. Both methods work directly on SDFGs, without explicitly converting them to their equivalent homogeneous SDFGs. Experimental results show that our methods give a significant improvement compared to the earlier methods.

Comparative Analysis of Global Techniques for Performance and Design Optimization of Launchers

vehicles. Environmental, dynamical, and guidance models for the optimization of ascent trajectories are therefore introduced. Results for seven performance optimization test cases show that global techniques provide comparable payload masses with respect to traditional gradient-based methods. In addition to the trajectory models, historical linear regressions simulating an expendable launch vehicle’s design cycle are described. The focus is in this case on the definition of a simple model as a test bench for the verification of the effectiveness of global methods on multidisciplinary design optimization problems, rather than on the quality of the design results. Three widely different expendable launch vehicle design optimization problems are successfully solved by applying the improved particle swarm optimization algorithm. This demonstrates the suitability of the developed global optimization architecture and algorithms for search-space exploration in multidisciplinary design optimization, paving the way for more detailed modeling and more realistic applications.

Expression Templates Revisited: A Performance Analysis of Current Methodologies

In the last decade, Expression Templates (ET) have gained a reputation as an efficient performance optimization tool for C++ codes. This reputation builds on several ET-based linear algebra frameworks focused on combining both elegant and high-performance C++ code. However, on closer examination the assumption that ETs are a performance optimization technique cannot be maintained. In this paper we demonstrate and explain the inability of current ET-based frameworks to deliver high performance for dense and sparse linear algebra operations, and introduce a new "smart" ET implementation that truly allows the combination of high performance code with the elegance and maintainability of a domain-specific language.

Efficiency Enhancement of Pico-cell Base Station Power Amplifier MMIC in GaN HFET Technology Using the Doherty Technique

1 Abstract With the growth of smart-phones, the demand for more broadband, data-centric technologies are being driven higher. As mobile operators worldwide plan and deploy 4 generation (4G) networks such as LTE to support the relentless growth in mobile data demand, the need for strategically positioned pico-sized cellular base stations known as ‘pico-cells’ are gaining traction. In addition to having to design a transceiver in a much compact footprint, pico-cells must still face the technical challenges presented by the new 4G systems, such as reduced power consumptions and linear amplification of the signals. The RF power amplifier (PA) that amplifies the output signals of 4G pico-cell systems face challenges to minimize size, achieve high average efficiencies and broader bandwidths while maintaining linearity and operating at higher frequencies. 4G standards as LTE use nonconstant envelope modulation techniques with high peak to average ratios. Power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to reduce power consumption, a design of a high efficiency PA that can maintain the efficiency for a wider range of radio frequency signals is required. The primary focus of this thesis is to enhance the efficiency of a compact RF amplifier suitable for a 4G pico-cell base station. For this aim, an integrated two way Doherty amplifier design in a compact 10x11.5mm monolithic microwave integrated circuit using GaN device technology is presented. Using non-linear GaN HFETs models, the design achieves high efficiencies of over 50% at both back-off and peak power regions without compromising on the stringent linearity requirements of 4G LTE standards. This demonstrates a 17% increase in power added efficiency at 6 dB back off from peak power compared to conventional Class AB amplifier performance. Performance optimization techniques to select between high efficiency and high linearity operation are also presented. Overall, this thesis demonstrates the feasibility of an integrated HFET Doherty amplifier for LTE band 7 which entails the frequencies from 2.62-2.69GHz. The realization of the layout and various issues related to the PA design is discussed and attempted to be solved.

On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI Systems

Leading-edge VLSI systems, essentially multiprocessor systems-on-chip, have a wide range of components integrated together and operating in unison. They can be analyzed as flow networks in which the system performance depends on the bandwidth, transmission time, and queueing delay characteristics of the individual components, their connectivity and interactions, as well as the traffic patterns they encounter. The flow in various parts of the system must ideally be distributed so as to extract the maximum throughput possible with minimum end-to-end delays. Such an ideal distribution for flow networks has previously been obtained using simple electrical circuits. We demonstrate a similar methodology for typical VLSI systems and provide the necessary extensions of the theory. We empirically validate the methodology using a cycle-accurate simulation model as the reference. We find this methodology to supply better distributions in the average case and comparable distributions in the worst case as compared to standard search procedures such as random sampling and simulated annealing. The real strength is that it provides a speedup of several orders of magnitude, i.e., 3-5 orders in our experiments. Thus it is an elegant means for analyzing and optimizing the flow in VLSI systems, which can easily be incorporated into design procedures, compilers and on-chip modules for real-time allocations.

Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm

In this article, we propose a novel floorplanning algorithm for GPUs. Floorplanning is an inherently sequential algorithm, far from the typical programs suitable for Single-Instruction Multiple-Thread (SIMT)-style concurrency in a GPU. We propose a fundamentally different approach of exploring the floorplan solution space, where we evaluate concurrent moves on a given floorplan. We illustrate several performance optimization techniques for this algorithm in GPUs. To improve the solution quality, we present a comprehensive exploration of the design space, including various techniques to adapt the annealing approach in a GPU. Compared to the sequential algorithm, our techniques achieve 6--188X speedup for a range of MCNC and GSRC benchmarks, while delivering comparable or better solution quality.

GPU computing in medical physics: A review

The graphics processing unit (GPU) has emerged as a competitive platform for computing massively parallel problems. Many computing applications in medical physics can be formulated as data-parallel tasks that exploit the capabilities of the GPU for reducing processing times. The authors review the basic principles of GPU computing as well as the main performance optimization techniques, and survey existing applications in three areas of medical physics, namely image reconstruction, dose calculation and treatment plan optimization, and image processing.

Parallel implementation and optimization of the Sebvhos algorithm

In this paper, a parallel Surface Extraction from Binary Volumes with Higher-Order Smoothness (SEBVHOS) algorithm is proposed to accelerate the SEBVHOS execution. The original SEBVHOS algorithm is parallelized first, and then several performance optimization techniques which are loop optimization, cache optimization, false sharing optimization, synchronization overhead optimization, and thread affinity optimization, are used to improve the implementation’s performance on multi-core systems. The performance of the parallel SEBVHOS algorithm is analyzed on a dual-core system. The experimental results show that the parallel SEBVHOS algorithm achieves an average of 1.86x speedup. More importantly, our method does not come with additional aliasing artifacts, comparing to the original SEBVHOS algorithm.

Landing stencil code on Godson-T

The advent of multi-core/many-core chip technology offers both an extraordinary opportunity and a profound challenge. In particular, computer architects and system software designers are faced with a unique opportunity to introducing new architecture features as well as adequate compiler technology -- together they may have profound impact. This paper presents a case study (using the 1-D Jacobi computation) of compiler-amendable performance optimization techniques on a many-core architecture Godson-T. Godson-T architecture has several unique features that are chosen for this study: 1) chip-level global addressable memory in particular the scratchpad memories (SPM) local to the processing cores; 2) fine-grain memory based synchronization (e.g., full-empty bit for fine-grain synchronization). Leveraging state-of-the-art performance optimization methods for 1-D stencil parallelization (e.g., timed tiling and variants), we developed and implement a number of many-core-based optimization for Godson-T. Our experimental study shows good performance in both execution time speedup and scalability, validate the value of globally accessed SPM and fine-grain synchronization mechanism (full-empty bits) under the Godson-T, and provides some useful guidelines for future compiler technology of many-core chip architectures.

STATCOM Control Reconfiguration Technique for Steady State and Dynamic Performance Optimization during Network Fault Conditions

The introduction of flexible AC transmission/distribution system (FACTS) in a power system is to improve the stability, reduce the losses, and also improve the loadability of the network system. Herein, the proposed work is a non-traditional optimization technique which has been adopted to optimize the various process control parameters that contribute notably to control STATCOM device operations in a power system network during any undesired condition. The simulation was performed by taking into consideration STATCOM process control parameters; hereby the controller was also configured in strategic ways to optimize the control model under both steady state and dynamic performances. The optimization process results have clearly indicated that the introduction of STATCOM device in the right location of the system increases the loadability and sustainability of the power system through optimization process. The new control can thus be effectively used for this type of optimization process.

A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures

Recently coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their efficiency and flexibility. While many CGRAs have demonstrated impressive performance improvements, the effectiveness of CGRA platforms ultimately hinges on the compiler. Existing CGRA compilers do not model the details of the CGRA, and thus they are i) unable to map applications, even though a mapping exists, and ii) using too many processing elements (PEs) to map an application. In this paper, we model several CGRA details, e.g., irregular CGRA topologies, shared resources and routing PEs in our compiler and develop a graph drawing based approach, split-push kernel mapping (SPKM), for mapping applications onto CGRAs. On randomly generated graphs our technique can map on average 4.5times more applications than the previous approach, while generating mappings which have better qualities in terms of utilized CGRA resources. Utilizing fewer resources is directly translated into increased opportunities for novel power and performance optimization techniques. Our technique shows less power consumption in 71 cases and shorter execution cycles in 66 cases out of 100 synthetic applications, with minimum mapping time overhead. We observe similar results on a suite of benchmarks collected from Livermore loops, Mediabench, Multimedia, Wavelet and DSPStone benchmarks. SPKM is not a customized algorithm only for a specific CGRA template, and it is demonstrated by exploring various PE interconnection topologies and shared resource configurations with SPKM.