Transistor Performance Research Articles

Umklapp electron-electron scattering in bilayer graphene moiré superlattice

Recent experimental advances have been marked by the observations of ballistic electron transport in moir\'e superlattices in highly aligned heterostructures of graphene and hexagonal boron nitride (hBN). Here, we predict that a high-quality graphene bilayer aligned with an hBN substrate features ${T}^{2}$-dependent resistivity caused by umklapp electron-electron (Uee) scattering from the moir\'e superlattice, that is, a momentum kick by Bragg scattering experienced by a pair of electrons. Substantial Uee scattering appears upon $p$ doping of the bilayer above a characteristic threshold, and its contribution towards the resistivity grows rapidly with hole density, until it reaches a peak value, then falling off by an order of magnitude. This rapid, nonmonotonic dependence of resistivity, in the density range where the system is otherwise highly conductive, suggests the possibility of a nonconventional field-effect transistor operation. We also analyze the influence of an electrostatically induced interlayer asymmetry (and the associated band gap) in the bilayer and trigonal warping on the electron-electron umklapp scattering.

Theoretical Investigation of Dual-Material Stacked Gate Oxide-Source Dielectric Pocket TFET Based on Interface Trap Charges and Temperature Variations

In this paper, the performance of dual-material stacked gate oxide-source dielectric pocket-tunnel field-effect transistor (DMSGO-SDP-TFET) has been investigated by considering fixed interface trap charges (ITCs) at the Si–SiO2 interface. During the analysis, both types of trap charges, positive (donor) and negative (acceptor), have been considered to investigate their effect on the DC, analog/ radio frequency, linearity and harmonic distortion performance parameters in terms of the carrier concentration, electric field, band-to-band tunneling rate, transfer characteristics, transconductance ([Formula: see text]), unity gain frequency ([Formula: see text]), gain–bandwidth product, device efficiency ([Formula: see text]/[Formula: see text]), transconductance frequency product, transit time ([Formula: see text]), second- and third-order transconductance and voltage intercept points ([Formula: see text], [Formula: see text], VIP2 and VIP3), third-order Input Intercept Point and Intermodulation Distortion (IIP3, IMD3), second-, third-order and total harmonic distortions (HD2, HD3 and THD), respectively. Further, the impact of temperature variations from [Formula: see text][Formula: see text]K to [Formula: see text][Formula: see text]K in the presence of ITCs is investigated and the results are compared with conventional DMSGO-TFET. In terms of percentage variation, DMSGO-SDP-TFET depicts lower variation than conventional DMSGO-TFET, indicating that the proposed device is more immune to trap charges and can be used for energy-efficient, high-frequency and linearity applications at elevated temperatures.

High-Performance Thin-Film Transistors with ZnO:H/ZnO Double Active Layers Fabricated at Room Temperature.

H doping can enhance the performance of ZnO thin-film transistors (TFTs) to a certain extent, and the design of double active layers is an effective way to further improve a device's performance. However, there are few studies on the combination of these two strategies. We fabricated TFTs with ZnO:H (4 nm)/ZnO (20 nm) double active layers by magnetron sputtering at room temperature, and studied the effect of the hydrogen flow ratio on the devices' performance. ZnO:H/ZnO-TFT has the best overall performance when H2/(Ar + H2) = 0.13% with a mobility of 12.10 cm2/Vs, an on/off current ratio of 2.32 × 107, a subthreshold swing of 0.67 V/Dec, and a threshold voltage of 1.68 V, which is significantly better than the performance of single active layer ZnO:H-TFTs. This exhibits that the transport mechanism of carriers in double active layer devices is more complicated. On one hand, increasing the hydrogen flow ratio can more effectively suppress the oxygen-related defect states, thus reducing the carrier scattering and increasing the carrier concentration. On the other hand, the energy band analysis shows that electrons accumulate at the interface of the ZnO layer close to the ZnO:H layer, providing an additional path for carrier transport. Our research exhibits that the combination of a simple hydrogen doping process and double active layer construction can achieve the fabrication of high-performance ZnO-based TFTs, and that the whole room temperature process also provides important reference value for the subsequent development of flexible devices.

Performance of piezoelectric semiconductor bipolar junction transistors and the tuning mechanism by mechanical loadings

A coupling model is established on piezoelectric semiconductor bipolar junction transistors (PS-BJT) subjected to mechanical loadings by abandoning depletion layer approximation and low injection assumption. Effect of base region on device performance and interaction between emitter/base junction (E/B) and base/collector junction (B/C) are investigated. It is found that too small a base width will cause B/C to extract electrons directly from emitter region, implying that an electron passageway will be excited to link from collector- to emitter-region by striding over base-region (abbreviated as “EP-CE” hereafter). We particularly clarify that the current produced by electrons flowing across EP-CE is independent of electron-hole recombination in E/B, which means that this current has not yet been bestowed on the information of base current. “Information of base current” refers to dispatching information of base current on the electrons in emitter region. Thus, a current from EP-EC cannot be reckoned in the amplification effect of base current. Our investigations show that base width should not be designed too small to avoid EP-CE, which has not been revealed before. As regards to tuning PS-BJT performance by mechanical loadings, we revealed the mechanism as follows: 1) raising electron-hole recombination rate inside E/B to reduce resistivity such that more electrons can be driven from emitter- to base-region; 2) elevating electron conductivity in base-region for easier pass of electrons; 3) promoting attractive ability of B/C on electrons such that more electrons cross the interface. Numerical results show that transmission characteristics can be greatly increased as expected by mechanical tuning.

Enhanced Organic Electrochemical Transistor Performance of Donor-Acceptor Conjugated Polymers Modified with Hybrid Glycol/Ionic Side Chains by Postpolymerization Modification.

Emergent bioelectronic technologies are underpinned by the organic electrochemical transistor (OECT), which employs an electrolyte medium to modulate the conductivity of its organic semiconductor channel. Here we utilize postpolymerization modification (PPM) on a conjugated polymer backbone to directly introduce glycolated or anionic side chains via fluoride displacement. The resulting polymers demonstrated increased volumetric capacitances, with subdued swelling, compared to their parent polymer in p-type enhancement mode OECTs. This increase in capacitance was attributed to their modified side chain configurations enabling cationic charge compensation for thin film electrochemical oxidation, as deduced from electrochemical quartz crystal microbalance measurements. An overall improvement in OECT performance was recorded for the hybrid glycol/ionic polymer compared to the parent, owing to its low swelling and bimodal crystalline orientation as imaged by grazing-incidence wide-angle X-ray scattering, enabling its high charge mobility at 1.02 cm2·V-1·s-1. Compromised device performance was recorded for the fully glycolated derivative compared to the parent, which was linked to its limited face-on stacking, which hindered OECT charge mobility at 0.26 cm2·V-1·s-1, despite its high capacitance. These results highlight the effectiveness of anionic side chain attachment by PPM as a means of increasing the volumetric capacitance of p-type conjugated polymers for OECTs, while retaining solid-state macromolecular properties that facilitate hole transport.

Aqueous electrolyte-gated solution-processed metal oxide transistors for direct cellular interfaces.

Biocompatible field-effect-transistor-based biosensors have drawn attention for the development of next-generation human-friendly electronics. High-performance electronic devices must achieve low-voltage operation, long-term operational stability, and biocompatibility. Herein, we propose an electrolyte-gated thin-film transistor made of large-area solution-processed indium-gallium-zinc oxide (IGZO) semiconductors capable of directly interacting with live cells at physiological conditions. The fabricated transistors exhibit good electrical performance operating under sub-0.5 V conditions with high on-/off-current ratios (>107) and transconductance (>1.0 mS) over an extended operational lifetime. Furthermore, we verified the biocompatibility of the IGZO surface to various types of mammalian cells in terms of cell viability, proliferation, morphology, and drug responsiveness. Finally, the prolonged stable operation of electrolyte-gated transistor devices directly integrated with live cells provides the proof-of-concept for solution-processed metal oxide material-based direct cellular interfaces.

Ti3 C2 Tx MXene van der Waals gate contact for GaN high electron mobility transistors.

Gate controllability is a key factor that determines the performance of GaN high electron mobility transistors (HEMTs). However, at traditional metal-GaN interface, direct chemical interaction between metal and GaN can result in fixed charges and traps, which can significantly deteriorate the gate controllability. In this study, Ti3 C2 Tx MXene films were integrated into GaN HEMTs as the gate contact, wherein van der Waals heterojunctions were formed between MXene films and GaN without direct chemical bonding. The GaN HEMTs with enhanced gate controllability exhibited an extremely low off-state current (IOFF ) of 10-7 mA/mm, a record high ION /IOFF current ratio of ∼1013 (which is six orders of magnitude higher than conventional Ni/Au contact), a high off-state drain breakdown voltage of 1085V, and a near-ideal subthreshold swing of 61mV/dec. This work shows the great potential of MXene films as gate electrodes in wide-bandgap semiconductor devices. This article is protected by copyright. All rights reserved.

High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma-Enhanced Atomic Layer Deposition

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In0.84Ga0.16O or In0.75Zn0.25O), and a barrier layer (BL) (Ga2O3) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μFE) with band-like transport, steep gate swing (SS), and positive threshold voltage (VTH) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In0.75Zn0.25O/Ga2O3 NL TFT showed remarkable electrical performance: μFE of 77.1 ± 0.67 cm2/(V s), VTH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and ION/OFF of 8.9 × 109 with a low operation voltage range of ≤2 V and excellent stabilities (ΔVTH of +0.27, -0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

High‐Resolution Lithography for High‐Frequency Organic Thin‐Film Transistors

AbstractOrganic thin‐film transistors are field‐effect transistors comprising a semiconductor in the form of a thin, typically polycrystalline layer of conjugated organic molecules. Since organic transistors can often be fabricated at temperatures no higher than about 100 °C, they are potentially useful for flexible, large‐area electronics applications. An important performance parameter of organic transistors is the transit frequency, which is the highest frequency at which the transistors can be operated. The transit frequency of organic transistors is determined in large part by the channel length and the parasitic gate‐to‐source and gate‐to‐drain overlap lengths. How small these dimensions can be made depends (at least in the case of transistors fabricated in the lateral device architecture) greatly on the resolution of the lithography method that is utilized for the patterning of the gate electrodes and the source and drain contacts. Patterning methods that have yielded organic transistors with lateral dimensions sufficiently small to provide transit frequencies above 10 MHz include photolithography, laser lithography, stencil lithography, and electron‐beam lithography. In this review, these four lithography methods and their roles in the fabrication of high‐frequency organic transistors, as well as their prospects for future improvements in the dynamic performance of organic transistors, will be illuminated.

High density polarization-induced 2D hole gas enabled by elevating Al composition in GaN/AlGaN heterostructures

A two-dimensional hole gas (2DHG) induced by polarization charges at the GaN/AlGaN hetero-interface is attracting much attention because of its potential to develop p-channel transistors required for GaN complementary logic integrated circuits. This platform is compatible with commercial AlGaN/GaN n-channel electronics, but the performance of GaN p-channel transistors has been far behind. In this work, 2DHGs in GaN/AlGaN/GaN heterostructures grown by plasma-assisted molecular beam epitaxy have been investigated. The Al composition of the AlGaN barrier has been pushed as high as possible without obvious strain relaxation, and the record high 2DHG sheet density and conductivity on the GaN/AlGaN/GaN platform have been obtained. By adopting a parallel conduction model, a dependent relationship of the 2DHG density on temperature has been extracted. The temperature dependent Hall-effect results have demonstrated that the 2DHG density boosts by 75 times and 46 times at room temperature and 77 K, respectively, when the Al composition is pushed from 0.18 to 0.45 for the AlGaN barriers. The 2DHG sheet density reaches 3.6 × 1013 and 2.1 × 1013 cm−2 at room temperature and 77 K, respectively, and the lowest sheet resistance is 8.9 kΩ/□ at 77 K. Such a 2DHG is beneficial for fabrication of p-channel GaN transistors with lower on-resistance on the already-industrialized platform.

Effects of Sn Doping on the Electrical Performance and Stability of Sub-V Operating Metal-Oxide Thin-Film Transistors Fabricated by Oxygen Annealing

The incorporation of Sn into a sol-gel-based indium-gallium-zinc oxide (IGZO) channel layer is investigated to improve the electrical characteristics and operational stability of amorphous metal-oxide thin-film transistors (oxide-TFTs). Sub-V operating Sn-doped IGZO-TFTs (IGZTO-TFTs) fabricated by solution-process under a high-pressure oxygen-enriched (O2) atmosphere exhibit significantly improved electrical properties such as a high linear field-effect mobility (11.5 cm2 V−1 s−1), high on/off ratio (up to 108), and low subthreshold swing (0.10 V/dec). The activation energy and density of states are determined to perform comparative analysis on the charge transport characteristics of the IGZTO-TFTs. Under both prolonged positive and negative bias illumination stresses, large shifts in threshold voltages of the IGZO-TFTs are reduced significantly after Sn doping. The suppressed formation of oxygen-related defect states affects the electrical characteristics and operational stability. This is verified by determining the proportional ratio of metal-oxygen bonding states in the O2-annealed IGZTO films.

Temperature effects on the performance of ferroelectric FET with random grain phase variation for non-volatile memory application

We report the temperature effects on the performance of ferroelectric field-effect transistor (FeFET)-based non-volatile memory (NVM) considering random grain phase variation in the ferroelectric layer through simulation. Based on the FE temperature effect model that accounts for both the transistor and ferroelectric degradation, we demonstrate that: (1) at a certain temperature, the memory window (MW) decreases with pronounced effect on low threshold voltage shift and its variation increases as the FE phase decreases; (2) with the temperature increases, the MW decreases with pronounced effect on high threshold voltage shift. The random grain phase variation further exacerbates the MW distribution, thus degrading the sensing margin. These results may provide insights for device design of high-performance FeFET-based NVMs.

RESEARCH THE ACCURACY OF MODELING POWER LOSSES IN POWER DIODES AND TRANSISTORS

The methodology for modeling static and dynamic power losses in power IGBT and MOSFET transistors in the Matlab and Multisim software environments is given. It is shown that when modeling switching processes in power transistors, Matlab / Simulink does not allow determining the dynamic components of power losses, namely, the energy of turning on the transistor, the energy of turning off the transistor, as well as the recovery energy of power diodes. At the same time, the simulation of static power losses of power diodes and transistors in Matlab/Simulink is carried out with a significant error due to incorrect representation of the current-voltage characteristics. It is shown that for a more correct and accurate simulation of the operation of power transistors, including power losses in power switches, it is more appropriate to conduct simulations in the Multisim software environment, which takes into account more than 47 parameters during simulation, including temperature characteristics, parasitic input and output capacitances and inductances, nonlinearities of current-voltage characteristics and others. In Multisim, a circuit of a half-bridge inverter with power MOSFETs controlled by the IR2104PBF driver has been developed. It is shown that the switching of power transistors is significantly influenced by the parameters of the driver microcircuit, namely the size of the storage capacitor of the driver, as well as the value of the active resistance of the gate resistor. It is shown that the simulation in Multisim correctly displays the transient processes of turning on and off power transistors and reverse recovery of diodes, which allows determining the dynamic losses of power transistors and power diodes.

Chirality-dependent electrical transport properties of carbon nanotubes obtained by experimental measurement

Establishing the relationship between the electrical transport properties of single-wall carbon nanotubes (SWCNTs) and their structures is critical for the design of high-performance SWCNT-based electronic and optoelectronic devices. Here, we systematically investigated the effect of the chiral structures of SWCNTs on their electrical transport properties by measuring the performance of thin-film transistors constructed by eleven distinct (n, m) single-chirality SWCNT films. The results show that, even for SWCNTs with the same diameters but different chiral angles, the difference in the on-state current or carrier mobility could reach an order of magnitude. Further analysis indicates that the electrical transport properties of SWCNTs have strong type and family dependence. With increasing chiral angle for the same-family SWCNTs, Type I SWCNTs exhibit increasing on-state current and mobility, while Type II SWCNTs show the reverse trend. The differences in the electrical properties of the same-family SWCNTs with different chiralities can be attributed to their different electronic band structures, which determine the contact barrier between electrodes and SWCNTs, intrinsic resistance and intertube contact resistance. Our present findings provide an important physical basis for performance optimization and application expansion of SWCNT-based devices.

The impact of multi-layered dielectrics on the electrical performance of ZnO thin-film transistors

The electrical performance of ZnO thin film transistors (TFTs) fabricated on three different dielectric layers is investigated using an inverted staggered bottom gate thin film transistor structure. This work demonstrated the potential of integrating high-k dielectrics in ZnO TFTs in a dielectric multi-layered stack using SiO2 as the support layer for all the hero-dielectrics layers. In order to achieve this, ZnO thin film semiconducting layers were deposited at room temperature by radio frequency (RF) sputtering method and with no post deposition heat treatment, making them suitable candidates for low cost large area electronics on low temperature substrates (such as plastics). The dielectric films investigated were aluminium nitride (AlN), silicon nitride (SiN) and silicon dioxide (SiO2). The effective mobility of SiN devices was about half that observed in AlN devices. However, the dielectric layers exhibited hysteresis of approximately 0 V, 2 V and 7 V for the SiO2, AlN and SiN respectively. In addition, SiO2 TFTs have lowest threshold voltage (VT) and turn-on voltage (Von). The capacitance-voltage measurement for these device show that the flatband and threshold voltage of SiN and AlN MOS capacitors shifted towards more negative voltages instead when compared with the single layer SiO2 devices.

Full Control of Solid-State Electrolytes for Electrostatic Gating.

Ionic gating is a powerful technique to realize field-effect transistors (FETs) enabling experiments not possible otherwise. So far, ionic gating has relied on the use of top electrolyte gates, which pose experimental constraints and make device fabrication complex. Promising results obtained recently in FETs based on solid-state electrolytes remain plagued by spurious phenomena of unknown origin, preventing proper transistor operation, and causing limited control and reproducibility. Here, a class of solid-state electrolytes for gating (Lithium-ion conducting glass-ceramics, LICGCs) is explored, the processes responsible for the spurious phenomena and irreproducible behavior are identified, and properly functioning transistors exhibiting high density ambipolar operation with gate capacitance of ≈ (depending on the polarity of the accumulated charges) are demonstrated. Using 2D semiconducting transition-metal dichalcogenides, the ability to implement ionic-gate spectroscopy to determine the semiconducting bandgap, and to accumulate electron densities above 1014 cm-2 are demostrated, resulting in gate-induced superconductivity in MoS2 multilayers. As LICGCs are implemented in a back-gate configuration, they leave the surface of the material exposed, enabling the use of surface-sensitive techniques (such as scanning tunneling microscopy and photoemission spectroscopy) impossible so far in ionic-gated devices. They also allow double ionic gated devices providing independent control of charge density and electricfield.

Modulation of Grain Boundary conductance of nanocrystalline SnO[formula omitted] film by electrostatically induced carriers

Grain boundary (GB) conductance of a channel has an immense effect on the device performance of a field effect transistor (FET) fabricated by chemical routes. Here, we report the modulation of intra and inter grain conductance of the channel of SnO2 based FET device by varying electrostatic carrier induction using a polymer gate dielectric. The channel was found highly resistive in the absence of any gate bias, but the channel current (IDS) increased nearly twenty times when VG = 14 V was applied. The threshold gate voltage (VTh) to turn on the channel was measured as low as 2.2 V. Analysis of the experimental results using a suitable theoretical model revealed that the induced carriers (by field effect) play a crucial role to tune the intra grain as well as GB conductance of the FET channel and thus modulating the overall conductance of the FET channel more effectively.

Organic Solvent Free Synthesis and Processing of Semiconducting Polymers for Field Effect Transistors in Waterborne Dispersions

AbstractConjugated semiconducting polymers are key active materials for printable electronics, sensors and biosensors, organic photovoltaics, organic light emitting devices, and more. The research in the field developed very efficient materials and sound structure property relationships, thus making a case for a transition from laboratory to industrial environment. At this critical juncture, sustainability, and ease of scaling up are at least as important as performances, to the point that efficient materials on a lab scale could become unpractical for the industry. The development of more efficient synthetic protocols and the complete removal of all organic solvents from both the synthesis and the processing of semiconducting polymers can help tremendously to improve sustainability and reduce costs. It is shown that the use of an aqueous dispersion of the food grade surfactant lecithin as the medium, enables the synthesis and processing of the representative semiconducting alternating copolymer poly (9,9‐dioctylfluorene‐alt‐bithiophene) (PF8T2) in high yield and high quality and with transistor performances comparable with those obtained with reference materials synthetized and processed from volatile organic solvents.

Modification of Two-Dimensional Tin-Based Perovskites by Pentanoic Acid for Improved Performance of Field-Effect Transistors.

Understanding and controlling the nucleation and crystallization in solution-processed perovskite thin films are critical to achieving high in-plane charge carrier transport in field-effect transistors (FETs). This work demonstrates a simple and effective additive engineering strategy using pentanoic acid (PA). Here, PA is introduced to both modulate the crystallization process and improve the charge carrier transport in 2D 2-thiopheneethylammonium tin iodide ((TEA)2 SnI4 ) perovskite FETs. It is revealed that the carboxylic group of PA is strongly coordinated to the spacer cation TEAI and [SnI6 ]4- framework in the perovskite precursor solution, inducing heterogeneous nucleation and lowering undesired oxidation of Sn2+ during the film formation. These factors contribute to a reduced defect density and improved film morphology, including lower surface roughness and larger grain size, resulting in overall enhanced transistor performance. The reduced defect density and decreased ion migration lead to a higher p-channel charge carrier mobility of 0.7 cm2 V-1 s-1 , which is more than a threefold increase compared with the control device. Temperature-dependent charge transport studies demonstrate a mobility of 2.3 cm2 V-1 s-1 at 100 K due to the diminished ion mobility at low temperatures. This result illustrates that the additive strategy bears great potential to realize high-performance Sn-based perovskite FETs.

Innovative design and optimized performance of thermoelectric transistor driven by the Seebeck effect

The combination of thermoelectricity and the transistor technology is a promising choice to obtain the high performance of thermoelectric (TE) materials and devices. In this context, the performance optimization always depends on the modulation of the external voltage. TE materials can produce their own voltages by the Seebeck effect, making them possible to form the transistor circuit without additional power sources. Here, the generic operation condition of TE transistor is demonstrated theoretically, considering temperature dependence in Bi2Te3-based materials. Further, the transistor is constructed as a TE generator. And a Direct-Current (DC) equivalent circuit method is introduced to analyze the performance of TE transistor. The method produces an optimized design to attain maximum output power and conversion efficiency. Calculation results show that the maximum output power is 17.8mW and the conversion efficiency is 8.69% at room temperature when the temperature difference is 50 K.