Performance Of Phase-locked Loop Research Articles

Phase-Locked Loop Based on an Observer for Grid Synchronization

A grid synchronization technique is essential for grid-connected power converters. Phase-locked loop (PLL) has been widely exploited as an implementation technique, but additional efforts are required to deal with severely distorted grid voltages. In this paper, an observer is proposed to enhance the performance of PLL. A state equation is newly formulated to construct the observer, which extracts positive-sequence voltage from the distorted grid voltage. Additionally, guidelines are suggested to set the observer gains by considering its internal transfer functions. The PLL and proposed observer have been tested in simulations and experiments in contrast to dual second-order generalized integrator frequency-locked loop. The results have shown that the proposed method reveals a better phase-tracking performance for grid synchronization.

Moving Average Filter Based Phase-Locked Loops: Performance Analysis and Design Guidelines

The phase-locked loops (PLLs) are probably the most widely used synchronization technique in grid-connected applications. The main challenge that is associated with the PLLs is how to precisely and fast estimate the phase and frequency, when the grid voltage is unbalanced and/or distorted. To overcome this challenge, incorporating moving average filter(s) (MAF) into the PLL structure has been proposed in some recent literature. An MAF is a linear-phase finite-impulse-response filter, which can act as an ideal low-pass filter, if certain conditions hold. The main aim of this paper is to present the control design guidelines for a typical MAF-based PLL. The paper starts with the general description of MAFs. The main challenge associated with using the MAFs is then explained, and its possible solutions are discussed. The paper then proceeds with a brief overview of the different MAF-based PLLs. In each case, the PLL block diagram description is shown, the advantages and limitations are briefly discussed, and the tuning approach (if available) is evaluated. The paper then presents two systematic methods to design the control parameters of a typical MAF-based PLL: one for the case of using a proportional-integral (PI) type loop filter (LF) in the PLL, and the other for the case of using a proportional-integral-derivative (PID) type LF. Finally, the paper compares the performance of a well-tuned MAF-based PLL when using the PI-type LF with the results of using the PID-type LF, which provides useful insights into their capabilities and limitations.

The Performance of a New Hybrid PLL in an Interconnected Renewable Energy Systems under Fault Ride Through Operation

Modern renewable energy systems (RES) require fault ride through (FRT) operation in order to provide voltage and frequency support to the power grid when faults occur. The grid synchronization of a RES could be ensured by the appropriate operation of a phase-locked loop (PLL). A new hybrid PLL (dαβPLL) has recently been suggested by the authors and could operate accurately and faster than the other existing PLLs. The dαβPLL could be a very useful tool in the FRT operation of a RES, since the faster performance of the new PLL could boost the time performance of the FRT algorithm when a disturbance occurs. This paper investigates the performance of the flexible positive and negative sequence control (FPNSC) when the new dαβPLL is used. The paper also deals with the improvement on the FRT operation of the RES that could be obtained from the outstanding performance of the dαβPLL.

Advantages and Challenges of a Type-3 PLL

A phase-locked loop (PLL) is a closed-loop feedback control system, which synchronizes its output signal in frequency as well as in phase with an input signal. The phase detector, the loop filter, and the voltage controlled oscillator are the key parts of almost all PLLs. Within the areas of power electronics and power systems, which are focused on in this paper, the PLLs typically employ a proportional-integral controller as the loop filter, resulting in a type-2 control system (a control system of type-N has N poles at the origin in its open-loop transfer function). Recently, some attempts have been made to design type-3 PLLs, either by employing a specific second-order controller as the loop filter, or by implementing two parallel tracking paths for the PLL. For this type of PLLs, however, the advantages and limitations are not clear at all, as the results reported in different literature are contradictory, and there is no detailed knowledge about their stability and dynamic characteristics. In this paper, different approaches to realize a type-3 PLL are examined first. Then, a detailed study of dynamics and analysis of stability, followed by comprehensive parameters design guidelines for a typical type-3 PLL are presented. Finally, to get insight into the advantages/limitations of this type of PLLs, the performance of a well-tuned type-3 PLL is compared with a conventional synchronous reference frame PLL (which is a type-2 PLL) through extensive experimental results and some theoretical discussions.

Analysis of the PLL phase error in presence of simulated ionospheric scintillation events

The functioning of standard phase locked loops (PLL), including those used to track radio signals from Global Navigation Satellite Systems (GNSS), is based on a linear approximation which holds in presence of small phase errors. Such an approximation represents a reasonable assumption in most of the propagation channels. However, in presence of a fading channel the phase error may become large, making the linear approximation no longer valid. The PLL is then expected to operate in a non‐linear regime. As PLLs are generally designed and expected to operate in their linear regime, whenever the non‐linear regime comes into play, they will experience a serious limitation in their capability to track the corresponding signals. The phase error and the performance of a typical PLL embedded into a commercial multiconstellation GNSS receiver were analyzed in presence of simulated ionospheric scintillation. Large phase errors occurred during scintillation‐induced signal fluctuations although cycle slips only occurred during the signal re‐acquisition after a loss of lock. Losses of lock occurred whenever the signal faded below the minimumC/N0threshold allowed for tracking. The simulations were performed for different signals (GPS L1C/A, GPS L2C, GPS L5 and Galileo L1). L5 and L2C proved to be weaker than L1. It appeared evident that the conditions driving the PLL phase error in the specific case of GPS receivers in presence of scintillation‐induced signal perturbations need to be evaluated in terms of the combination of the minimumC/N0 tracking threshold, lock detector thresholds, possible cycle slips in the tracking PLL and accuracy of the observables (i.e. the error propagation onto the observables stage).

Methodology for comparing two carrier phase tracking techniques

The carrier phase tracking loop is the primary focus of the current work. In particular, two carrier phase tracking techniques are compared, the standard phase tracking loop, i.e., the phase lock loop (PLL), and the extended Kalman filter (EKF) tracking loop. In order to compare these two different techniques and taking into consideration the different models adopted in each, it is important to bring them to one common ground. In order to accomplish this, the equivalent PLL for a given EKF has to be determined in terms of steady-state response to both thermal noise and signal dynamics. A novel method for experimentally calculating the equivalent bandwidth of the EKF is presented and used to evaluate the performance of the equivalent PLL. Results are shown for both the L1 and L5 signals. Even though the two loops are designed to track equivalent dynamics and to have equivalent carrier phase standard deviations, the EKF outperforms the equivalent PLL in terms of both the transient response and sensitivity.

Design and Analysis of Second and Third Order PLL at 450MHz

Designing of an analog circuit satisfying the design constraints for desired application is a challenging job. Phase Lock Loop (PLL) is an important analog circuit used in various communication applications such as frequency synthesizer, radio, computer, clock generation, clock recovery, global positioning system, etc. Since all these applications are operating at different frequency, satisfying design constraints for PLL with respect to type of PLL operating frequency, Bandwidth, Settling time and other parameters is an critical and time consuming issue. In this paper, selection and design for Second order and third order PLL suggested using MATLAB, Simulink as a simulation tool. The simulated results for the design PLL at 450 MHz indicates good accuracy when the behavior model is compared with the mathematical model. Finally the performance of PLL is tested and calculated for parameters like lock time, lock range, Bandwidth.

The Magnetic Resonator Piano: Electronic Augmentation of an Acoustic Grand Piano

This paper presents the magnetic resonator piano, a hybrid acoustic-electronic instrument extending the traditional grand piano. Sound is produced without loudspeakers using electromagnetic actuators to directly manipulate the piano strings, expanding its vocabulary to include infinite sustain, notes that crescendo from silence, harmonics, and a variety of timbres. A feedback-based approach senses string vibrations from a single pickup on the soundboard, using filters and phase-locked loops to generate signals which reinforce the natural motion of each string. Signal-routing hardware enables coverage of all 88 notes of the piano using a standard digital audio interface. This paper describes the hardware, software, and performing interface of the instrument and presents measurements of amplitude, frequency response, and phase-locked loop performance. Sounds generated by the actuators achieve similar amplitudes to the traditional piano, and while they cannot replicate the rapid attack produced by a piano hammer, they complement the percussive nature of the piano by enabling continuous legato control of amplitude, frequency, and timbre.

Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology

In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.

電離層シンチレーションの影響下におけるGPS受信機の性能評価

Ionospheric scintillation induces a rapid change in the amplitude and phase of radio wave signals. This is due to irregularities of electron density in the F-region of the ionosphere. It reduces the accuracy of both pseudorange and carrier phase measurements in GPS/Satellite Based Augmentation System (SBAS) receivers and can cause loss of lock on the satellite signal. Scintillation is not strong at mid-latitude regions, but severe effects occur mainly in a band approximately 15-degree latitude on either side of the magnetic equator and sometimes in the polar and auroral regions. Most scintillation occurs for a few hours after sunset during the peak years of the solar cycle. In Japan, several ionospheric scintillations were observed by Electronic Navigation Research Institute (ENRI). This work intended to investigate the scintillation characteristics in Japan and statistically evaluate constant bandwidth phase locked loop (PLL) and a Fast Adaptive Bandwidth (FAB) PLL performance under the ionospheric scintillation condition. The results show that the characteristics are consistent with the models proposed in early studies and the FAB PLL has the flexibility against the scintillation effects compared with the constant PLL.

52 Gb/s 161 transmitter in 0.13 [micro sign]m SiGe BiCMOS technology

A52-Gb/s 16:1 quarter-rate clocking transmitter for high-speed serial data transmission is designed to utilise 0.13-mum SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The quarter-rate transmitter consists of a 16:1 multiplexer (MUX), a voltage-controlled ring oscillator, a phase-locked loop (PLL), a pseudorandom data generator and an output amplifier. The voltage-controlled ring oscillator has a wide tuning range from 11 to 22 GHz with feedforward loop and delay interpolation. A continuous model of a third-order PLL is developed and used to optimise loop filter parameters and to estimate the PLL performance in a simulation. The PLL achieves a low phase noise of -124.6 dBc/Hz at 1 MHz offset. The 16:1 MUX features quarter-rate clock multiplexing with multi-phase voltage-controlled oscillator clocks. In the design of a 16:1 MUX, an edge-channelling 4:1 MUX is used to alleviate a duty cycle and a jitter problem.

All-pole phase-locked loops: calculating lock-in range by using Evan's root-locus

The dynamics of a phase-locked loop (PLL), an essential component for the electronic synchronization processes, is described by an ordinary nonlinear differential equation with an order equal to 1 plus the order of its internal linear low-pass filter. Literature contains several results mainly concerned to the second-order loops giving expressions for lock-in range and transient response specifying a linear equivalent second-order system. However, in some applications, more accurate transient responses are necessary and the PLL performance can be improved by considering the higher-order filters resulting in the nonlinear loops with order greater than 2. Such systems, due to high order and nonlinear terms, depending on the parameters combination can present some undesirable behaviors, resulting from bifurcations, as error oscillation and chaos, decreasing the synchronization ranges. Implication to engineering design is that some regions of the parameter space become forbidden limiting the circuit options. This work is a contribution on establishing the lock-in range for a PLL of generic order n + 1, considering that the filter is all-pole linear stable low-pass of order n. Analysis is performed by detecting a Hopf bifurcation on the synchronous state by using the root-locus method combined with the dynamical system theory. The lock-in range is calculated by applying the classical control tools defining an equivalent feedback control system.

Digital ready TV platform with synchronization shaping circuit

This paper proposes an improved digital ready TV platform that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL (phase-locked loop) of an ADC (analog to digital converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization shaping technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, i.e. the timing of the signal falling edge remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

Vehicular speed response PLL using square‐law circuits

AbstractIn this paper, we propose using a square‐law loop circuit that does not require a pilot signal in a vehicular speed response phase‐locked loop (PLL) and study its performance. In the PLL performance in the fading transmission path in mobile communications, a vehicular speed response PLL improves the PLL performance by using a directional antenna to lengthen the fading period and by providing frequency offset information generated in response to the vehicular speed to the PLL. Compared with a PLL using a conventional square‐law circuit, the proposed scheme effectively uses the cancellation effect of the frequency offset and the loop gain adaptation based on the vehicular speed response to obtain substantial improvement in the bit error rate. A substantial improvement is exhibited, particularly in an environment having a high fDT. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 85(8): 22–29, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.1109

The effect of Doppler shift/spread on the performance of the phased locked loop for phase coherent underwater acoustic communications

Phase coherent acoustic communication systems, which employ joint adaptive channel equalization and phase-locking synchronization, have been shown to yield a much higher symbol rate (e.g., 1–2 kb/s at 2–5 kHz) by successfully tracking and updating time varying acoustic channels dominated by multipath components. While the decision feedback equalizer (DSE) can in principle adapt to the change of both the signal amplitude and phase, the adaptation rate (requiring typically 20–30 symbols) is in practice too slow compared with the phase rate, hence an additional phase locked loop (PLL) is required. However, the PLL has its limitations. It is found in data analysis that the failure of the PLL is responsible for the high bit error rate (BER) for many situations. This paper illustrates the effect of the phase shift/fluctuations (emulating the Doppler shift/spread) on the performance of PLL and BER, keeping the channel impulse response fixed in time. It is shown with at-sea data that the BER is significantly reduced by removing the phase wander after precise Doppler estimation. The residue phase is apparently below the tolerance threshold as determined by simulations. [Work supported by ONR.]

Studies on the performance of phase-locked loops incorporating modified loop filters

The behaviour of a phase-locked loop (PLL) is highly dependent on the structure of the loop filter. In the present paper, the filter structure has been modified by incorporating a high-pass filter connected in parallel to the conventional low-pass filter. Numerical results show that a proper choice of design parameters of the filters can enhance the transient response of a PLL as well as improve its noise rejection capability in some specific cases. The filter modification algorithm has been verified by means of a software experiment using MAT-LAB, and through a hardware experiment.

Effects of CW interference on phase-locked loop performance

This paper focuses on the modeling and analysis of phase-locked loops in the presence of continuous wave (CW) interference such that the operating vulnerability to CW jamming and interference can be accessed. The loop phase error is characterized, and the conditions under which the loop remains locked in frequency to the desired carrier are presented. Analysis is conducted for arbitrary offsets of carrier and interferer signal frequencies relative to the quiescent voltage-controlled oscillator (VCO) frequency. The results show that loop performance depends not only on the frequency difference between the desired signal and interferer, but also on the frequency offset between the quiescent VCO oscillation and desired carrier. The vulnerability of the loop to the presence of interference increases if interferer and desired signal spectral locations are in opposite sides of quiescent VCO frequency.

Transient response of Colpitts-VCO and its effect on performance of PLL system

In this paper, we investigate the frequency step response of the Colpitts-voltage-controlled oscillator (VCO) by solving its third-order circuit state equation. The result shows that after the capacitance change, its oscillation frequency changes to its steady state value with vibration. We also establish a more accurate transfer function of the Colpitts-VCO by considering its transient response with the assumption that the change of the capacitance is small. Moreover, we also introduce the idea of VCO time constants which represent a degree of the transient response of the VCO. Finally, to evaluate how the transient response of VCO influences on performance of phase-locked loops (PLL's), we investigate acquisition processes of PLL model using our new transfer function. In the high-speed PLL, transient response of the VCO affects acquisition performance. There might be the case where response of the acquisition changes to its steady state with vibration, even in case where there is only overshoot in conventional analysis with conventional idealized VCO model.

Quality evaluation of random numbers generated by chaotic sampling phase-locked loops

The quality of generated random numbers is determined by the independence of consecutive numbers from one another. If the random numbers are used for enciphering plain text then correlation or periodicity destroys the security of the transmission. Chaotic signals are claimed to be suitable for secure communications; however, the quality of the generated sequences has not yet been studied. Physical changes in the parameters of the chaotic circuits used to generate random numbers may alter the parameters determining the chaotic behavior, i.e., the quality of the generated random numbers. This paper evaluates the quality of random sequences generated by chaotic sampling phase-locked loops (PLLs). It shows that micro-Feigenbaum diagrams, i.e., small periodic windows, can be observed in the chaotic PLLs proposed for random number generation. The run test, a much more sensitive tool than the autocorrelation function, is used to evaluate the quality of the random numbers. Because the results have shown that the quality of the generated numbers does not meet the requirements, a simple method is proposed to improve the performance of the chaotic PLLs.

Decision-directed PLL for coherent optical pulse CDMA systems in the presence of multiuser interference, laser phase noise, and shot noise

A digital decision-directed phase-locked loop (PLL) for use in optical pulse code-division multiple-access (CDMA) systems based on coherent correlation demodulation is proposed. PLL performance is affected by multiuser interference, laser phase noise and optical shot noise. The effect of these sources of interference and noise on PLL performance is evaluated based on a nonlinear model (the Fokker-Planck method) since a linear analysis yields large deviations between the analytical results and actual performance at low signal-to-noise ratios (SNRs). After describing the implementation of the PLL, the steady-state probability density function (pdf) of the phase estimator is derived. Numerical evaluation of the variance of the phase estimator is given for Gold codes. The linewidth requirements of the laser for an acceptable phase estimator variance and the value of the optimal loop bandwidth minimizing the impact of the interference and noise on the PLL are discussed.