NoC Performance Research Articles

On designing an efficient numerical-based forbidden pattern free crosstalk avoidance codec for reliable data transfer of NoCs

Inter-wire coupling capacitances can lead to crosstalk fault that is strongly dependent on the transition patterns appearing on the wires. These transition patterns can cause mutual influences between adjacent wires of NoCs and as a result threaten the reliability of data transfer seriously. To increase the reliability of NoCs against the crosstalk fault, Forbidden Pattern Free (FPFs) codes are used. To generate FPF codes, numerical systems are among the overhead-efficient mechanisms. The algorithms of numerical systems have direct effect on the amounts of the codec overheads including power consumption, area occupation and performance of NoCs. To find an overhead-efficient numerical system, this paper proposes an Algorithm for Generating FPF Numerical systems (AGFN). AGFN can provide a tradeoff for designers in selecting overhead-efficient FPF numerical systems. Using this algorithm, collection of Fibonacci-based and non-Fibonacci-based numerical systems can be generated. Then, using AGFN, non-Fibonacci-based FPF numerical system called Summation-based-Subtracted-Added-Penultimate (S2AP) is generated. Experimental results indicate that S2AP not only reduces the worst crosstalk effects by completely removing the Triplet Opposite Direction (TOD) transitions, but also it can significantly improve power consumption, area occupation and critical path overheads of codec with respect to the other state-of-the-art FPF codes.

Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation

Recently, Through-Silicon-Via (TSV) has been more popular to provide faster inter-layer communication in three-dimensional Networks-on-Chip (3D NoCs). However, the area overhead of TSVs reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs such as homogeneous 3D NoCs topologies. Also, 3D routers require more memory and thus they are more power hungry than conventional 2D routers. Alternatively, hybrid 3D NoCs combine both the area and performance benefits of 2D and 3D router architectures by using a limited number of TSVs. Existing hybrid architectures suffer from higher packet delays as they do not consider the dynamic communication patterns of different application and their NoC resource usage. We propose a novel algorithm to systematically generate hybrid 3D NoC topologies for a given application such that the vertical connections are minimized while the NoC performance is not sacrificed. The proposed algorithm analyses the target application and generates hybrid architectures by efficiently redistributing the vertical links and buffer spaces based on their utilizations. Furthermore, the algorithm has been evaluated with synthetic and various real-world traffic patterns. Experimental results show that the proposed algorithm generates optimized architectures with lower energy consumption and a significant reduction in packet delay compared to the existing solutions.

CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs

Router's buffer design and management strongly influence energy, area and performance of on-chip networks, hence it is crucial to encompass all of these aspects in the design process. At the same time, the NoC design cannot disregard preventing network-level and protocol-level deadlocks by devoting ad-hoc buffer resources to that purpose. In chip multiprocessor systems the coherence protocol usually requires different virtual networks (VNETs) to avoid deadlocks. Moreover, VNET utilization is highly unbalanced and there is no way to share buffers between them due to the need to isolate different traffic types. This paper proposes CUTBUF , a novel NoC router architecture to dynamically assign virtual channels (VCs) to VNETs depending on the actual VNETs load to significantly reduce the number of physical buffers in routers, thus saving area and power without decreasing NoC performance. Moreover, CUTBUF allows to reuse the same buffer for different traffic types while ensuring that the optimized NoC is deadlock-free both at network and protocol level. In this perspective, all the VCs are considered spare queues not statically assigned to a specific VNET and the coherence protocol only imposes a minimum number of queues to be implemented. Synthetic applications as well as real benchmarks have been used to validate CUTBUF , considering architectures ranging from 16 up to 48 cores. Moreover, a complete RTL router has been designed to explore area and power overheads. Results highlight how CUTBUF can reduce router buffers up to 33 percent with 2 percent of performance degradation, a 5 percent of operating frequency decrease and area and power saving up to 30.6 and 30.7 percent, respectively. Conversely, the flexibility of the proposed architecture improves by 23.8 percent the performance of the baseline NoC router when the same number of buffers is used.

The Performance of NoCs for Very Large Manycore Systems under Locality-based Traffic

The scaling of semiconductor technologies is leading to processors with increasing numbers of cores. A key enabler in manycore systems is the use of Networks-on-Chip (NoC) as a global communication mechanism. The adoption of NoCs in manycore systems requires a shift in focus from computation to communication, as communication is fast becoming the dominant factor in processor performance. In large manycore systems, performance is predicated on the locality of communication. In this work, we investigate the performance of three NoC topologies for systems with thousands of processor cores under two types of localised traffic models. We present latency and throughput results comparing fat quadtree, concentrated mesh and mesh topologies under different degrees of localisation. Our results, obtained using a modified version of the HNOCS NoC simulator and based on the ITRS physical data for 2023, show that the type of locality traffic and the degree of localisation significantly affects the NoC performance, and that scale-invariant topologies perform worse than flat topologies.

Characterization and modeling of multicast communication in cache-coherent manycore processors

The scalability of Network-on-Chip (NoC) designs has become a rising concern as we enter the manycore era. Multicast support represents a particular yet relevant case within this context, mainly due to the poor performance of NoCs in the presence of this type of traffic. Multicast techniques are typically evaluated using synthetic traffic or within a full system, which is either simplistic or costly, given the lack of realistic traffic models that distinguish between unicast and multicast flows. To bridge this gap, this paper presents a trace-based multicast traffic characterization, which explores the scaling trends of aspects such as the multicast intensity or the spatiotemporal injection distribution for different coherence schemes. This analysis is the basis upon which the concept of multicast source prediction is proposed, and upon which a multicast traffic model is built. Both aspects pave the way for the development and accurate evaluation of advanced NoCs in the context of manycore computing.

A New CDMA Encoding/Decoding Method for on-Chip Communication Network

As a high performance on-chip communication method, the code division multiple access (CDMA) technique has recently been applied to networks on chip (NoCs). We propose a new standard-basis-based encoding/decoding method to leverage the performance and cost of CDMA NoCs in area, power assumption, and network throughput. In the transmitter module, source data from different senders are separately encoded with an orthogonal code of a standard basis and these coded data are mixed together by an XOR operation. Then, the sums of data can be transmitted to their destinations through the on-chip communication infrastructure. In the receiver module, a sequence of chips is retrieved by taking an AND operation between the sums of data and the corresponding orthogonal code. After a simple accumulation of these chips, original data can be reconstructed. We implement our encoding/decoding method and apply it to a CDMA NoC with a star topology. Compared with the state-of-the-art Walsh-code-based (WB) encoding/decoding technique, our method achieves up to 67.46% power saving and 81.24% area saving together with decrease of 30%–50% encoding/decoding latency. Moreover, the CDMA NoC with different sizes applying our encoding/decoding method gains power saving, area saving, and maximal throughput improvement up to 20.25%, 22.91%, and 103.26%, respectively, than the WB CDMA NoC.

Hierarchical approach for hybrid wireless Network-on-chip in many-core era

Due to high latency and high power consumption in long hops between operational cores of Network-on-Chips (NoCs), the performance of such architectures has been limited. Billions of transistors available on a single chip present opportunities for new levels of computing capability. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless NoC has been emerged. Employing wireless communication links between cores, wireless NoC has reasonably increased the performance of NoC. However, wireless transceivers along with associated antenna impose considerable area and power overheads in wireless NoCs. Thus, in this paper, we introduce a hybrid wireless NoC called Hierarchical Wireless-based Architecture (HiWA) to use the wireless resources optimally. In the proposed approach the network is divided into subnets where intra-subnet nodes communicate through wire links while inter-subnet communications are handled almost by single-hop wireless links. Simulation results show that HiWA efficiently reduces power consumption by 39% in comparison with a traditional wireless NoC, called WiNoC, while still achieves 16% lower packet latency than conventional NoC.

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multi-core revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due to the cores, since the NoC contribution to the overall energy budget is relevant. To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly dynamic voltage frequency scaling (DVFS) and power gating. Typically, simulation-based tools are employed to explore the huge design space by adopting simplified models of the components. As a consequence, the majority of state-of-the-art on NoC power-performance optimization do not accurately consider timing and power overheads of actuators, or (even worse) do not consider them at all, with the risk of overestimating the benefits of the proposed methodologies. This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC. It integrates accurate power gating and DVFS models encompassing also their timing and power overheads. The value added of our proposal is manyfold: (i) DVFS and power gating actuators are modeled starting from SPICE-level simulations; (ii) such models have been integrated in the simulation environment; (iii) policy analysis support is plugged into the framework to enable assessment of different policies; (iv) a flexible GALS ( globally asynchronous locally synchronous ) support is provided, covering both handshake and FIFO re-synchronization schemas. To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article.

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs

As one of the main trends of communication technology for 3D integrated circuits, the 3D networks-on-chip (NoCs) have drawn high concern from the academia. The links are main components of the NoCs. For the permanent link faults, the fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of the 2D NoCs. In this paper, we propose a low-overhead fault-tolerant routing scheme called LOFT for 3D Mesh NoCs without requiring any virtual channels (VCs). LOFT is a deadlock-free scheme by adopting a logic-based routing named LBDRe2 guided by a turn model Complete-OE. The experimental results show that LOFT possesses better performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing schemes.

FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels

In this paper, we explore optimizing the bandwidth utilization of the network-on-chips (NoCs). We propose a flit-level speedup scheme to improve the NoC performance using self-reconfigurable bidirectional channels. For the NoC intrarouter bandwidth, in addition to allowing flits from different packets to use the idle internal bandwidth of the crossbar, our proposed flit-level speedup scheme also allows flits within the same packet to be transmitted simultaneously. For interrouter channels, a distributed channel configuration scheme is developed to dynamically change the link directions. In this way, the effective bandwidth between two routers can change adaptively depending on the run time network traffic. We present the implementation of the proposed flit-level speedup NoC on a 2-D mesh. An input buffer architecture, which supports reading and writing two flits from the same virtual channel at the same time, is proposed. The switch allocator is also designed to support flit-level parallel arbitration. Extensive simulations on both the synthetic traffic and real applications show performance improvement in throughput and latency over the existing architectures using bidirectional channels.

The Impact of Traffic Localisation on the Performance of NoCs for Very Large Manycore Systems

The scaling of semiconductor technologies is leading to processors with increasing numbers of cores. The adoption of Networks-on-Chip (NoC) in manycore systems requires a shift in focus from computation to communication, as communication is fast becoming the dominant factor in processor performance. In large manycore systems, performance is predicated on the locality of communication. In this work, we investigate the performance of three NoC topologies for systems with thousands of processor cores under two types of localised traffic. We present latency and throughput results comparing fat quadtree, concentrated mesh and mesh topologies under different degrees of localisation. Our results, based on the ITRS physical data for 2023, show that the type and degree of localisation of traffic significantly affects the NoC performance, and that scale-invariant topologies perform worse than flat topologies.

An Empirical Evaluation of Topologies for Large Scale NoC

In the past decades, processing power has achieved considerable gains. Researchers proposed faster uniprocessors that are capable of improving the instruction level parallelism through out-of-order implementation for increasing the performance quality of the existing network-on-chip (NoC). Although, the reducing returns of the performance of uniprocessor architecture caused multiprocessors to be integrated on a chip. In this paper, we selected a famous popular NoC topology, i.e., mesh, and evaluated it in terms of different figures of merit e.g., latency, power consumption, and power/throughput ratio under different routing algorithms, number of buffer, and hotspot traffic models. We selected two size of NoC, 12×12 and 16×16, as large scale NoC. We investigated all characteristics and measured latency, maximum delay, and total energy by Noxim simulator. In this paper, we demonstrated that when the network size and number of buffer were large, no routing algorithm could contribute to improve network performance. This is because the routing algorithms had the same performance in the large scale NoCs and they could not solve problems alone. Therefore, for a large scale system, the topology has a major impact on the performance and cost of the network. http://dx.doi.org/10.11591/telkomnika.v12i12.6840

Statically adaptive multi FIFO buffer architecture for network on chip

In this paper, we present the architecture of a simple input-port that utilizes a static but adaptive Virtual Channel (VC) mechanism. In our approach, the flits of one packet can interleave with the other flits of different packets in a channel and a single buffer by using a rotating flit-by-flit arbitration. The routing path of each flit can be guaranteed because the flits belonging to a packet are attached with an ID tag at each router. Then these flits become differentiable at downstream routers. These tagged interleaved flit-by-flit flow of packet can be controlled and stored in a single memory buffer at different specific area called VC. We further develop the control part of single memory to give an adaptive property to the VCs of a channel. Our approach prevents the monopoly of channel’s buffer by a VC because of the static nature of VCs. Moreover, the adaptive nature of our approach lets the VCs allocate different size of buffers according to traffic demand. Overall, our Statically Adaptive Multi FIFO (SAMF) approach improves the NoC performance metrics such as throughput, latency and buffer utilization by employing an efficient hardware overhead as compared to a conventional static VC mechanism.

Probabilistic odd–even: an adaptive wormhole routing algorithm for 2D mesh network-on-chip

Wormhole routing is a popular routing technique used in network-on-chip. It is efficient but susceptible to deadlock, while deadlock will significantly degrade the network performance of NoC. Most existing adaptive wormhole routings avoid deadlock by reducing the degree of adaptiveness and thus sacrificing network performance. In this paper, we address both deadlock and network performance issues jointly, and propose a probabilistic odd---even (POE) routing algorithm that achieves the minimum packet delivery delay. The proposed POE dynamically adjusts the probabilities of constrained turns that may lead to deadlocks according to the current network conditions, and uses an efficient deadlock detection and recovery scheme when a deadlock happens. By adopting constrained turns adaptively to the network status, it not only reduces the frequency of deadlock and allows the network to be swiftly recovered when it occurs, but also greatly improves the degree of adaptiveness to obtain high network performance. Experimental results show that our method achieves a significant performance improvement both in terms of network throughput and average packet latency compared with the existing methods such as XY, odd---even, abacus turn model and fully adaptive routing algorithm while it only has moderate energy consumption.

Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip

Traditional metal-wire-based networks-on-chip (NoC) suffer from high latency and power dissipation as the system size scales up in the number of cores. This limitation stems from the inherent multihop communication nature of larger NoCs. It has previously been shown that the performance of NoCs can be significantly improved by introducing long-range, low power, and high-bandwidth single-hop links between distant cores. While previous work has focused on specific NoC architectures and configurations, it remains an open question whether heterogeneous link types are beneficial in a broad range of NoC architectures. In this article, we show that a generic NoC architecture with heterogeneous link types allows for NoCs with higher bandwidth at a lower cost compared to homogeneous networks. We further show that such NoCs scale up significantly better in terms of performance and cost. We demonstrate these broadly-applicable results by using a technology-agnostic complex network approach that targets NoC architectures with various emerging link types.

Silicon-based all-optical multi microring network-on-chip

An optical multi microring network-on-chip (MMR NoC) is proposed and evaluated through numerical simulations. The network architecture consists of a central resonating microring with local microrings connected to the input/output ports. A mathematical model based on the transfer matrix method is used to assess the MMR NoC performance and to analyze the fabrication tolerances. Results show that the proposed architecture exhibits a limited coherent crosstalk with a bandwidth suitable for 10 Gb/s signals, and it is robust to coupling ratio variations and ring radii fabrication inaccuracies.

Effective Task Scheduling and IP Mapping Algorithm for Heterogeneous NoC-Based MPSoC

Quality of task scheduling is critical to define the network communication efficiency and the performance of the entire NoC- (Network-on-Chip-) based MPSoC (multiprocessor System-on-Chip). In this paper, the NoC-based MPSoC design process is favorably divided into two steps, that is, scheduling subtasks to processing elements (PEs) of appropriate type and quantity and then mapping these PEs onto the switching nodes of NoC topology. When the task model is improved so that it reflects better the real intertask relations, optimized particle swarm optimization (PSO) is utilized to achieve the first step with expected less task running and transfer cost as well as the least task execution time. By referring to the topology of NoC and the resultant communication diagram of the first step, the second step is done with the minimal expected network transmission delay as well as less resource consumption and even power consumption. The comparative experiments have shown the preferable resource and power consumption of the algorithm when it is actually adopted in a system design.

Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance

Virtual channels (VC) and multiple physical (MP) networks are two alternative methods to provide better performance, support quality-of-service, and avoid protocol deadlocks in packet-switched network-on-chip design. Since contention can be dynamically resolved, VCs give lower zero-load packet latency than MPs; however, MPs can be built with simpler routers and narrower channels, which improves the target clock frequency, power dissipation, and area occupation. In this paper, we present a comprehensive comparative analysis of these two design approaches, including an analytical model, synthesis-based designs with both FPGAs and standard-cell libraries, and system-level simulations. The result of our analysis shows that one solution does not outperform the other in all the tested scenarios. Instead, each approach has its own specific strengths and weaknesses. Hence, we identify the scenarios where each method is best suited to achieve high performance, very low power dissipation, and increased design flexibility.

Packet triggered prediction based task migration for network-on-chip

The development of IC technology makes Network-on-Chip (NoC) an attractive architecture for future massive parallel systems. Task migration optimize the overall communication performance of NoCs since the changing phases of execution make static task mapping insufficient. It is well-known that the communication behavior of many applications are predictable, which makes it feasible to use prediction to guide task migration. The triggering of activating a task migration is also important. In this paper, we first defined and analyzed predictabilities of applications, and then compared different ways of triggering for migration. We then modified the Genetic Algorithm (GA) based task remapping and proposed two other task migration algorithms: Simple Exchange (SE) and Benefit Assess (BA). A mechanism called node lock is also used to reduce unnecessary and costly migrations. Simulation results on real applications from PARSEC benchmark suites show that the SE, BA and GA algorithms can reduce 21.4%, 34.0% and 34.9% of number of hops, and 17.3%, 27.2% and 26.3% in terms of average latency respectively, compared with the system without task migration; BA and SE reduce 72.0% and 78.7% of migrations without significant performance degradation compared with GA, and the node lock mechanism can further remove 37.3% and 46.0% of migrations while achieving almost the same performance.

Analytical performance modeling of shuffle–exchange inspired mesh-based Network-on-Chips

This paper proposes and evaluates a shuffle–exchange as an efficient alternative to the popular mesh topology for Network-on-Chips (NoCs). Although the proposed topology imposes the cost equal to that of the mesh topology, the proposed topology (1) provides lower diameter for NoC, (2) offers better performance under uniform, hotspot, and matrix-transpose traffic patterns and (3) consumes lower energy for packet delivery. To speed up the evaluation process of the proposed topology, an analytical performance model is proposed in the paper to predict the performance of NoCs. The model uses a network of M/G/1 queues to consider channels of the NoC. In this way, the model accurately estimates the average message latency which is a widely used representative for the network performance. Results obtained from the analytical model are in good agreement with those of simulations for a wide range of working conditions (e.g. various network sizes, different message lengths, and different traffic patterns). The proposed analytical model provides a minimum of 400% speed-up in the evaluation process of the proposed topology.