Performance Of Multiprocessors Research Articles

Multiprocessor Performance Measurement and Evaluation [Book Reviews

Multiprocessor Performance Measurement and Evaluation [Book Reviews

Efficient shared memory with minimal hardware support

Shared memory is widely regarded as a more intuitive model than message passing for the development of parallel programs. A shared memory model can be provided by hardware, software, or some combination of both. One of the most important problems to be solved in shared memory environments is that of cache coherence. Experience indicates, unsurprisingly, that hardware-coherent multiprocessors greatly outperform distributed shared-memory (DSM) emulations on message-passing hardware. Intermediate options, however, have received considerably less attention. We argue in this position paper that one such option---a multiprocessor or network that provides a global physical address space in which processors can make non-coherent accesses to remote memory without trapping into the kernel or interrupting remote processors---can provide most of the performance of hardware cache coherence at little more monetary or design cost than traditional DSM systems. To support this claim we have developed the Cashmere family of software coherence protocols for NCC-NUMA (Non-Cache-Coherent, Non-Uniform-Memory Access) systems, and have used execution-driven simulation to compare the performance of these protocols to that of full hardware coherence and distributed shared memory emulation. We have found that for a large class of applications the performance of NCC-NUMA multiprocessors rivals that of fully hardware-coherent designs, and significantly surpasses the performance realized on more traditional DSM systems.

Boosting the performance of hybrid snooping cache protocols

Previous studies of bus-based shared-memory multiprocessors have shown hybrid write-invalidate/write-update snooping protocols to be incapable of providing consistent performance improvements over write-invalidate protocols. In this paper, we analyze the deficiencies of hybrid snooping protocols under release consistency, and show how these deficiencies can be dramatically reduced by using write caches and read snarfing.Our performance evaluation is based on program-driven simulation and a set of five scientific applications with different sharing behaviors including migratory sharing as well us producer-consumer sharing. We show that a hybrid protocol, extended with write caches as well as read snarfing, manages to reduce the number of coherence misses by between 83% and 95% as compared to a write-invalidate protocol for all five applications in this study. In addition, the number of bus transactions is reduced by between 36% and 60% for four of the applications and by 9% for the fifth application. Because of the small implementation cost of the hybrid protocol and the two extensions, we believe that this combination is an effective approach to boost the performance of bus-based multiprocessors.

A Lazy Scheduling Scheme for Hypercube Computers

Processor allocation and job scheduling are two complementary techniques for improving the performance of multiprocessors. It has been observed that all the hypercube allocation policies with the FCFS scheduling provide only incremental performance improvement. A greater impact on the performance can be obtained by efficient job scheduling. This paper presents an effort in that direction by introducing a new scheduling algorithm called lazy scheduling for hypercubes, The motivation of this scheme is to eliminate the limitations of the FCFS scheduling. This is done by maintaining separate queues for different job sizes and delaying the allocation of a job if any other job(s) of the same dimension is(are) running in the system. Processor allocation is done using the buddy strategy. The scheduling and allocation complexity is O( n) for an n-cube. Simulation studies show that the performance is dramatically enhanced by using the lazy scheduling scheme as compared to the FCFS scheduling. Comparison with a recently proposed scheme called scan indicates that the lazy scheme performs better than the scan scheduling under a wide range of workloads.

A trace-driven simulator for performance evaluation of cache-based multiprocessor systems

We describe a simulator which emulates the activity of a shared memory, common bus multiprocessor system with private caches. Both kernel and user program activities are considered, thus allowing an accurate analysis and evaluation of coherence protocol performance. The simulator can generate synthetic traces, based on a wide set of input parameters which specify processor, kernel and workload features. Other parameters allow us to detail the multiprocessor architecture for which the analysis has to be carried out. An actual-trace-driven simulation is possible, too, in order to evaluate the performance of a specific multiprocessor with respect to a given workload, if traces concerning this workload are available. In a separate section, we describe how actual traces can also be used to extract a set of input parameters for synthetic trace generation. Finally, we show how the simulator may be successfully employed to carry out a detailed performance analysis of a specific coherence protocol. >

Hardware approaches to cache coherence in shared-memory multiprocessors. 2

Improving performance and scalability in shared-memory multiprocessors requires an appropriate solution to the well-known cache coherence problem. Hardware schemes-highly convenient because of their transparency for software-offer fully dynamic solutions, with an ability to achieve high performance. In Part 1 of this two-part series, we discussed the principles of the two major groups of hardware protocols and summarized relevant representatives. Here, we also briefly consider the coherence problem in multilevel cache hierarchies and large-scale, shared-memory multiprocessors. >

Performance Implications of Synchronization Support for Parallel Fortran Programs

This paper studies the performance implications of architectural synchronization support for automatically parallelized numerical programs. As the basis for this work, we analyze the needs for synchronization in automatically parallelized numerical programs. The needs are due to task scheduling, iteration scheduling, barriers, and data dependence handling. We present synchronization algorithms for efficient execution of programs with nested parallel loops. Next, we identify how various hardware synchronization support can be used to satisfy these software synchronization needs. The synchronization primitives studied are test&set, fetch&add, and exchange-byte operations. In addition to these, synchronization bus implementation of lock/unlock and fetch&add operations are also considered. Finally, we ran experiments to quantify the impact of various architectural support on the performance of a bus-based shared memory multiprocessor running automatically parallelized numerical programs. We found that supporting an atomic fetch&add primitive in shared memory is as effective as supporting lock/unlock operations with a synchronization bus. Both achieve substantial performance improvement over the cases where atomic test&set and exchange-byte operations are supported in shared memory.

False sharing and spatial locality in multiprocessor caches

The performance of the data cache in shared-memory multiprocessors has been shown to be different from that in uniprocessors. In particular, cache miss rates in multiprocessors do not show the sharp drop typical of uniprocessors when the size of the cache block increases. The resulting high cache miss rate is a cause of concern, since it can significantly limit the performance of multiprocessors. Some researchers have speculated that this effect is due to false sharing, the coherence transactions that result when different processors update different words of the same cache block in an interleaved fashion. While the analysis of six applications in the paper confirms that false sharing has a significant impact on the miss rate, the measurements also show that poor spatial locality among accesses to shared data has an even larger impact. To mitigate false sharing and to enhance spatial locality, we optimize the layout of shared data in cache blocks in a programmer-transparent manner. We show that this approach can reduce the number of misses on shared data by about 10% on average.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MIN-Graph: A Tool for Monitoring and Visualizing MIN-Based Multiprocessor Performance

A Multistage Interconnection Network (MIN) makes it possible to build large-scale shared-memory multiprocessor systems. To provide insight into dynamic system performance, we have developed an integrated data collection, analysis, and data visualization environment for a MIN-based multiprocessor system, called MIN-Graph. MIN-Graph is a graphical instrumentation monitor to aid users in investigating performance problems and in determining an effective way of exploiting the high performance capabilities of interconnection network multiprocessor systems. Our monitor measures, analyzes, evaluates, and displays the events, performance, and overhead of interprocessor communication, process scheduling, remote-memory access, network contention, and other processes on a MIN-based multiprocessor. The graphical monitor is X-window based and implemented on the BBN GP1000 and the BBN TC2000.

Performance of RISC-based multiprocessors

In this paper, a new performance evaluation methodology for the RISC-based multiprocessor systems is presented. The study relies on a detailed simulation model of the RISC processor that considers various applications and a wide spectrum of operation environments and conditions. The technique is applied on the crossbar switch and delta interconnection networks (IN). The benchmark programs are characterized by their percentage of I/O instructions (α-ratio). The MC88100 RISC processor, which includes four processing units and numerous pipelines, is considered in this simulation study as a case study and it is modeled in a detailed method that considers all interaction between CPU units. The main performance measures used in this paper are the speedup, probability of blocked requests and the relative speedup. A comparative performance study is made between crossbar switch and delta INs. It is found that due to internal I/O pipeline saturation in RISC processors, all performance measure curves saturate near the 80% α-ratio. A linear equation predicting the speedup is derived for both the crossbar switch and the delta INs.

The performance of cache-coherent ring-based multiprocessors

Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective use of powerful microprocessors in shared memory multiprocessor configurations. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessors, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new microprocessors. In this paper we evaluate the performance of unidirectional slotted ring interconnection for small to medium scale shared memory systems, using a hybrid methodology of analytical models and trace-driven simulations. We evaluate both snooping and directory-based coherence protocols for the ring and compare it to high performance split transaction buses.

Architecture, design, and performance of Application System/400 (AS/400) multiprocessors

The architecture, design, and performance of multiprocessors in the Application System/400® (AS/400®) family are discussed. The paper describes how this multitasking system, originally designed as a uniprocessor system, was modified to form a multiprocessor system. The unique approach, using relatively atomic instructions, required a minimum of change while providing significant performance gains.

Multiprocessor performance for real-time processing of video coding applications

The authors discuss the performance of multiprocessor architectures to be applied for video coding algorithms. SIMD, SIMD cluster, and MIMD architectures are studied by a unified performance approach under specific constraints of video coding algorithms. The proposed performance model considers communication and computation times as well as the required silicon area. MIMD architectures are compared to SIMD with regard to their performance. The optimization of architectural parameters for SIMD and MIMD architectures is discussed. It is shown how the proposed performance model can be applied to the design of VLSI-based multiprocessor systems for video coding. >

The impact of communication locality on large-scale multiprocessor performance

As multiprocessor sizes scale and computer architects turn to interconnection networks with non-uniform communication latencies, the lure of exploiting communication locality to increase performance become inevitable. Models that accurately quantify locality effects provide invaluable insight into the importance of exploiting locality as machine sizes and features change. This paper presents a framework for modeling the impact of communication locality on system performance. The framework provides a means for combining simple models of application, processor, and network behavior to obtain a combined model that accurately reflects feedback effects between processors and networks. We introduce a model that characterizes application behavior with three parameters that capture computation grain, sensitivity to communication latency, and amount of locality present at execution time. The combined model, we show that exploiting communication locality provides gains which are at most linear in the factor by which average communication distance is reduced when the number of outstanding communication transactions per processor is bounded. The combined model is also used to obtain rough upper bounds on the performance improvement from exploiting locality to minimize communication distance.

Simulated performance of a RISC-based multiprocessor using orthogonal-access memory

This paper reports the simulated performance of the Orthogonal MultiProcessor (OMP) under development at the University of Southern California. The OMP is simulated with hardware parameters used in the system design. The results are obtained by using a CSIM-based multiprocessor simulator developed at USC. The OMP was evaluated in SPMD ( Single-Program and Multiple-Data-streams) mode, which demands interprocessor synchronizations at the subprogram level, rather than at the instruction lockstep level as in an SIMD machine. The simulated OMP consists of 16 Intel i860 processors and 256 memory modules interconnected by two-dimensional spanning buses. The simulated benchmarks include unfolded matrix multiplication, two-dimensional FFT, orthogonal sorting, and parallel pattern clustering. These simulation experiments resulted in a speedup factor between 10 and 15, as compared with a system using a single i860 processor. The paper also reports program and data partitioning methods for the OMP and discusses the effects of synchronization and vector register windows on the multiprocessor performance.

A program-driven simulation model of an MIMD multiprocessor

A simulation model that supports very accurate modeling of multiprocessors with a hierarchical, packet-switched interconnection network and private caches is explored. The simulation system contains workload simulators and a memory system simulator. The workload simulators are program-driven, i.e. they actually execute programs. The time unit of the simulator is the time between two consecutive memory references from the processors. The performance of the simulation model, although acceptable, could be improved using a trace-driven approach. The author shows that results obtained from trace-driven simulation methods in the course of multiprocessor performance evaluation are generally not valid. Furthermore, he shows that in the evaluation of certain processor architectural features, such as non-blocking architectures, the program-driven approach is necessary. >

Book review: Multiprocessor Performance by Erol Gelenbe (John Wiley &amp; Sons, 1989)

This book begins with a survey of the different approaches to paralletizing computation: vector or array processors, loosely-coupled distributed systems, and multiprocessor systems. The author then states his principal thesis, that only multiprocessor systems offer the potential for unlimited processing power in the machines of the future. Since the impetus for designing multiprocessor systems is to improve performance, it is obviously crucial to evaluate the performance of these systems. This is the task set out for the rest of the book.

Book review: Multiprocessor Performance by Erol Gelenbe (J. Wiley &amp; Sons, Chichester, England)

Book review: Multiprocessor Performance by Erol Gelenbe (J. Wiley &amp; Sons, Chichester, England)

Task allocation in data flow multiprocessors

The performance of data flow multiprocessors depends to a large extent on the methods used to partition a data flow program and assign the resulting computational tasks among the processors. We cite significant contributions to the field of data flow computing, and categorize these efforts according to the granularity of the partitions and by whether task allocation is static (performed at compile time) or dynamic (performed during execution of the program). Each reference is accompanied by a brief description of the task allocation techniques used in the system.

A comparative simulation study of the performance of single-bus and two-bus multiprocessors

This paper presents a comparative simulation modeling of the performance of the uniprocessor, single-bus multiprocessor, and two-bus multipro cessor computer systems. The performance indexes of the single-bus and two-bus multiprocessor systems compared to the uniprocessor system, that are used in the modeling, are processor speedup factors SP1 and SP2 respectively. A third perfor mance index, Bus-speedup factor, SB, is derived to compare the performance of the two-bus and single- bus systems. The first two indexes provide measures of the processing speedup improvement of both multiprocessors with respect to the uniprocessor system, while the third index provides a measure of the performance improvement resulting from adding an extra bus to the single- bus multiprocessor system. Three data transfer protocols are considered in this work: First Come First Served (FCFS), Token Ring (TR), and the Priority (PR) Policy. Simulation experiments show that increasing the number of processors in the considered multiprocessor architectures does not necessarily improve the overall performance. Moreover, adding an extra bus to the single- bus architecture provides some speedup improvement that depends on the nature of the task program and the data transfer protocol. Simulation results show that FCFS and TR scheduling policies provide better performance than the PR policy. However, FCFS requires relatively less hardware and software complexity than the TR.