Performance Of MOSFETs Research Articles

A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels

This paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge the device and package–heatsink–board (PHB) level simulators. As a result, the cross-scale electrothermal coupling effect within multilevel settings is considered. Correspondingly, variation values in chip temperature and temperature-dependent drain current can be obtained at various voltage biases, level settings, and DPHB structural parameters, incorporating cross-level physical insights. The simulation results are compared with existing methods, and their features and limitations are discussed. Additionally, this paper also derives an empirical equation from the co-simulations to characterize the relationship between the drain current and the chip temperature under different operations exactly. A commercial MOSFET with TO-220F packaging is implemented in experiments to extract the chip temperature and drain current in electrothermal equilibrium. The method comparisons and fair agreement among simulations, equations, and measurements presents the proposed approach as generalized and powerful for describing variations in chip temperature and drain current considering from micrometer devices to millimeter packages–heatsinks–PCB boards, thus providing effective support for DPHB-level co-design.

High-temperature time-dependent dielectric breakdown of 4H-SiC MOS capacitors

—With the rapid applications of silicon carbide metal–oxide–semiconductor field-effect transistor (SiC MOSFET) power devices, further improving the performance of SiC MOSFET device through enhancing its gate oxide reliability is one of the crucial directions. The density of interface states in a SiC MOSFET is a significant parameter that affects the reliability of the gate oxide layer. In this paper, the SiC MOS capacitors (MOSCAPs) were prepared by the 1250 °C dry oxidation and 1350 °C NO annealing process. Then, we analyzed the mechanisms of the breakdown by two group of ramped experiment. And we still evaluated the reliability of oxide layer via the high-temperature time-dependent dielectric breakdown (TDDB) tests on the prepared MOSCAPs, meanwhile, the temperature effect on the reliability was considered. Furthermore, the E, 1/E, and E models with Weibull plotting were used to calculate the tBD lifetimes and failure analysis was carried on the failed samples finally. The results indicate that: (1) the impact of the generation and accumulation of the traps in the oxide, which is the main mechanisms of device failure; (2) The prediction of lifetime was calculated with three models at different acceleration factors; (3) at high-temperature, although the lower the density of interface states is, the Si epitaxial growth and C cluster will manifest in the oxide surface and lead to the breakdown of SiC MOSCAPs.

A Critical Analysis and Comparison of the Effect of Source Inductance on 3- and 4-Lead SuperJunction MOSFETs Turn-Off

This paper critically compares the turn-off performance of two package solutions, 3-lead (3L) vs. 4-lead (4L), in SuperJunction MOSFETs. It is commonly assumed that the better performance (lower switching losses) of the 4L MOSFET is obtained thanks to the decoupling of the power and driving loops. On the contrary, in this work, the experimental results, circuit models and Kirchhoff laws show that the turn-off improvement (lower turn-off losses) obtained by adopting the Kelvin source is due to the lower inductance of the driver loop of the 4L MOSFET, instead of the decoupling between the driver and power loops. In detail, an inductor is added to the gate path of the 4L MOSFET to obtain a total inductance in the driver loop equal to the 3L counterpart. The experimental results show that the 4L MOSFET presents the same drain current slew rate under this condition, although the driver and power loops are still decoupled.

Comparison and analysis on static and dynamic performance of 1.2-kV SiC planar MOSFETs with different cell topologies

1.2-kV SiC MOSFETs with different cell topologies were fabricated based on the same design and process parameters in a commercial 6-inch SiC foundry. A series of comparative evaluations were conducted on the static and dynamic performance of SiC MOSFETs with common linear, island-shaped P+ linear, current sharing linear, and hexagonal cell topologies for the first time. The common linear cell topology has the lowest switching loss, but the highest on-resistance. The island-shaped P+ linear and current sharing linear cell topologies optimized the cell pitch, reduced the specific on-resistance by 9.68 %, but the freewheeling and surge capability of their body diode have been decreased. The current sharing linear cell topology has the highest Ciss/Crss, making it the lowest in crosstalk intensity. The hexagonal cell topology has the lowest on-resistance, but performs the worst in terms of blocking characteristics and switching losses.

Dynamic Bias-Temperature Instability Testing in SiC MOSFETs

For power converter development in mission critical applications, the attractive performances of SiC power MOSFETs are shadowed by reliability concerns, particularly those induced by the defects at the gate dielectric. Charge trapping at the oxide-semiconductor interface can lead to threshold voltage drift, degrading the power converter efficiency and lifetime. The scope of this contribution is to show a testing methodology under development to understand SiC power MOSFET threshold voltage stability under dynamic and accelerated operating conditions. The presented testing methodology relies on switching the device under test at high-voltage and current, simultaneously applying a gate stress and extracting threshold voltage from switching transients. The paper outlines the setup description, its operating modes and intended design of experiment to assess SiC MOSFET threshold voltage stability.

Emission of Trapped Electrons from the 4H-SiC/SiO<sub>2</sub>-Interface via Photon-Irradiance at Cryogenic Temperatures

For a reliable MOSFET performance it is crucial to identify and reduce device performance limiting 4H-SiC/SiO2 interface defects. Previous studies have focused on the quantification of the interface states density, however, the atomic defect structure is still to be investigated. Here, we introduce a new approach based on opto-electrical measurements, which allow to determine the energetic position of interface defects. The measurement routine is performed at cryogenic temperatures to suppress the thermal emission of electrons, which were trapped at interface states during the cooldown processed (from 300 K to 15 K) while a positive gate voltage of 50 V was applied. At 15 K the photon-assisted emission of trapped electrons is measured in dependence on the photon’s energy (1.8 eV-3 eV). The reduction of the threshold voltage is taken as an indicator for the amount of released charges after each photon irradiation. We found an enhanced emission efficiency at certain photon energies, especially at 2.8 eV. Near-interface-traps (NITs), reported by Afanasev et al. are located close to the measuredtrap level with ENIT = EC, SiO2−2.77(5) eV. Recently, El-Sayed et al. suggested wide-angle O-Si-Obonds as defect configuration, that act as electron traps and have a similar energy as the measure traplevel.

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Impact of underlap layer is analytically investigated on asymmetric junctionless dual material double gate MOSFET (AJDMDG) to reduce subthreshold slope and threshold voltage, which are two essential requirements with shrinking device dimensions to avoid short channel effects. The model utilizes two-dimensional Poisson’s equation with parabolic approximation for determining electrical parameters where dimensional ranges are kept within fabrication limit. Excellent accuracy is found for the obtained analytical outcome, when compared with results obtained from TCAD ATLAS simulator. Comparative study is extended for conventional junctionless DMDG (JDMDG) and underlap asymmetric junctionless single material DGFET (UAJDG) device, having identical dimensional parameters and biasing ranges; where the present structure exhibits superior performance in terms of threshold voltage, subthreshold slope and DIBL of 34.57%, 62.85% and 69.85% respectively compared to JDMDG and 12.50%, 26.08% and 40.25% respectively w.r.t UAJDG structure. Supremacy of the proposed architecture is further established with RF/analog Figures of Merit (FOMs), which are essential for designing low power analog amplifier.

Recent Fundamental Advances in Quality of High-Performance and Highly-Scaled Carbon Nanotube Transistors

Recently a number of breakthroughs have been reported by our team in the component qualities of transistors built on Carbon Nanotube (CNT) channels. However, any emerging channel material which seeks to outperform established semiconductors for transistor logic applications has a substantial hill to climb, given the incredible capabilities of advanced Si-based logic technology platforms. This talk will first aim to frame our progress on Carbon Nanotube CMOS technology in the broader context of the value proposition and desired component qualities needed to realize practical impact in computing applications. Next, we will share advances in the fundamental building blocks for Carbon Nanotube transistors towards these targets including channel, contact, doping, and gate-stack modules. Finally we will describe new record CNT MOSFET performance milestones achieved by integrating best available device components for first time, which gives insight into the remaining performance limiters and future directions.[1] G. Pitner, et al., "Building High Performance Transistors on Carbon Nanotube Channel," VLSI 2023.[2] S. Li, et al., "High-Performance and Low Parasitic Capacitance CNT MOSFET: 1.2 mA/um at Vds of 0.75 V by self-aligned doping in sub-20 nm spacer," IEDM 2023.[3] N. Safron, et al., "Low N-type Contact Resistance to Carbon Nanotubes in Highly Scaled Contacts through Dielectric Doping," IEDM 2023.[4] H.-Y. Chiu, et al., "Self-Aligned Contact Doping for Performance Enhancement of Low-Leakage Self-Alignment Method for High-Density Aligned CNT Array," Advanced Materials Interfaces, 2023.[5] T.A. Chao, et al., "Small Molecule Additives to Suppress Bundling in Dimensional-Liminted Self-Alignment Method for High-Density Aligned CNT Array," Advanced Materials Interfaces, 2023.[6] Q. Lin, et al., " Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors," ACS Nano 2023.[7] Z. Zhang, et al., "Complementary Carbon Nanotube Metal-Oxide-Semicondcutor Field-Effect Transistors with Localized Solid-State Extension DOping," Nature Electronics, 2023.[8] S.K. Su, et al., " Perspective on Low-Dimensional Channel Materials for Extremely Scaled CMOS," VLSI 2022.[9] Z. Zhang, et al., "Sub-Nanometer Interfacial Oxides on Highly Oriented Pyrolytic Graphite and Carbon Nanotubes Enabled by Lateral Oxide Growth," ACS Applied aterials & Interfaces, 2022.[10] G. Pitner, et al., "Sub-0.5 nm Interfacial Dielectrics Enables Superior Electrostatics: 65 mV/dec top-gated Carbon Nanotube FETs at 15 nm gate length," IEDM 2020.

Impact of deep cryogenic temperatures on gate stack dual material DG MOSFET performance: Analog and RF analysis

By understanding the potential benefits of Gate Stack Dual Material double gate MOSFET (DG MOSFET), this research aims to contribute to the investigation of its electrical characteristics with improved performance and dependability. A detailed investigation is conducted into the temperature dependent electrical properties at different temperatures. A detailed analysis is conducted on the enhanced gate controllability in lower technology nodes and the protection against short channel effects. Together with the DC performances, this research also analyzes the suggested device's analog performance. The device's performance matrix was presented for temperatures ranging from 70 K to 800 K. The results showsthe improvement the drain current, transconductance, and transconductance generation factor(TGF) with decrease in temperature.

Ge quantum well channel P-MOSFET for 2.45 GHz wireless weak energy harvesting

Wireless energy harvesting is an important application of microwave wireless energy transmission system, but due to the weak energy of RF signals in the 2.45 GHz band, its rectification efficiency is not ideal. As one of the core rectifier components of wireless weak energy harvesting system, the performance of MOSFET determines the rectification efficiency of the system, and its optimized design to improve the rectification efficiency is an important direction of current research in the field. In view of this, this paper proposes and designs Ge quantum well channel PMOS for wireless weak energy harvesting at 2.45 GHz, aiming to improve the rectification efficiency of wireless weak energy harvesting systems. Starting from adjusting the structural physical parameters of the MOS tubes, the absolute value of the threshold voltage is reduced in the weak energy density region, which in turn improves the rectification efficiency of the device. Then, the novel diode connection with the introduction of substrate bias effect is compared with the conventional connection using an ADS simulation circuit, and the simulation results show that the leakage current is smaller and the rectification efficiency is higher under the novel connection. On this basis, a Ge quantum well channel PMOS device is proposed. Compared with the Ge surface channel, the hole mobility of the quantum well channel will be greatly improved, and its rectification efficiency can also be improved. The device is connected to the rectifier circuit with a novel connection and simulated using Silvaco's Mixedmode module. The results show that the rectification efficiencies of the Ge quantum well channel MOS reach 13.53 % and 32 % at low input powers of −20.34 dBm and −6.28 dBm, respectively, which are 3.3 and 1.14 times higher than those of the conventional surface channel MOS.

Study on gate‐source voltage oscillation suppression in SiC MOSFETs based on LCR parallel branch

AbstractSilicon carbide (SiC) MOSFETs are garnering widespread attention due to their superior performance in high‐temperature, high‐frequency, and high‐voltage applications, emerging as the preferred power semiconductor devices in converters for photovoltaic power generation and new energy vehicles. However, SiC MOSFETs are prone to gate drive and drain‐source voltage oscillations during high‐speed switching events, resulting in diminished system efficiency, increased electromagnetic interference, reduced device safety, and even compromising the overall reliability of the converter. This paper introduces an oscillation suppression method based on a gate LCR parallel branch, aimed at optimizing the switching performance of SiC MOSFETs. A half‐bridge circuit model based on SiC MOSFET is established, and the mechanism of gate and drain‐source oscillation is meticulously analysed using the transfer function expression. Building upon this, the LCR parallel branch parameters are meticulously designed to introduce appropriate damping in the gate drive path, effectively mitigating oscillations. Experimental results demonstrate that the proposed design not only significantly reduces the amplitude of oscillations but also shortens the switch‐transition time. This enhancement effectively increases the switching frequency and reduces switching losses.

Impact of low-temperature and low-pressure mild oxidation after plasma solidification on electrical properties and reliability in ultra-thin SiON MOSFETs

The impact of different SiON manufacturing processes on performance and reliability behaviors has been investigated for the MOSFETs. The performance of devices composed of an ultrathin SiON film fabricated by the novel low-temperature and low-pressure mild oxidation after the plasma solidification (LLMOPS) method can be enhanced compared to conventional processes, which is attributed to the increased mobility. It is observed from secondary ion mass spectrometry analysis that the distribution of nitrogen with the LLMOPS process moves toward the upper surface of SiON. As a result, the p-MOSFET manufactured by the LLMOPS process exhibits lower electrical performance degradation during the NBTI stress, indicating that a reduction in nitrogen concentration at the Si/SiO2 interface contributes to improving NBTI behavior. It is also demonstrated that the inhibition of NBTI phenomena enhances the frequency stability on the ring oscillator with circuit simulation. Thus, the LLMOPS process is a promising approach to improve the performance and reliability of MOSFETs in mass production.

Small Signal Parameters Extraction and RF Performance of GaN-Based Dual-Metal Cylindrical Surrounding Gate Junctionless Accumulation-Mode (DM-CSG-JAM) MOSFET

In this paper, small-signal model parameters and RF characteristics of the GaN-based Dual-Metal Cylindrical Surrounding Gate-Junctionless Accumulation Mode (DM-CSG-JAM) MOSFET has been extracted. Better scattering parameters has been observed for GaN-based DM-CSG-JAM MOSFET over other analogous structures which confirms its applications for RF domain. Also, enhanced drain current, transconductance, cut-off frequency, I on/I off ratio, etc. have been observed for the GaN-based device. The performance of the GaN-based MOSFET has also been compared with the other compound semiconductors (GaAs, InP) and silicon-based DM-CSG-JAM MOSFET. On account of the eminent properties possessed by GaN, the GaN-based device shows outstanding characteristics over the other semiconductor-based device.

Assessment of 180 nm double SOI technology for analog front-end design with back-gate voltage

This paper provides an assessment of the electrical and noise performance in the 180 nm double silicon-on-insulator (DSOI) technology, which shows advantages for analog front-end radiation detectors. For the first time, the impact of the back-gate voltage on the electrical and noise performance of DSOI MOSFETs is investigated. The transconductance-to-current (gm /ID ) ratio and low-frequency (1/f) noise were measured as a function of the MOS device types (NMOS/PMOS), gate length, and bias condition of front- and back-gates. Experimental results show that positive back-gate voltage deteriorates the gm /ID ratio of the MOSFETs in weak inversion region. The DSOI NMOS devices overwhelm the PMOS with better gm /ID and 1/f performance. The DSOI devices have a comparable 1/f noise with the 180 nm SOI counterparts. With negative back-gate voltage applied, the low frequency noise performance of NMOS is improved. This assessment of DSOI technology gives a guideline for the readout circuit design in detector front-end systems.

Analysis on performances of ultra-thin vertical MOSFET depending on position of gate–drain misalignment

In advanced MOSFET design, a vertical-channel structure provides the advantages of a smaller footprint of the transistor cell and stronger immunity against short-channel effects by introducing higher freedom in determining the channel length. For these reasons, vertical devices are still predicted to be an upcoming solution in the most recent technology roadmap. However, due to the cell-to-cell or wafer-to-wafer processing deviation that inevitably exists, it can be quite challenging to locate the gate edges at the exact positions that maximize the device performance. In this work, a series of technology computer-aided design (TCAD) device simulations have been carried out to investigate the effects of gate underlap and overlap structures on the device performance of vertical-channel MOSFETs. The device characterizations were conducted from the aspects of both DC and HF operations for higher completeness of this work, since both are not usually optimized at the same time under the same structural and processing conditions. Under the underlap condition, slight degradation in the on-state current (I on) drivability was observed. On the other hand, a noticeable off-state current (I off) increase was witnessed under the underlap conduction. It is explicitly demonstrated that excessive gate underlap results in non-ideal effects, including degradation of the subthreshold swing (S), worsening of drain-induced barrier lowering, and lowering of the maximum transconductance (g m,Max). In the HF analyses, although f T and f max remained high under overlap and gate–drain alignment conditions, it was observed that both were likely to deteriorate under underlap conditions. As a result, a processing margin in the anisotropic etching of the gate can be obtained for the optimization of the DC and HF performance of vertical-channel MOSFETs, paving the way for a wide variety of low-power and high-speed analog and digital applications.

Thickness Effect of Copper Clips on Power Module Packaging Design

The superior switching performance of SiC MOSFETs compared to Si devices is limited by packaging-related issues. High electromagnetic parasitics which lead to high voltage overshoots, and higher power losses are the main challenges of high frequency operation. Hence, packaging design modification and optimisation are necessary to accommodate faster switching. Copper clips replacing the bonding wires show promising results in reducing stray inductances, while enhancing the current conduction and heat dissipation since the clip are in contact with a larger area of the semiconductor chip. Silver sintering instead of soldering further improves the electrothermal behaviour. This paper investigates numerically various thicknesses of the copper clips and their effect on double-sided silver sintering, half-bridge 1200V/400A SiC MOSFET power module. Moreover, the silver layer thickness is varied to reduce th maximum stresses on the chip - silver interface.

The Performance of Organic Field Effect Transistor Affected by Different Thickness of Active Semiconductor Layer and Thickness of Gate Insulator

The purpose of this paper is to fabricate organic field effect transistor and to investigate the effect of the thickness of the pentacene active layer and the thickness of gate insulator layer on MOSFET performance. The fabricated structure is top-contact. When the thickness of the insulator gate layer increases from 10 nm to 30 nm, the magnitude of the drain source current, when VGS = VDS = -4 V, decreases from 1813 nA to 214 nA and then the threshold voltage shifts from -1.4 V to -2.4 V. When the thickness of the pentacene increases from 9 nm to 40 nm, the threshold voltage voltage shifts slightly in the negative direction from -1.4 V to -1.6 V for SiO2 thickness of 10 nm. In case of SiO2 thickness of 20 nm, the threshold voltage voltage shifts from -1.9 V to -2.2 V. In case of SiO2 thickness of 30 nm, the threshold voltage voltage shifts from -2.4 V to -2.9 V. Besides that, the mobility decreases from around 0.31 cm2/(Vs) to 0.15 cm2/(Vs) when the pentacene thickness increases from 9 nm to 40 nm.

Improved performance of H-diamond MOSFETs with ZrO2/Al2O3 gate dielectric stacks deposited by electron beam method

H-diamond MOSFETs with ZrO2/Al2O3 gate dielectric stacks were fabricated using an electron beam (EB) evaporation technique. The fixed positive charge in the ZrO2 contact layer depleted the two-dimensional hole gas to achieve normally off operation. Thanks to the leakage suppression of Al2O3 blocking layer, the device exhibited a considerably low gate leakage current of 1.8 × 10−6 A/cm2 at VGS = −5 V. Contributed from the relatively lower estimated interfacial state density (1.45 × 1012 cm−2 eV−1) and uncontaminated ZrO2/Al2O3 gate interface, the maximum mobility was estimated to be 345.8 cm2/V·s at VGS of −2 V, indicating excellent interfacial property of ZrO2/H-diamond. The hole mobility remains an almost constant of about 150 cm2/V·s for −4 V ≤ VGS ≤ −7 V. The maximum drain current density with 6 μm-gate length was −112 mA/mm at VGS of −7 V. These results will provide an approach for fabricating high-performance H-diamond FETs.

Degradation of electrical performance and radiation damage mechanism of cascode GaN HEMT with 80 MeV proton

In this paper, proton irradiations on Cascode GaN HEMT power device with an energy of 80 MeV and fluences of 2 × 1011 p/cm2 and 6 × 1011 p/cm2 have been carried out, where the threshold voltages drifted negatively by 20.55% and 28.17%, respectively. After two months of room temperature annealing, the threshold voltages recovered 0.22 V and 0.27 V, respectively. The ionizing deposition energy (IEL) was simulated by using Monte Carlo software and TCAD, it the results showed that the value of IEL in Si MOSFET is 5 ∼ 6 orders higher than that in GaN HEMT, while the value of the non-ionizing energy loss (NIEL) is one order higher than that in GaN HEMT. It means that the proton irradiation on the Cascode depleted GaN HEMT is more prone to produce displacement damage. As a large number of electrons and holes pairs were existed on the incident path of Si MOSFET under the proton irradiation, the produced electron will be captured by the gate oxide traps at the SiO2/Si interface, and the holes be captured by the defects generated in displacement damage, resulting in the accumulation of oxide trapped charges. Then, the electrical performance of Si MOSFET degrades seriously, thereby affecting the performance of the entire device. The studies will be helpful for the radiation hardening of Cascode GaN HEMT.

A Simulator for Investigation of Breakdown Characteristics of SiC MOSFETs

Breakdown characteristics play an important role in silicon carbide (SiC) power devices; however, the wide bandgap of SiC poses a challenge for numerical simulation of breakdown characteristics. In this work, a self-developed simulator employing a novel numerical processing method to prevent convergence issues, based on semi-classical transport models and including several kinds of mobility, generation and recombination models, is used to investigate the performance and breakdown characteristics of 4H-SiC MOSFETs in high-power applications. Good agreement between our simulator and an experiment and commercial TCAD was achieved. The simulator has good stability and convergence and can be used as a powerful tool to design and optimize semiconductor devices. Further, the breakdown characteristics are evaluated with different factors, including lattice temperature, device structure and doping profiles. Our results show that the doping profile plays the most important role in the breakdown voltage, followed by the device structure, while the impact of lattice temperature is found to be minimal.