Interconnect Performance Research Articles

Performance of stainless steel interconnects with (Mn,Co)3O4-Based coating for solid oxide electrolysis

Mixed transition-metal oxide coatings are commonly applied to stainless steel interconnects for solid oxide cell stacks. Such coatings reduce oxidation and Cr evaporation rates, leading to improved degradation rate and stack lifetime. Here, the ChromLok™ MCO-based composition (Mn,Co)3O4 is applied to Crofer 22 APU stainless steel and evaluated specifically for application in solid oxide electrolyzer stacks operating around 800 °C and utilizing oxygen-ion-conducting solid oxide cells. The MCO coating is found to decrease the stainless steel oxidation rate by about one order of magnitude, and decrease the Cr evaporation rate by fourfold. The coating also dramatically lowers the rate of area-specific resistance increase for stainless steel coupons oxidized for 500 h with constant current applied, from 33 mΩ∗cm2 kh−1 for an uncoated coupon to less than 4 mΩ∗cm2 kh−1 for coated coupons. The coating is demonstrated on full-scale interconnects for single-cells, where the coating dramatically reduces degradation rate, and for a stack, which displays stable operation for 700 h.

Dissipativity and Integral Quadratic Constraints: Tailored Computational Robustness Tests for Complex Interconnections

A central notion in systems theory is dissipativity, which was introduced by Jan Willems with the explicit goal of arriving at a fundamental understanding of the stability properties of feedback interconnections. In robust control, the framework of integral quadratic constraints (IQCs) builds on the seminal contributions of Yakubovich and Zames in the 1960s. It provides a technique for analyzing the stability of an interconnection of some linear system in feedback with a whole class of systems, also referred to as uncertainty. This article surveys the key ideas of exploiting dissipativity and IQCs to systematically construct computational tests for robust stability and performance of uncertain interconnections in terms of linear matrix inequalities. The article focuses on the recently introduced notion of finite-horizon IQCs with a terminal cost, which is shown to provide a seamless link between dissipativity theory and absolute stability theory based on dynamic IQCs.

System Dynamics Approach for Evaluating the Interconnection Performance of Cross-Border Transport Infrastructure

System Dynamics Approach for Evaluating the Interconnection Performance of Cross-Border Transport Infrastructure

Ag metal interconnect wires formed by pseudoplastic nanoparticles fluid imprinting lithography with microwave assistant sintering

Nanoimprint technology has the advantages of low cost, high precision, high fidelity and high yield. The metal nanoparticle fluid is non-Newtonian fluid, which is used as the imprint transfer medium to realize high fidelity of pattern because of its shear thinning effect. In order to functionalize the metal nanoparticles microstructure, the subsequent sintering step is required to form a metal interconnect wire. Metal interconnect wire with fewer grain boundaries and fewer holes have excellent mechanical and electronic properties. In this paper, the pseudoplastic metal nanoparticle fluid was formed by Ag nanoparticle and precursor solution, and then the thermal diffusion process was completed by microwave sintering after interconnects were embossed. The influence of microwave and thermal atmosphere on the microstructure and performance of Ag Interconnect wires was analyzed and discussed, and the Ag Interconnect wires performance was determined under the influence of time and temperature parameters. In our experiments, the interconnects after microwave sintering can achieve 39% of the conductivity of bulk silver. The microwave sintering module might be integrated as the heat treatment module of the metal micro/nano pattern directly imprint lithography.

Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon Era

Due to the exceedingly high integration density of VLSI circuits and the resulting high power density, thermal integrity became a major challenge. One way to tackle this problem is Dark silicon. Dark silicon is the amount of circuitry in a chip that is forced to switch off to insure thermal integrity of the system and prevent permanent thermal-related faults. In many-core systems, the presence of Dark Silicon adds new design constraints, in general, and on the communication fabric of such systems, in particular. This is due to the fact that system-level thermal-management systems tend to increase the distance between high activity cores to insure better thermal balancing and integrity. Consequently, a designing dilemma is created where a compromise has to be made between interconnect performance and power consumption. This study proposes a hybrid wire and surface-wave interconnect (SWI) based Network-on-Chip (NoC) to address the dark silicon challenge. Through efficient utilization of one-hop cross the chip communication SWI links, the proposed architecture is able to offer an efficient and scalable communication platform in terms of performance, power, and thermal impact. As a result, evaluations of the proposed architecture compared to baseline architecture under dark silicon scenarios show reduction in maximum temperature by 15∘C, average delay up to 73.1%, and energy-saving up to ∼3X. This study explores the promising potential of the proposed architecture in extending the utilization wall for current and future many-core systems in dark silicon era.

Recent Advances and Trends in Advanced Packaging

In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.

Estimation of Shearing and Peeling Thermal Stress of Spinel Coated Metallic Interconnects of Solid Oxide Fuel Cells

Interconnects are used in solid oxide fuel cells (SOFCs) for connecting the fuel cell stacks. These interconnect are coated with spinel oxides to prevent the formation of a native scale oxide layer under high heat flux conditions. Generally, the SOFCs are subjected to thermal shock during their operation. At the interfaces of these coating, shear stresses and peeling stresses were induced due to a mismatch between the thermal expansion coefficient of coating and native scale thickness. These stresses peel off the coating layers which affect the interconnect performance. In this paper, the effect of varying native scale thickness at two different coating thicknesses on the shearing stress and peeling stress of the interconnects is analytically calculated along the two different interconnect thicknesses. The oxidation kinetics of spinel-coated SOFCs interconnects with the analytical equations relating native scale thickness with the time of SOFCs operation were reported. As per our analysis, we concluded that these stresses majorly depend on the thickness and the mechanical properties of the interconnects, native scale and a coating layer.

Process optimization for enhancing interconnect performance of large-size BGA component during vibration loading

A series of problems such as failure solder at SnAgCu large-size BGA component and Pb-rich phase at SnPb component are always found during mixed lead-free/tin-lead assembly. In order to give a better reflow process window of assembled printed circuit board, process optimization was carried out to satisfy a favourable reflow time for all the components. Numerical simulation according to the Box-Behnken design method was carried out to monitor the effective reflow time of mixed lead-free/tin-lead and tin-lead components, and a mathematical response model between the effective reflow time and the process curve was developed by multivariate quadratic regression analysis. An optimal reflow process curve was established by simulated annealing algorithm. According to the optimal process parameter, numerical simulation was carried out to observe the temperature distribution and residual stress, and the experimental researches including the vibration test and micro structure analysis were conducted on the mixed lead-free/tin-lead assembled component to monitor the dynamic resistance and deformation and characterize the reaction product at the interface. It is shown that the corner BGA component still suffers from both a higher residual stress (about 32 MPa) after reflow process and a larger deformation (about 64 μm) at the first order modality during random vibration test. However, a continuous intermetallic compound layer with the thickness of 1.2–1.5 μm containing the reaction products Ni3Sn4 and (Au,Ni)Sn4 is well generated, and no cracks and voids are observed.

On- and Off-chip Signaling and Synchronization Methods in Electrical Interconnects

Advances in integrated circuit (IC) fabrication technology, coupled with aggressive circuit design, have led to an exponential growth in speed and integration levels. However, to improve overall system performance, the communication speed between on-chip subsystems and between ICs in printed circuit board must increase accordingly. Currently, communication bus links in various applications approach Gbps (gigabits per second) data rates. These applications include high-speed network switching, local area network, memory buses, and multiprocessor interconnection networks. In this article, we analyze the most common (popular) CMOS implementations of high speed on- and off-chip links (electrical interconnects) and show that the links’ performance should continue to scale with technology. In addition, we point to the fact that global electrical interconnects are widely acknowledged as a limiting factor in future on-chip and off-chip designs. Novel electrical interconnect driving techniques like multi-level multi-wire signaling, and GALS synchronization method primarily intended to improve performance of on-chip electrical interconnects, has been shortly analyzed. In the future, in order to handle the electrical interconnects’ finite bandwidth (data rate higher than 100 Gbps), however, more sophisticated signaling and synchronization methods will be required.

Power Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes

We assess the performance impact of cobalt interconnect metallization for both signal routing and power delivery in advanced logic technologies with a minimum metal pitch of 32 nm or less. While cobalt interconnects may enable lower line resistance in narrow signal lines than industry-standard copper interconnects below a threshold pitch, there is still a significant performance penalty associated with using cobalt in wide lines, including both signal and power. For wide signal lines at minimum-pitch metallization levels, we find a delay penalty as much as 60%–100% depending on signal run length for Co interconnects. For wide power lines at minimum-pitch metallization levels, we find a parasitic voltage (IR) drop penalty as high as 50% for Co interconnects. In light of these performance disadvantages, we discuss several design strategies to minimize the impact of Co metallization for both signal routing and power delivery. We also highlight critical differences between low-power and high-performance design points for power delivery.

Thermal-Aware Modeling and Analysis of Cu-Mixed CNT Nanocomposite Interconnects

Growing only single-walled carbon nanotube (SWCNT) or only multi-walled carbon nanotube (MWCNT) in a bundle is not feasible practically. Thus, a random number of SWCNTs and MWCNTs whose diameters are also varied randomly (following a Gaussian distribution) should be considered in a bundle of mixed carbon nanotubes. A thermal aware electrical modeling of copper-mixed carbon nanotube (Cu-MCNT) composite interconnect is proposed here and its performance and reliability has been studied and compared with copper interconnect at 7 nm and 11 nm technology nodes. An increase in filling fraction (F_MCNT) of mixed carbon nanotubes in Cu-MCNT composites leads to a decrease in delay. But in some cases, if the fraction of SWCNTs is greater than that of MWCNTs in a bundle, then it leads to a higher delay. Variation in delay with respect to F_MCNT is more at higher temperature by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 10%. Cu-MCNT composite interconnects with F_MCNT = 0.5 have <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 52% higher breakdown power than copper interconnects and are thermally more efficient. Scaling down the dimensions leads to degradation in performance and reliability combined but this degradation is more in copper interconnect when compared to Cu-MCNT composite interconnect by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 14% Cu-MCNT composite interconnects attain <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 39% less temperature rise at steady state when compared to copper interconnects. The performance of Cu-MCNT composite interconnects in terms of meantime to failure at higher current densities is phenomenal as compared to copper interconnects. Our study promotes Cu-MCNT composite interconnects as an alternate candidate to copper interconnects considering their superior electro-thermal performance.

C-N-S Interconnection Degradation Mechanism and Performance of Organic-Rich Urban River Sediments Biochemical Remediation

C-N-S Interconnection Degradation Mechanism and Performance of Organic-Rich Urban River Sediments Biochemical Remediation

Gravity-Induced Progressive Collapse Response of Precast Corner-Supported Modular Buildings

Compared with conventional buildings, the design of interconnections in multistory modular buildings requires special attention, due to different load distribution mechanisms, level of redundancy, integration strategies, and the stability requirements, in particular under accidental load conditions. In this paper, the robustness of corner-supported modular steel buildings, subject to various sudden loss scenarios, is studied through investigating the collapse-resisting capacities and the probable gravity-induced progressive collapse mechanisms. The aim is to evaluate the minimum requirements and special considerations for the design of interconnections for robustness. To that end, archetypal precast room-sized volumetric modules with different heights are analyzed using the finite-element macromodelling method and the alternate load path approach. The load redistribution mechanisms are inspected, nonlinear dynamic responses are determined, and probable collapse mechanisms are identified for buildings with different heights and configurations. The dynamic increase factors are computed and compared with the values suggested by the design codes. Given that the individual modules are mainly made of inherently robust structures, the focus of this study is on the performance of interconnections and interactions between an assemblage of units. The results indicate that due to high redundancy in these systems, there is great reserve strength against gravity-induced progressive collapse scenarios, triggered by instantaneous removal of components.

Novel coupled modular steel structure and seismic tests on high-performance interconnection

Modular building registers the advanced stage of construction industrialization and the corner-supported steel modular building is the most widely applied. However, its structure, which is integrated by corner interconnections only, incurs the problems of structural redundancy and interconnection-assembly complexity. To this gap, this paper proposes the novel coupled modular steel structure and suitable interconnection, which significantly affects the overall structural response and assembly efficiency. Pseudo static tests of three full-scale cruciform joint specimens are implemented to study the seismic performance of interconnection. The results show that the currently proposed coupled modular steel structure could replace the incompletely-combined group-columns and laminated beams with single structural components to avoid the structural redundancy and reduce the assembly difficulty of interconnections. The proposed interconnection exhibits excellent seismic performance. Hysteretic loops of coupled beam and module beam are “bow” shape and “shuttle” shape, respectively, indicating their good hysteretic performance. Ultimate storey drift angles of coupled beam and module beam could reach 0.08–0.09 rad and 0.06–0.08 rad, respectively, which satisfy the requirement for SMF in ANSI/AISC 341-16 and indicate their excellent rotation capacity. The ductility coefficients of the specimens are 2.27–3.64 except for MC2, indicating their good ductility capacity. Adopting the flush end plate for coupled beam and high strength bolts for vertical splice is recommended for the interconnections to obtain better hysteretic performance and bearing capacity. This research provides brand new design for modular construction and references for future research on global response of coupled modular steel structure.

Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes

The temperature-dependent modeling technique (in the temperature range of 200–500[Formula: see text]K) for a mixed class of carbon nanotube (CNT) bundle interconnects is proposed. The equivalent single conductor (ESC) transmission line models of multi-walled carbon nanotube (MWCNT) and double-walled carbon nanotube (DWCNT) are combined to develop multiple single conductor (MSC) model of mixed CNT interconnects. Various possible arrangements of densely packed MWCNT and DWCNT bundles (MDCB) are considered to form different types of mixed CNT bundle structures (MDCB-1, MDCB-2, MDCB-3 and MDCB-4). The integrated circuit emphasis simulation is performed and the performances of these mixed CNT bundle interconnects are investigated in terms of propagation delay (with and without crosstalk), power dissipation, power-delay product (PDP). Switching times, overshoot voltages and Nyquist plots are analyzed to check the stability of these mixed CNT structures for global interconnect length for 32-nm, 22-nm and 16-nm technology nodes. It is observed that the MDCB-1 structure yields the most promising result in all aspects for interconnect applications in the near future.

Quantitative study in coupling loss reduction under a large mode-field mismatch using a self-written waveguide.

The coupling loss between optical devices is a critical factor affecting the performance of optical interconnect. This paper quantitatively studies the effectiveness of using a dye-doped-epoxy-based self-written waveguide (SWW) to reduce the coupling loss in optical interconnect caused by large mode-field mismatch and lateral offset. We formed SWW between single-mode fiber (SMF) with different mode-field diameters (MFD) and a 5 × 2 µm rectangular channel waveguide-under-test (WUT). For the case between a SMF with a mode-field diameter of 9.4 μm and the WUT, the coupling loss is -11 dB. After forming the SWW, the coupling loss is reduced by 8.34 dB. Using SWW, the lateral tolerance length between a SMF with a mode-field diameter of 4.5 μm and the WUT increases by 2.5 times. Under the above-mentioned situation, the coupling loss falls less than 0.20 dB over ± 2 μm lateral offset range. Our findings offer insights quantitatively for coupling loss reduction and relaxing the lateral tolerance under significant mode-field mismatch conditions.

Quality Control of Thick Film Hybrid Integrated Circuit Process Design and Manufacturing

With the continuous upgrading of the technological content of electronic products, higher requirements have been put forward for the manufacturing process of thick film hybrid integrated circuits, resulting in the manufacturing process of thick film hybrid integrated circuits. Thick-film hybrid integrated circuits are an important realization method of microelectronic components. They are widely used in many fields such as civil, military, and aerospace satellites. An important reason is that the thick film process has a super high cost performance compared with other process realization methods. Thick film conductive paste is the most core material in the thick film process. Its interconnection performance such as sintering and welding directly affects the performance of the finished thick film components. Therefore, the thick film conductive paste interconnection under specific process conditions is evaluated. Related performance is crucial. In the mass production process of thick film hybrid integrated circuits, it is particularly important to control the quality and increase the product growth rate. This paper introduces the description of the quality management of the rear-film hybrid integrated circuit production line in the aspects of thick-film hybrid integrated circuit quality system construction, raw material procurement, supplier management, project quality management, on-site management, etc. The manufacturing process of the back-film hybrid integrated circuit briefly introduced has stable performance, high reliability and wide application fields in terms of manufacturing characteristics. Studies have shown that the manufacturing process is suitable for mass automated production, and has the advantages of simple process, low investment, and quick results.

Impact of Measurement Uncertainty on Correlation Quality for High-Speed Interconnects

The ever-increasing demand for higher bandwidth and lower loss makes the predictability of high-speed interconnect performance increasingly challenging. Validating models against measurements of manufactured test structures requires not only accurate methodology but also understanding of the uncertainty impact. S-parameter measurements, characterization of materials, manufacturing processes, and models constructed based on measured inputs all cause uncertainty in the performance metrics of interest. Therefore, it is critical to anticipate the results with the associated uncertainty to assess the correlation quality more objectively. This article investigates the reproducibility of measurements required for high-speed package interconnect validation through rigorous analysis and presents a methodology to quantify the impact of measurement uncertainty on commonly used performance metrics.

Evaluation and Reduction of Signal Integrity Issues in Multiwalled Carbon Nanotube On-Chip VLSI Interconnects

Due to advancements in device scaling in very-large-scale integration (VLSI) technology, signal integrity (SI) issues play a major role to determining the performance of on-chip interconnects in high-speed digital circuits. The main SI issues are delays, peak voltage noise effects, crosstalk, and timing uncertainties. Here, the SI issues of the coupled multi-walled carbon nanotube (MWCNT) on-chip interconnects are evaluated with and without the effect of shielding technique and compared to the copper interconnects. The MWCNT exhibits an average of 47.9% smaller propagation delays than Cu in dynamic crosstalk conditions. Further, for crosstalk reduction, the active shielding (AS) and passive shielding (PS) techniques are proposed. With the AS and PS techniques, the MWCNT interconnects experience a decreased delay by 46.8% and 30.15% compared to without shielding technique, respectively. Moreover, the AS exhibits smaller crosstalk effects than the PS technique due to its input switching activities on shielded lines. In addition, the quality of the signal (QoS) and Intersymbol interference (ISI) noise effects of coupled MWCNT interconnect with and without shielding is evaluated. Finally, to improve the QoS and reduce the ISI effects, the decision feedback equalizer with the least mean square adaptive algorithm is implemented at the receiver end.

Additive Manufacturing of a W-Band System-on-Package

In this article, we demonstrate the design, fabrication, and characterization of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> -band system-on-package (SoP). This package is fully additively manufactured using a chip-first process and aerosol jet printing. With this method, we implement a transceiver consisting of two bare die amplifiers for transmitted and received signals, a bare die switch, printed bypass capacitors, surface-mount resistors for biasing networks, and a printed patch antenna, operating between 77.1 and 79.0 GHz. The second patch antenna of the same design, fabricated simultaneously, is used to characterize the antenna performance alone and the packaged components. Package substrates (dielectrics), conductors, and interconnects are printed around bare die attached to a carrier. Thin-film bypass capacitor dielectrics were printed using multimaterial aerosol jet printing (MMAJP), where aerosols of barium titanate and polyimide inks are mixed in place to form a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{r}$ </tex-math></inline-formula> polymer matrix nanocomposite film. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> -band interconnect performance is achieved using conformal-shaped ramp interconnects, allowing for frequency agnostic performance of the interconnect with no impedance discontinuity, within the physical limits of the printer. The antenna alone achieves a maximum gain of 6.7 dBi at 78.3 GHz, and the SoP achieves a gain of 16.4 dBi for the package. We estimate the package loss to be 2.8 dB or 0.6 dB/mm, including interconnects.