Performance Of FinFETs Research Articles

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks for many arithmetic circuits. This paper contrasts and evaluates the performance of conventional CMOS and FinFET based XOR-XNOR circuit design. It is based on the study of high speed, low power, and small area in XOR-XNOR digital circuits. The proposed FinFET based XOR and XNOR circuits have been designed using Cadence VIRTUOSO Tool applying voltage supply of 0.2 to 1.2 voltages, with temperature at 27 0 C and all the simulation results have been generated by Cadence SPECTRE simulator at 45nm technology. Simulation results exhibit low power, delay, power, delay product (PDP), and average dynamic power consumption.

3D Monte Carlo simulation of FinFET and FDSOI devices with accurate quantum correction

The performance of FinFET and FDSOI devices is compared by 3D Monte Carlo simulation using an enhanced quantum correction scheme. This scheme has two new features: (i) the quantum correction is extracted from a 2D cross-section of the 3D device and (ii) in addition to using a modified oxide permittivity and a modified work function in subthreshold, the work function is ramped above threshold to a different value in the on-state. This approach improves the accuracy of the quantum-correction for multi-gate devices and is shown to accurately reproduce 3D density-gradient simulation also at short channel lengths. 15 nm FDSOI device performance with thin box and back-gate bias is found to be competitive: compared to a FinFET with (110)/〈110〉 sidewall/channel orientation, the on-current for N-type devices is 25 % higher and the off-current is only increased by a factor of 2.5.

Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs

This paper investigates the impact of fin width ( W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> s = 15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device. Carrier conduction in the Si-fin body of FinFETs with various W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> s is also studied. The experimental results show that the threshold voltage and drain current of n-type FinFETs increases and decreases, respectively, as W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> is reduced. A thinner W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET exhibits greater immunity to short channel effects. In addition, according to the analysis results of low-frequency noise, the thinnest W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET possesses the largest bulk oxide trap density (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BOT</sub> ) than that of a thicker W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET. Moreover, the noise of the thinnest W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> (15 nm) FinFET is largely dominated by the fluctuation of carrier number. In the hot-carrier injection (HCI) reliability test, the thinnest W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET shows less performance degradation than those of the thicker ones. However, by removing the effect of the parasitic source/drain resistance, we believe that the volume inversion charged carriers flow through the entire thin Si-fin having a lower surface roughness and Coulomb scattering than those of thicker ones, which results in a higher carrier temperature and worsening of the reliability of the HCI.

Influences of Charged Dislocations on Performance of III-V Compound Semiconductor FinFETs

We present a model for charged dislocations effects on III-V compound semiconductor based FinFETs performance. The model is developed to obtain momentum relaxation time and, from it, key device performance parameters such as effective mobility, threshold voltage, and finally saturation drain current. We find out that charged threading edge dislocation density of a FinFET channel should be smaller than about 107cm-2to ignore the dislocation scattering impact on the device performance which is roughly one order more strict condition than previously known condition for wurtzite GaN.

Experimental Comparison between pTFET and pFinFET under Analog Operation

In this work, the analog performance of Tunnel FET and FinFET, which have a different principle of operation, is evaluated based on a comparison between them. This comparison is performed through the drain current behavior, the transconductance, the output conductance and the intrinsic voltage gain. Although the TFET devices present a smaller transconductance than the FinFET ones, the output behavior is strongly improved and results in a better performance of TFET devices when the focus is the intrinsic voltage gain.

Influence of gate-source/drain misalignment on the performance of bulk FinFETs by a 3D full band Monte Carlo simulation

We investigate the influence of gate-source/drain (G—S/D) misalignment on the performance of bulk fin field effect transistors (FinFETs) through the three-dimensional (3D) full band Monte Carlo simulator. Several scattering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G—S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G—D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G—D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.

Impact of the Aggressive Scaling on the Performance of FinFETs: the Role of a Single Dopant in the Channel

ABSTRACTNon-equilibrium Green’s functions (NEGF) simulations are carried out to determine the impact of an unintentional dopant in the middle of the channel of a FinFET. We consider two different geometries scaled according to the ITRS and two different types of dopants, donors and acceptors. We show that there is a degradation of the subthreshold characteristics with the scaling of the smooth device and also a stronger impact of the stray dopants in the middle of the channel, with variations up to 32% in the current in on-state conditions.

Impact of dual-k spacer on analog performance of underlap FinFET

Multigate structures have better short channel control than conventional bulk devices due to increased gate electrostatic control. FinFET is a promising candidate among multigate structures due to its ease of manufacturability. The RF performance of FinFET is affected by gate controlled parameters such as transconductance, output conductance and total gate capacitance. In this paper we have used dual-k spacers in underlap FinFETs to improve the gate electrostatic integrity. The inner high-k spacer helps in better screening out the gate sidewall fringing fields, thereby, increasing transconductance and reducing output conductance with increase in total gate capacitance. At 16nm gate lengths, we have observed that, the intrinsic gain of dual-k spacer based FinFET can be increased by more than 100% (>6dB) without affecting cutoff frequency and maximum oscillation frequency, as compared to conventional single spacer based FinFET. Improvement in cutoff frequency by 11% and maximum oscillation frequency by 5% can be achieved, when the gate lengths are scaled down to 12nm, in addition to 2.75 times (8.8dB) increase in intrinsic gain.

Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance

We compared the electrical characteristics, including mobility and on -state current Ion, of n+-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights Hfin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length Lg decreases, Ion for devices with tall fins becomes worse, probably due to a high parasitic resistance Rp. Furthermore, Vth variation increased with increasing Hfin due to rough etching of the fin sidewall. Process technologies for reducing Rp and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

Modeling of noise for p-channel DG-FinFETs

The noise performance of p-channel Double Gate FinFETs has been studied with varying structural parameters. The effects of mobility degradation due to velocity saturation, carrier heating and channel length modulation have been taken into consideration for an accurate modeling of noise. The dependence of mobility fluctuations on the inversion carrier density has been incorporated. This has been validated by the experimental results. The noise behavior of p-channel device has been compared to that of a corresponding n-channel device. It has been observed that noise in p-channel device is comparatively higher due to higher number of oxide-trap density in it. Further, it has been noted that with the same trap density in both p-channel and n-channel device, the flicker noise in the p-channel device is lower than that of the corresponding n-channel device.

Robustness Comparison of Emerging Devices for Portable Applications

Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real‐time portable domain. Operating the Si‐MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well‐designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most promising upcoming devices like CNFET and DG FinFET in subthreshold regions. Effect of PVT variation on performance of CNFET and DG FinFET has been explored and it is found that CNFET is more robust than DG‐FinFET under subthreshold conditions against PVT variations.

Computer Design of Source/Drain Extension Region Profile and Spacer Length in Tri-Gate Body-Tied Fin Field-Effect Transistors with High-k Gate Dielectrics

The influences of source/drain extension region engineering and high-k gate dielectrics on the device performance of tri-gate body-tied fin field-effect transistors (FinFETs) was investigated to achieve the International Technology Roadmap for Semiconductor (ITRS) projections for high-performance (HP) logic technology. The impact of lateral source/drain doping gradient (Ldg) and spacer length (Lsp) on short-channel effects (SCEs) was extensively analyzed by three-dimensional device simulation. Results show that a lateral doping gradient along with an appropriate spacer length not only can effectively control SCEs, resulting in a low off-current, but also can be optimized to achieve low values of intrinsic gate delay and high values of on-current. The ratio of spacer length to lateral doping gradient (Lsp/Ldg) between 2.7 and 4 is optimal for achieving a low intrinsic gate delay, a low off-current, and a high on/off-current ratio. The present work provides valuable design guidelines in the performance of tri-gate body-tied FinFETs with optimal source/drain extension region engineering and serves as a tool for optimizing important device and technological parameters.

Variability Analysis of TiN Metal-Gate FinFETs

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the in the FinFET occurs and the standard deviations of the of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the variation of the TiN FinFET is due to the work function variation (WFV) of TiN metal gate. The WFV is also responsible for the on-current variation.

Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs

In this letter, we report the enhanced fringe capacitance in FinFETs when compared to the equivalent planar MOSFETs at the 22-nm node. We show that this increase is due to the 3-D nature of the device and also due to the close proximity of the source/drain (S/D) epitaxial (epi) region to the metal gate. Using well-calibrated 3-D mixed-mode simulations, we show that this will cause the performance of FinFETs to be significantly degraded, unless proper device optimizations are carried out. Our results also indicate that the selective epi growth of S/D may adversely affect the overall performance of FinFETs, although it is effective in reducing series resistance. The increased parasitic components in FinFETs can be a serious issue for FinFET circuits with a large fan-out, and the solution lies in the aggressive fin pitch reduction, as shown in this letter.

Experimental studies of dose retention and activation in fin field-effect-transistor-based structures

With emerging three-dimensional device architectures for advanced silicon devices such as fin field-effect-transistors (FinFETs), new metrology challenges are faced to characterize dopants. The ratio of dopant concentration in the top surface and sidewalls of FinFETs may differ significantly, thereby influencing the performance of these devices. In this work, a methodology involving secondary ion mass spectrometry (SIMS) is presented to study the dose conformality in fins. However, SIMS is limited to probe the quantitative chemical dopant concentration (i.e., top/sidewall of fins). The fraction of the active dopant concentration determining the performance of FinFETs would still be unknown. Additionally, the concept based on SIMS is unable to provide information on the lateral junction depth. Thus, to obtain the unknown active dopant concentration and their spatial distribution, the authors extend their study by measuring the cross section of the fins with scanning spreading resistance microscopy and extracting the quantitative active carrier concentration in the fins.

Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability

We present a model for estimating the impact of gate line edge roughness (LER) on the performance of double-gate (DG) FinFET devices. Thirteen-nanometer-gate-length DG FinFETs are investigated using a framework that links device performance to commonly used LER descriptors, namely, correlation length (xi), rms amplitude or standard deviation (sigma) of the line edge from its mean value, and roughness exponent ( alpha). Our approach provides physical insight into how LER impacts FinFET performance. In addition, our modeling approach is more efficient than Monte Carlo TCAD simulations and provides comparable results with appropriately selected input parameters. The FinFET device architecture is found to be robust to gate LER effects. Furthermore, a spacer-defined gate electrode (versus a resist-defined gate electrode) provides for reduced variability in performance, indicating that the gate length mismatch has more impact than lateral offset between the front and the back gates.

Metal-Gate FinFET Variation Analysis by Measurement and Compact Model

A compact model (CM) for fin-type FETs (FinFETs) was successfully developed and applied to variability analysis of a fabricated state-of-the-art metal-gate (MG) FinFET. By combining the statistical measurements with the CM calibration, V th variation was, for the first time, broken down into structure-based (silicon fin thickness and gate length) and material-based (gate work function) components. As a result, the measured variation of MG FinFET performance was successfully reproduced by the CM. Characterization using the CM with the measured statistical data provides insight on the gate work function variation of 16 meV in short-channel molybdenum (Mo) gate FinFETs.

FinFET Design for Tolerance to Statistical Dopant Fluctuations

Variations in highly scaled (L G = 9 nm), undoped-channel FinFET performance, caused by statistical dopant fluctuations (SDFs) in the source/drain (S/D) gradient regions, are systematically investigated using 3-D atomistic device simulations. The impact of SDF on device design optimization is examined and simple design strategies are identified. Variation-tolerant design imposes stringent specifications for S/D lateral abruptness and gate-sidewall spacer thickness, and it poses a tradeoff between performance and variability for body thickness.

Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

Electrostatic discharge performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing parameters. Both N- and P-type MOS FinFET devices are characterized in bipolar operation mode as a function of layout parameters such as gate length and fin width. The impact of well implants, selective epitaxial growth, and strain is studied.