Performance Of FinFETs Research Articles

Enhancing the performance of Ga2O3 FinFETs through double fin channels and buried oxide

In this study, double fin channels and buried oxide has been implemented on Ga2O3 FinFET. Exhaustive simulations have been performed to study the performance of the proposed device and its comparison has been drawn with the device with only double fin channels without buried oxide, and the conventional FinFET. Various device characteristics such as output and transfer characteristics etc., have been studied and several figure of merits (FoMs) such as transconductance, parasitic capacitances, gain bandwidth product, intrinsic delay etc., have also been obtained. Further, the inverter has been designed using all the devices under consideration. It has been demonstrated that the inverter using the proposed device exhibits excellent characteristics in terms of significant improvement in key metrics such as noise margin, transient response etc., as compared to the inverter using conventional devices. The current study also lays the groundwork for designing various high-performance circuits for ultra-high frequency applications.

Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric

In this work, a high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length. Indium Gallium Arsenide (InGaAs) is a compound semiconductor that has gained attention in the field of semiconductor devices, including FinFETs. The incorporation of InGaAs in proposed FinFETs introduces several advantages, making it an attractive material for certain applications. InGaAs–SOI–FinFET performance has been observed and found high electron mobility, improved On-Current performance (ION), drain current (IDS), transconductance (gm), energy bands, lower subthreshold swing (SS), electric field, surface potential, and better short-channel behaviour. All the results of InGaAs–SOI–FinFET have been simultaneously compared with SOI-FinFET and conventional FinFET (C-FinFET). Incorporating InGaAs in the channel with high-k gate material enhances the drain current by ⁓75% and ⁓77% in the proposed device compared to the other two counterparts. Owing to the higher drain current in the InGaAs–SOI–FinFET, other parameters have also been improved, which leads to higher performance applications.

Thermal management and switching performance of β-Ga2O3 vertical FinFET with diamond-gate structure

In this paper, a beta-phase gallium oxide (β-Ga2O3) vertical FinFET with diamond-gate has been studied by Silvaco-ATLAS simulation. The diamond-gate structure achieves adjustable pin (p-insulator-n) junction owing to the diamond-SiO2-Ga2O3 heterostructure. This design also enhances heat dissipation by virtue of the high thermal conductivity of the diamond. Compared to conventional FinFETs, the diamond-gate FinFET (DG-FinFET) reduces the static operating temperature rise by around 17.30%. Additionally, due to its greater heat dissipation capacity, DG-FinFETs provide a 5.84% increase in current density at 1 kA cm−2 current density level. The structural changes in the diamond-gate also result in a significant reduction in the gate-source capacitance (C GS). At 1 MHz operating frequency and the same gate voltage, DG-FinFETs have 69.29% less gate-source charge (Q GS), 70.80% less charge/discharge delay time, 73.70% less switching loss, and 57.15% less conduction loss. Overall, the simulation and analysis presented in this work indicate a promising advancement of the DG-FinFET structure in high-power and rapid switching applications.

Effect of Temperature on RF and Linearity Performance of Inverted-T FinFET

Effect of Temperature on RF and Linearity Performance of Inverted-T FinFET

Advancements in single-crystal silicon with elevated-laser-liquid-phase-epitaxy (ELLPE) for monolithic 3D ICs

In this study, we present a low thermal budget elevated-laser-liquid-phase-epitaxy technique designed for the precise fabrication of single-crystal islands (SCIs) intended for use in middle-end-of-line (MEOL) FinFETs. Each of these SCIs features a (100) orientation tended from Si seeding structure and is successfully integrated as channel materials in the MEOL circuit of a monolithic 3D IC (3DIC). This technique effectively mitigates the typical performance disparities associated with poly-Si channel materials in upper tiers, addressing a significant challenge in advanced electronic device fabrication and potentially enhancing the performance and reliability of MEOL FinFETs in monolithic 3DIC.

Impact of Buried Gate Oxide on the Electrical Performance of Negative Capacitance FinFETs: Design Perspectives

Impact of Buried Gate Oxide on the Electrical Performance of Negative Capacitance FinFETs: Design Perspectives

Physics-based modeling of surface potential and leakage current for vertical Ga2O3 FinFET

Gallium oxide (Ga2O3) is a promising ultra-wide bandgap material offering a large bandgap (>4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga2O3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga2O3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga2O3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga2O3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga2O3 power transistors.

Physical insights of interface traps and self-heating effect on electrical response of DMG FinFETs in overlap and underlap configurations: analog/RF perspective

This paper presents a thorough analysis on analog/RF parameters including interface trap charges (ITCs) of two different densities of states (DOS) along with self-heating on the performance of DMG FinFETs in Overlap and Underlap configurations. Initially, the independent simulations for acceptor ITCs and Self-heating in conventional device reveals that performance degradation caused by Self-heating is more prominent (25.03%) than uniform acceptor ITCs (9.46%). In consecutive step, the cumulative impact of both acceptor ITCs and Self-heating on DC and RF/analog parameters are carried out. Investigation reveals that as the impact of self-heating is larger in overlap configuration, the degradation in drain current is higher in overlap configuration (45.2%, 54.5%) as compared to conventional (30.4%, 40.96%) and underlap (37.2%, 52.8%) configurations for both Uniform and Gaussian trap distributions, respectively.

Comparative analysis of logic gates based on CMOS, FINFET, and CNFET: Characteristics and simulation insights

In the evolution of integrated circuit technology, chip size and performance enhancement stand as paramount and challenging domains of progress. Yet, a dearth of foundational simulations and comparisons for introductory purposes exists. Consequently, this study delves into an introduction of distinct advanced integrated circuit (IC) technologies: CMOS, FinFET, and CNTFET, dissecting their merits and limitations. Subsequently, a preliminary simulation is executed to authenticate specific characteristics inherent to these IC technologies. Discoveries indicate that as IC transistors scale down, there are marked improvements in transistor performance, encompassing aspects such as switching speed, noise immunity, power efficiency, and heat dissipation. Further, a simulation grounded on a NAND gate substantiates certain traits in CMOS and FinFET, specifically switching speed, propagation delay, and noise margin. The results illustrate a superior performance of FinFET over CMOS. Additionally, as CMOS technology scales, its efficacy enhances. Nonetheless, the present research and simulations hold potential uncertainties and constraints, paving avenues for more refined investigations in the future.

Performance Enhancement of Dual Material Gate Junctionless FinFETs using Dielectric Spacer

In this work, a detailed investigation is done on the effectiveness of various spacer materials having different spacer lengths (LSP), in improving the performance of Dual-Material Gate-Junctionless FinFET (DMG-JLFinFET). Various performance metrics, such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), ON current (ION), OFF current (IOFF), ratio of ION to IOFF (ION/IOFF), and tunneling current (Itunn), are closely monitored at gate lengths (Lg) down to 10 nm. DIBL degradation of 3.46 mV/V and SS degradation of 4.97 mV/dec are observed when Lg scales down from 30 nm to 10 nm. Except for the case of Itunn, other performance metrics improve with an increase in dielectric constant and length of spacer materials. The optimum performance of DMG-JLFinFET with a channel length of 10 nm is obtained when LSP is 5 nm. Enhancement in analog performance metrics is observed when high κ materials are used as spacers. Transconductance Generation Factor (TGF) improves from 35.86 V−1 to 47.4 V−1 and intrinsic gain increases from 6.93 dB to 11.98 dB when high κ dielectric materials like TiO2 are incorporated as spacers in a DMG-JLFinFET.

Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5 nm Technology: A Simulation Study

Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5 nm Technology: A Simulation Study

Temperature dependent characteristics of β -Ga2O3 FinFETs by MacEtch

Understanding the thermal stability and degradation mechanism of β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) is crucial for their high-power electronics applications. This work examines the high temperature performance of the junctionless lateral β-Ga2O3 FinFET grown on a native β-Ga2O3 substrate, fabricated by metal-assisted chemical etching with Al2O3 gate oxide and Ti/Au gate metal. The thermal exposure effect on threshold voltage (Vth), subthreshold swing (SS), hysteresis, and specific on-resistance (Ron,sp), as a function of temperature up to 298 °C, is measured and analyzed. SS and Ron,sp increased with increasing temperatures, similar to the planar MOSFETs, while a more severe negative shift of Vth was observed for the high aspect-ratio FinFETs here. Despite employing a much thicker epilayer (∼2 μm) for the channel, the high temperature performance of Ion/Ioff ratios and SS of the FinFET in this work remains comparable to that of the planar β-Ga2O3 MOSFETs reported using epilayers ∼10–30× thinner. This work paves the way for further investigation into the stability and promise of β-Ga2O3 FinFETs compared to their planar counterparts.

A comparative study on performance of junctionless Bulk SiGe and Si FinFET

In this paper, the n-type and p-type SiGe junctionless bulk FinFET (SiGe JL-FinFET) with a high Ge mole fraction (xF>0.8) was studied for characteristics of a single device and the CMOS logic circuit using 3D numerical simulation. A comparison study between SiGe JL-FinFET and Si JL-FinFET under 1×1019 to 5×1019 doping concentrations. The SiGe JL-FinFET exhibits a 28% and 9% enhancement of hole and electron mobility, thus the saturation current, transconductance, intrinsic gain, and intrinsic delay are improved up to 38%, 26%, 45% and 27% in the SiGe-based device as compared to the Si-based device. Due to the higher mobility and lower gate capacitance of SiGe JL-FinFET, the rise time, fall time, propagation delay, and maximum operating frequency of the CMOS inverter are also improved up to 34%, 13%, 9%, and 20%, respectively, compared to their Si-based counterparts. This SiGe junctionless device has a simple fabrication process and improvements in analog and digital performance at the sub-5 nm technology node, making this device a promising architecture for high-performance CMOS logic applications.

Study on Negative Bias Temperature Instability Induced Degradation of P-Type FinFETs by Distinguishing Fin Top and Fin Sidewalls

In this work, the components of fin top and fin sidewalls of tri-gate fin field-effect transistor (FinFET) were distinguished and extracted by a proposed method to find out the characteristic and reliability. Poor fresh characteristic could be found on fin sidewall area due to the existed surface defects after the fabrication the Si etching process. After NBTI stress, larger VTH shift and severe SS degradation reveals worse reliability on fin top area. The result indicates that the poor initial characteristics of the fin sidewalls will reduce the performance of tri-gate FinFETs, but the poor reliability of the fin top determines the overall degradation of the device.

Liquid Gate and Back Gate Capacitive Coupling Effects in pH Sensing Performance of FinFETs

Liquid Gate and Back Gate Capacitive Coupling Effects in pH Sensing Performance of FinFETs

(Digital Presentation) Characterization and Compression Technology of Real 3D Corner Residue Between Dummy Gate and Formed Fin During an Advanced Inductive Coupled Plasma (ICP) Gate Etch Process in Advanced FinFET

3-Dimesional corner residue between Fin and gate bottom plays a key role in gate profile definition and device performance, while the characterization and compression remain challenging due to shortage of analysis technology and decreasing gate/Fin pitch. In this work, cross-section and planar TEM/STEM are adopted together to measure the real corner size. Gate profile loading along Fin is discussed based on the characterizations and further optimized by tuning processes. Several methods including sidewall passivation and ion bombardment modification has been introduced. An excellent FinFET performance is presented, together with a detailed mechanism.

Benchmarking of Analog/RF Performance of Fin-FET, NW-FET, and NS-FET in the Ultimate Scaling Limit

In this work, we examine and benchmark the analog/RF performance metrics of silicon-based multigate devices, such as Fin-FET, gate-all-around nanowire (NW)-FET, and gate-all-around nanosheet (NS)-FET, in the ultimate scaling limit of sub-5-nm technology node. The performance analysis of multigate devices is done using a fully calibrated 3-D technology computer-aided design (TCAD) simulation based on self-consistent solutions of Poisson’s equation, drift-diffusion transport equation, and carrier continuity equation with quantum correction terms for accounting band-to-band tunneling and confinement effects. Our performance benchmarking suggests that NS-FET with (100) surface orientation is a more favorable candidate over NW-FET and Fin-FET for analog/RF applications with higher voltage gain (32 V/V), higher peak cutoff frequency (373 GHz), and higher maximum oscillation frequency (389 GHz) at the 5-nm technology node. The performance benefits of NS-FET are found to be retained by decreasing the channel length, increasing the effective device width, and stacking the multichannel. Furthermore, our studies identify the proper directions to optimizations for achieving high-frequency and high-gain RF operations with multigate devices.

Modeling and characterization of optimal nano-scale channel dimensions for fin field effect transistor based on constituent semiconductor materials

This study aims to design an optimal nano-dimensional channel of fin field effect transistor (FinFET) on the basis of electrical characteristics and constituent semiconductor materials (Si, GaAs, Ge, and InAs) to overcome issues regarding the shrinking of dimensions and ensure the best performance of FinFETs. This objective has been achieved by proposing a new scaling factor, K, to simultaneously shrink the physical scaling limits of channel dimensions for various FinFETs without degrading their performance. A simulation-based comprehensive comparative study depending on four variable parameters (length, width, oxide thickness of the channel, and scaling factor) was carried out. The influence of changing channel dimensions on the performance of each type of FinFET was evaluated according to four electrical characteristics: i) ON-state/OFF-state current (ION/IOFF) ratio, ii) subthreshold swing (SS), iii) threshold voltage, and iv) drain-induced barrier lowering. The well-known multi-gate field-effect transistor (MuGFET) simulation tool for nanoscale MuGFET structure was utilized to conduct experimental simulations under the considered conditions. The obtained simulation results showed that the optimal channel dimensions for the best performance of all considered FinFET types were achieved at a minimal scaling factor K=0.125 with 5 nm length, 2.5 nm width, and 0.625 nm oxide thickness of the channel.

Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET

In this article, an analytical Subthreshold Drain Current model has been developed for Negative Capacitance Junctionless FinFET (NC-JL FinFET). To obtain the subthreshold current model for NC-JL FinFET the drift-diffusion equation is solved by including negative capacitance effect through LK equation and further utilized to attain the expression of subthreshold slope (SS). The influence of the fringing field due to source/drain spacer on the subthreshold current has been included in the model. The model predictions turn out to be in fair agreement with numerical simulation results. The performance of NC-JL FinFET is also examined for different technology nodes. Also, the influence of physical parameters like ferroelectric thickness, gate dielectric constant, fin thickness, spacer length etc. has also been analyzed. Further, the SS is also examined for variations in several device design parameters. It has been revealed that the NC-JL FinFET improves subthreshold current and SS by almost 80% and 16.7%, respectively as compared to JL FinFET.

Impact of gate dielectric on overall electrical performance of Quadruple gate FinFET

Impact of gate dielectric on overall electrical performance of Quadruple gate FinFET