Abstract
3-Dimesional corner residue between Fin and gate bottom plays a key role in gate profile definition and device performance, while the characterization and compression remain challenging due to shortage of analysis technology and decreasing gate/Fin pitch. In this work, cross-section and planar TEM/STEM are adopted together to measure the real corner size. Gate profile loading along Fin is discussed based on the characterizations and further optimized by tuning processes. Several methods including sidewall passivation and ion bombardment modification has been introduced. An excellent FinFET performance is presented, together with a detailed mechanism.
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