Performance Of Digital Systems Research Articles

A novel JFG detection-decoding approach of a vertical shuffle scheduling for iterative MIMO receivers with NB-LDPC codes

MIMO systems exploit multi-path propagation in a rich broadcast environment to improve throughput and performance of digital communication systems. The correspondent demappers require additional computational complexity. In this paper, a new detection-decoding approach based on vertical shuffle scheduling is proposed. Space exploration for the maximum likelihood detection is reduced to a dynamic region that surrounds the received symbol. Thus, a dynamic approach is proposed to detect the closest point of the channel observation without calculating all the candidate symbols in a constellation. In addition, a novel method based on EXIT chart study is proposed to find the sufficient number of neighboring points to search around a local minimum and then compute by recursion their Euclidean distances. Compared to the conventional Maximum Likelihood detector, the proposed algorithm allows a reduction in the computational complexity, in terms of number of multiplication, reaching 98%. The simulation results show that the proposed algorithm outperforms the state-of-the-art algorithms like MMSE, sphere decoding, DBTC and DaVinci codes.

Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications

Approximate computing has emerged as an efficient design methodology for improving the performance and power-efficiency of digital systems by allowing a negligible loss in the output accuracy. Dedicated hardware accelerators built using approximate circuits can solve power-performance trade-off in the computationally complex applications like deep learning. This paper proposes an approximate radix-4 Booth multiplier and hardware accelerator for deploying deep learning applications on power-restricted mobile/edge computing devices. The proposed accelerator uses approximate multiplier based parallel processing elements to accelerate the workloads. The proposed accelerator is tested with matrix–vector multiplication (MVM) and matrix–matrix multiplication (MMM) workloads on Zynq ZCU102 evaluation board. The experimental results show that the average power consumption of the proposed accelerator reduces by 34% and 40% for MVM and MMM respectively, as compared to the conventional multiply-accumulate unit that was used in the literature to implement similar workloads. Moreover, the proposed accelerator achieved an average performance of 5 GOP/s and 42.5 GOP/s for MVM and MMM respectively at 275 MHz, which are 14× and 5× respective improvements over the conventional design.

Performance of digital data acquisition system in gamma-ray spectroscopy

Performance of digital data acquisition system in gamma-ray spectroscopy

Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications

This paper presents the implementation and design of Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computational speed multiplier plays a key role in performance of digital system. But the major drawback is it consumes more power , area and delay. To enhance the performance and decrease the area consumption and delay there are many algorithms and techniques. In this paper we designed a radix-8 Booth Multiplier using two parallel prefix adders and compared them for best optimized multiplier. The number of parital products generation can be reduced by n/3 by using radix-8 in the multiplier encoding. To further reduce the additions we have used booth recoding mechanism .We have implemented the design using Kogge stone adder and Brent kung adder. We observed that by using parallel prefix adders reduces the delay further more which results in significant increase in speed of the digital systems. The simulation results are carried out on XILINX VIVADO software.

Simulation is essential for embedded control systems with task jitter

Sampling or task jitter affects the performance of digital control systems but realistic simulation of this effect has not been possible to date. Our previous work has developed a novel method to simulate sampling jitter in MATLAB/Simulink simulation software where the jitter is generated randomly. What has been missing is a way to capture sampling jitter from a target platform and then feed this timing information into the simulation. This paper presents a low-cost and novel solution to these problems. The method uses an Arduino board to capture task jitter from two different hardware platforms with multiple stressing conditions. Then the recorded performance data is used to drive realistic simulations of a control system. Measurement shows that the task jitter data does not follow any specific random distribution such as Gaussian or Uniform. Furthermore, very occasional timing patterns, which may not be picked up while testing a real system, can result in extreme controller responses. This novel method allows comparisons of different platforms and reduces the effort required to choose the most appropriate platform for full implementation.

RAW Image Quality Evaluation Using Information Capacity

In this article, we propose a comprehensive objective metric for estimating digital camera system performance. Using the DXOMARK RAW protocol, image quality degradation indicators are objectively quantified, and the information capacity is computed. The model proposed in this article is a significant improvement over previous digital camera systems evaluation protocols, wherein only noise, spectral response, sharpness, and pixel count were considered. In the proposed model we do not consider image processing techniques, to only focus on the device intrinsic performances. Results agree with theoretical predictions. This work has profound implications in RAW image testing for computer vision and may pave the way for advancements in other domains such as automotive or surveillance camera.

Effect of Epidemic Interference on the Performance of M-ASK, M-PSK and M-QAM Modulation Schemes

This article presents a study on the performance of different digital modulation systems in the presence of epidemic interference. This type of interference is caused by the fast increase in the number of users in a system at a given time. The epidemic interference can be modeled as a non-stationary stochastic process, which presents random power levels over time. In a previous work, the authors assessed the effect of the epidemic interference on the performance of BPSK, QPSK, and M-QAM systems. The present paper extends the previous results for MASK and M-PSK systems. Furthermore, numerical results from Monte Carlo simulations are presented for all evaluated digital modulation systems.

Design of Simulation for Time-Division Multiplexing Digital Optimal Frequency Band Transmission System

This paper designs a simulation experiment model of the overall structure of time-division multiplexing digital optimal frequency band transmission system based on MATLAB simulation platform. The parameters of each module in the simulation model are set. The working process and performance of the time-division multiplexing digital optimal band transmission system are simulated. The simulation results show that the digital optimal band transmission system achieves the best transmission receiving conditions and performance, and the designed time-division multiplexing optimal digital band transmission simulation system achieves its functions. The research in this paper will help to improve the level of digital communication technology and to understand the structure of time-division multiplexing digital optimal band transmission system.

Distributed Load Testing System in Continuous Integration

The digital system performance is a separate engineering science that includes approaches and practices for building and optimizing systems at all levels – from physical devices, network, to writing highly efficient algorithms. At the same time, any digital solution that is designed and built should be tested, preferably under real conditions, including performance testing or as it is often called load testing.Performance testing is designed to simulate the real usage conditions of the system and load on it in order to find out its potential bottlenecks.However, to implement this type of testing without special software tools is almost impossible. The performance testing system itself should also meet certain criteria and requirements, the implementation of which will make possible an effective testing. Thus, to test large (including distributed) information solutions, it is necessary to build a distributed system for its load. In addition, it may be necessary to create such a load simultaneously, for example, from different continents.Moreover, large-scale testing produces large amounts of resulting data that need to be collected and tracked in real, allowing to respond quickly to errors or other problems.The relevance of this topic is that, despite the presence on the market of commercial tools for such testing, it is often necessary to build own (project specific) system to display either more required metrics, or the inability to use third-party systems or budget restrictions, or all together.This paper explores the possibility of building such a distributed solution for performance testing using open-source tools such as Gatling, InfluxDB, Grafana, Logstash, Docker and Jenkins. Gatling is the main tool for load testing, but its open-source version does not allow to implement scaled testing “out of the box”. The main limitation is that even if you run several test processes from different servers at the same time, the report will be generated separately on each one and will not show the overall picture.This problem has been solved by using such a tool as Logstash which is described in this paper. Additionally, this solution has been integrated into the continuous integration based on Jenkins service and successfully tested with centralized real-time reporting using Grafana service.Manscript received 05.06.2020

Introduction of a new parameter for evaluation of digital radiography system performance

Background:The aim of this study was to compare the image quality and radiation doses in various digital radiography systems using contrast-detail radiography (CDRAD) phantom.Methods:The image quality and radiation dose for seven different digital radiography systems were compared using the CDRAD phantom. Incident air kerma (IAK) values were measured for certain exposure settings in all digital radiography systems. The images from the CDRAD phantom were evaluated by three observers. The results were displayed in the form of a contrast-detail (CD) curve. In addition, the inverse image quality figure (IQFinv)-to-IAK ratios were used for quantitative comparison of different digital radiography system performance.Results:Results of this study showed that the CD curves cannot be suitable criterion for determining the performance of digital radiography systems. For this reason, IQFinv-to-radiation dose (IAK) ratios in a fixed radiation condition were used. The highest performance in terms of producing high-quality images and low radiation dose was related to X-ray unit 1 and the lowest performance was for X-ray unit 5.Conclusion:The ratio of IQFinv to IAK for performance evaluation of digital radiography systems is an innovation of this study. A digital radiography system with a higher IQFinv-to-IAK ratio is associated with lower patient dose and better image quality. Therefore, it is recommended to equip the new imaging centers with the systems that have higher IQFinv-to-IAK ratios.

Research on HEVC screen content coding and video transmission technology based on machine learning

With the complexity of the 5 G network environment and the diversified requirements for video transmission, multimedia content transmission in different channel environments is a direction worth studying in order to achieve good performance of digital media content transmission systems in an open network environment. Based on the code stream structure characteristics of screen content in HEVC, this paper has proposed a joint source channel coding (JSCC) scheme to study the transmission of compressed video in wireless channels. Combined with the clustering algorithm from the field of artificial intelligence in the environment of wireless channel classification problem, the parameters of the wireless channel and the influencing factors can be used to reduce the noise and then use the FCM (Fuzzy C-Means) clustering algorithm to classify the channel environment. According to the channel status, optimize the current remaining resources and implement channel coding through LDPC codes. By analyzing and minimizing the end-to-end distortion model, the adaptive bit rate allocation further guarantees the quality of the reconstructed video.

Performance Analysis of Multipliers Using Modified Gate Diffused Input Technology

The primitive constraints in any VLSI system design are power, delay and area. Systems based on CMOS logic consume more power and area. Higher power dissipation will have a direct effect on the lifetime and performance of digital systems. Adders and multipliers form the core of almost all the digital systems like Microprocessor, Digital Signal Processors (DSPs), etc., so the adders and multipliers need to be optimized in terms of power, area and delay for an efficient and cost-effective processor design. This paper presents an approach for implementing 8-bit Array multiplier, Wallace Tree multiplier and Vedic multiplier using modified Gate Diffusion Input (m-GDI) technology and comparative analysis against area, power and delay. From the analysis, it is found that multipliers, which are built on m-GDI logic, occupy less area, dissipate less power and experience less delay than the multipliers based on CMOS logic, GDI logic and Booth multiplier. Also among the three m-GDI-based multipliers, Vedic multiplier performs better in terms of area, speed and power than array multiplier and Wallace tree multiplier.

WITHDRAWN: Practical methods for characterizing the optical performance of digital camera-based imaging systems: image processing application using ImageJ

Abstract In this paper, practical and simple methods for characterizing the optical performance of a digital CCD camera equipped with a zoom lens using test targets projected by a Newtonian collimator coupled to an integrating sphere and a halogen light source are presented. The presented methods include the evaluation of the CCD camera system modulation transfer function (MTF), uniformity, dynamic range, linearity and signal-to-noise ratio (S/N) properties in the visible region of the spectrum. Through out this work image processing for the recorded target images is performed using ImageJ. In addition, the paper presents a comparison between MTF measurements collected with a 1951-USAF resolution test target and a slanted edge test target. Finally, simple mathematical expressions for the measured optical system performance properties are provided. The presented optical system characterization methods can provide researchers with the needed data when a CCD or CMOS digital camera is integrated with a lens system.

Practical Methods for Characterizing the Optical Performance of Digital Camera-Based Imaging Systems

In this paper, practical and simple methods for characterizing the optical performance of a digital CCD camera equipped with a zoom lens using test targets projected by a Newtonian collimator coupled to an integrating sphere and a halogen light source are presented. The presented methods include the evaluation of the CCD camera system modulation transfer function (MTF), uniformity, dynamic range, linearity, and signal-to-noise ratio (S/N) properties in the visible region of the spectrum. Through out this work image processing for the recorded target images is performed using ImageJ. In addition, the paper presents a comparison between MTF measurements collected with a 1951-USAF resolution test target and a slanted edge test target. Finally, simple mathematical expressions for the measured optical system performance properties are provided. The presented optical system characterization methods can provide researchers with the needed data when a CCD or CMOS digital camera is integrated with a lens system.

A New Frame Synchronization Algorithm for Linear Periodic Channels With Memory

Identifying the start time of a sequence of symbols received at the receiver, commonly referred to as frame synchronization, is a critical task for achieving good performance in digital communications systems employing time-multiplexed transmission. In this work we focus on frame synchronization for linear channels with memory, in which the channel impulse response is periodic and the additive Gaussian noise is correlated and cyclostationary. Such channels appear in many communications scenarios, including narrowband power line communications and interference-limited wireless communications. We derive frame synchronization algorithms based on simplifications of the optimal likelihood-ratio test, assuming the channel impulse response is unknown at the receiver, which is applicable to many practical scenarios. The computational complexity of each of the derived algorithms is characterized, and a procedure for selecting nearly optimal synchronization sequences is proposed. The algorithms derived in this work achieve better performance than the noncoherent correlation detector, and, in fact, facilitate a controlled tradeoff between complexity and performance.

A Digital WATERMARKING Algorithm with High Efficiency Based on DWT and LSB

In order to improve the performance of digital watermarking system, a novel watermarking algorithm for blind watermarking based on the least significant bits and support vector machine. Firstly, digital watermarking was pretreated by binaryzation. Subsequently, the watermark signal is embedded into least significant bit of the low frequency coefficients by the Discrete Wavelet Transformation. Finally, the trained support vector machine is used to extract the attacking vetors. Simulation results show that the watermarking algorithm has good invisibility and robustness to general attacks and geometrical distortions.

Characterization of a Gm-C Filter Based on CNTFETs for Use in Digital Audio Broadcasting Systems

Anti-aliasing filters play an important role in analog front-end circuits, and their suitable design can improve the performance of digital audio broadcasting systems. In this paper, a Gm-C anti-aliasing filter based on carbon nanotube field effect transistors (CNTFETs) is proposed. Using CNTFETs provides low power consumption and appropriate frequency response. Simulation results show that these characteristics are widely dependent on the physical parameters of CNTFETs. The effects of chirality, the number of CNTs in each CNTFET, and distance of CNTs from each other on power consumption and frequency response are investigated. Among these parameters, the chirality and number of CNTs respectively have nonlinear and linear relationships with both power consumption and cutoff frequency. On the other hand, changing the distance between CNTs has the least effect on the output characteristics. Also, the output features of the filter for different gate oxides and channel lengths are studied. The overall result of the simulations demonstrates that the filters based on CNTFETs are promising candidates to be used in future nano-scale integrated circuits.

Counteracting the Dynamical Degradation of Digital Chaos by Applying Stochastic Jump of Chaotic Orbits

The performance of digital chaotic systems in secure communications and cryptographic applications is significantly degraded due to the limited precision of digital computational devices that are used to implement digital chaotic systems. However, regardless of the initial value, the digital chaotic map employed in these applications converges to several periodic orbits. Thus, a periodic orbit search algorithm (POSA) can be designed to accurately locate fixed points and limit cycles. In addition, an effective method based on stochastic jumps of chaotic orbits is proposed to counteract the performance degradation of digital chaos. Numerical simulations were performed to assess the effectiveness and feasibility of the proposed method in terms of autocorrelation, phase space inspection, approximate entropy and periodicity analysis. Furthermore, comparison with other existing methods is presented to show the competitiveness of the proposed scheme. Finally, a pseudorandom bit generator (PRBG), with desirable statistical properties, is constructed for chaos cryptography and other applications.

On the Performance of $\alpha$ –$\eta$ –$\kappa$ –$\mu$ Fading Channels

In this letter, we study the performance of digital communication systems considering the general and versatile α-η-κ-μ fading model, which was recently proposed in the literature. To this end, novel and exact expressions for the outage probability, average channel capacity, and average error rate of a variety of modulation formats are derived for arbitrary values of the fading parameters. Moreover, an asymptotic outage analysis is carried out in order to get further insight as to how the fading parameters impact system performance. Monte Carlo simulations are provided to validate the proposed analytical framework.

Performance evaluation of an ultra-high speed adder based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is among the most promising nanotechnologies as the substitution for the current metal oxide semiconductor field effect transistor based devices. Therefore, lots of attention have been paid to different aspects to improve the efficiency of QCA circuits. In this way, the adder circuits are widely investigated since their performance can directly affect the whole digital system performance. In this paper, a new ultra-high speed QCA full adder cell is proposed based on multi-layer structures. The proposed full adder cell is simple in design using 3-input Exclusive-OR (TIEO), which computes the Sum bits and Majority gate, which computes the Carry bits. To verify the efficacy of the presented full adder cell, it is considered, the main constructing block in 4-bit ripple carry adder circuit. Hence, significant improvements in terms of area and cell count have been achieved. Particularly simulation results show 20% and 1.8% reduction respectively in the area and cell count overhead. Detailed performance evaluation and structural analysis are performed in different aspects to authenticate the proposed circuits (one-bit and 4-bit) having superb performance in comparison to previously reported works. QCADesigner CAD tool has been used to verify the correct functionality of the proposed architectures.