Cache Performance Analysis Research Articles

Content Pushing Over Idle Timeslots: Performance Analysis and Caching Gains

Caching holds the promise of scaling the service capability of next-generation radio access networks (RANs), thereby attracting much recent attention in the era of 6G research. To enable caching, popular content items should be proactively pushed to the user ends (UEs) in the placement phase. In practice, most content placement is only allowed to exploit idle spectrum or timeslot that is not occupied by any on-demand transmissions. In this case, however, the performance analysis and optimizations of practical caching gains remain open. In this paper, we are interested in how pushing, as a secondary service, improves the overall performance in terms of energy efficiency and latency reduction. To this end, we formulate a Markovian queueing model, the caching gains of which are optimized via linear programming (LP) with acceptable computational complexity. Our work demonstrates that the peak traffic load due to burst on-demand transmissions, as primary services, can be effectively offloaded by pushing over idle timeslots, leading to substantially reduced power consumption and queueing delay.

Performance Estimation and Evaluation Framework for Caching Policies in Hierarchical Caches

The emergence of information-centric network (ICN) architectures has attracted a flurry of renewed research interest in caching policies and their performance analysis. One important feature ICNs offer that is distinct from classical computer caches is a distributed network of caches, namely, a cache network which poses additional challenges both in terms of practical cache management issues and performance analysis. Much attention of the research community has focused on performance analysis of cache networks under various caching policies. However, the issue of how to evaluate and compare caching policies for cache networks has not been adequately addressed. In this paper, we propose a novel and general framework for evaluating caching policies in a hierarchical network of caches. We introduce the notion of a hit probability/rate matrix, and employ a generalized notion of majorization as the basic tool for evaluating caching policies for various performance metrics. We discuss how the framework can be applied to existing caching policies, and conduct an extensive simulation-based evaluation to demonstrate the utility and accuracy of our framework.

L2 cache performance analysis for MPSoC by tag – comparision

Memory systems in many applications are becoming increasingly large, contributing to many challenges in the memory management that has led to many method to manage memory. The tag comparison consumes large amount of cache energy. Current methods provide tag comparison cache or failure of the expected cache. Here is proposed an idea based on new call Comparing Tag stages, filter bloom is presented to improve the efficiency of the cache to predict failure and partial tag comparison for the cold line of verification and full comparison check for direct labels. Moreover, the administration of the cache that is filled with cache lines occurs when there is a cache miss. Today's embedded applications use MPSoC. The MPSoC consists of the following ie more than one processors, shared memory among the processors available and a global off-chip memory. Planning of the activities of an integrated application processor and memory partition between processors are two main critical problem. Here, for an integrated application, both task scheduling and partitioning the integrated available L2 cache to reduce the runtime approach is used.

An Analytical Model for Loc/ID Mappings Caches

Concerns regarding the scalability of the interdomain routing have encouraged researchers to start elaborating a more robust Internet architecture. While consensus on the exact form of the solution is yet to be found, the need for a semantic decoupling of a node's location and identity is generally accepted as a promising way forward. However, this typically requires the use of caches that store temporal bindings between the two namespaces, to avoid hampering router packet forwarding speeds. In this article, we propose a methodology for an analytical analysis of cache performance that relies on the working-set theory. We first identify the conditions that network traffic must comply with for the theory to be applicable and then develop a model that predicts average cache miss rates relying on easily measurable traffic parameters. We validate the result by emulation, using real packet traces collected at the egress points of a campus and an academic network. To prove its versatility, we extend the model to consider cache polluting user traffic and observe that simple, low intensity attacks drastically reduce performance, whereby manufacturers should either overprovision router memory or implement more complex cache eviction policies.

A Performance Analysis of Semantic Caching for XML Query Processing

Caching is important for any system attempting to achieve high performance. The semantic caching is an approach trying to benefit from the certain knowledge of data semantics. The authors expect that this information might enable reuse of semantically close data rather than exactly equal to cached data in the traditional system. However, the major obstacle for extensive application of semantic caching for any data model or query language is the computational complexity of the query containment problem, which is, in general, undecidable. In this article the authors introduce and compare three approximate conservative query matching algorithms for semantic caching of semi-structured queries. The authors then analyze their applicability for distributed query processing. Based on this analysis, the authors outline few scenarios where semantic caching can be beneficial for query processing in a distributed system of heterogeneous semi-structured information resources.

Performance analysis of in-network caching for content-centric networking

With the explosion of multimedia content, Internet bandwidth is wasted by repeated downloads of popular content. Recently, Content-Centric Networking (CCN), or the so-called Information-Centric Networking (ICN), has been proposed for efficient content delivery. In this paper, we investigate the performance of in-network caching for Named Data Networking (NDN), which is a promising CCN proposal. First, we examine the inefficiency of LRU (Least Recently Used) which is a basic cache replacement policy in NDN. Then we formulate the optimal content assignment for two in-network caching policies. One is Single-Path Caching, which allows a request to be served from routers only along the path between a requester and a content source. The other is Network-Wide Caching, which enables a request to be served from any router holding the requested content in a network. For both policies, we use a Mixed Integer Program to optimize the content assignment models by considering the link cost, cache size, and content popularity. We also consider the impact of link capacity and routing issues on the optimal content assignment. Our evaluation and analysis present the performance bounds of in-network caching on NDN in terms of the practical constraints, such as the link cost, link capacity, and cache size.

Location Cache Design and Performance Analysis for Chip Multiprocessors

Recent research at Intel suggests that chips with hundreds of processor cores are possible in the not-so-distant future. As the number of cores grows, so does the size of the cache systems required to allow them to operate efficiently. Caches have grown to consume a significant percentage of the power utilized by a processor. In this research, we extend the concept of location cache to support chip multiprocessors (CMPs) systems in combination with low-power L2 caches based upon the gated-ground technique. The combination of these two techniques allows for reductions in both dynamic and leakage power consumption. In this paper, we will present an analysis of the power savings provided by utilizing location caches in a CMP system. The performance of the cache system is evaluated by extending the capability of CACTI and Simics using the SPLASH-2 and ALPBench benchmark suites. These simulation results demonstrate that the utilization of location caches in CMP systems is capable of saving a significant amount of power over equivalent CMP systems that lack location caches.

Can models of scientific software-hardware interactions be predictive?

Abstract Sparse scientific codes face grave performance challenges as memory bandwidth limitations grow on multi-core architectures. We investigate the memory behavior of a key sparse scientific kernel and study model-driven performance evaluation in this scope. We propose the Coupled Reuse-Cache Model (CRC Model), to enable multilevel cache performance analysis of parallel sparse codes. Our approach builds separate probabilistic application and hardware models, which are coupled to discover unprecedented insight into software-hardware interactions in the cache hierarchy. We evaluate our model's predictive performance with the pervasive sparse matrix-vector product kernel, using 1 to 16 cores and multiple cache configurations. For multi-core setups, average L1 and L2 prediction errors are within 3% and 6% respectively.

Performance Analysis of Profile-Based Location Caching with Fixed Local Anchor for Next-Generation Wireless Networks

Although a lot of works for location management in wireless networks have been reported in the literature, most of the works have been focused on designing per-user-based strategies. This means that they can achieve the performance enhancement only for a certain class of mobile users with a specific range of CMR (call-to-mobility ratio). However, these per-user-based strategies can actually degrade the performance if a user's CMR changes significantly.Therefore, an efficient uniform location management strategy, which can be commonly applied to all mobile users regardless of their CMR, is proposed and analyzed in this paper. The motivation behind the proposed strategy is to exploit the concepts of the two well-known existing strategies: the location caching strategy and the local anchor strategy. That is, the location caching strategy exploits locality in a user's calling pattern, whereas the local anchor strategy exploits locality in a user's mobility pattern. By exploiting these characteristics of both strategies together with the profile management at the HLR (home location register), the proposed strategy can reduce the frequent access to the HLR, and thus effectively results in significant reduction in terms of the total location management cost. The analytical results also demonstrate that the proposed strategy can be uniformly applied to all mobile users, while always maintaining the performance gain over the IS-41 standard regardless of a user's CMR and the network traffic conditions.

An analysis of cache performance of multimedia applications

Multimedia applications are fast becoming one of the dominating workloads for modern computer systems. Since these applications normally have large data sets and seem to have little data-reuse, a commonly held belief is that they have poor memory behavior compared to traditional programs and that current cache architectures cannot handle them well. It is therefore important to quantitatively characterize the memory behavior of these applications in order to provide insights for future design and research of memory systems. However, very few results on this topic have been published. We analyze the cache behavior of a group of representative multimedia applications. These programs include a subset of the popular MediaBench suite and several large multimedia programs running on the Linux, Windows 98, and TruUnix operating systems. We performed extensive measurement and trace-driven simulation experiments. We then compared the memory utilization of these programs to that of the SPEC2000 applications. We found that multimedia applications actually have better cache behavior than SPEC2000 programs. The following three factors contribute to the high cache hit rates of multimedia applications: First, most multimedia applications apply block-partitioning algorithms to the input data and work on small blocks of data that easily fit in the cache. Second, within these blocks, there is significant data reuse as well as spatial locality. Third, a large number of references generated by multimedia applications are to their internal data structures, which are relatively small and can easily fit in reasonably sized caches.

Tiling, block data layout, and memory hierarchy performance

Recently, several experimental studies have been conducted on block data layout in conjunction with tiling as a data transformation technique to improve cache performance. In this paper, we analyze cache and translation look-aside buffer (TLB) performance of such alternate layouts (including block data layout and Morton layout) when used in conjunction with tiling. We derive a tight lower bound on TLB performance for standard matrix access patterns, and show that block data layout and Morton layout achieve this bound. To improve cache performance, block data layout is used in concert with tiling. Based on the cache and TLB performance analysis, we propose a data block size selection algorithm that finds a tight range for optimal block size. To validate our analysis, we conducted simulations and experiments using tiled matrix multiplication, LU decomposition, and Cholesky factorization. For matrix multiplication, simulation results using UltraSparc II parameters show that tiling and block data layout with a block size given by our block size selection algorithm, reduces up to 93 percent of TLB misses compared with other techniques. The total miss cost is reduced considerably. Experiments on several platforms show that tiling with block data layout achieves up to 50 percent performance improvement over other techniques that use conventional layouts. Morton layout is also analyzed and compared with block data layout. Experimental results show that matrix multiplication using block data layout is up to 15 percent faster than that using Morton data layout.

Performance analysis of caching and prefetching strategies for palmtop-based navigational tools

Navigational tools that assist travelling people when they visit new areas are becoming increasingly common. Some of these tools are designed to be used with small portable devices (palmtops and also cellular phones) to give users more flexibility in their utilization (e.g. while walking in a town). The limited storage capacity of such devices makes it unrealistic to think that all the useful information can be stored in such devices, apart from the most basic one, like road maps and location of some points of interests. Other more detailed information should be loaded on the fly when needed, e.g., by using a wireless connection to some remote information service. However, this could cause unacceptably high latency to get the information. Another important factor that must be taken into account is the energy consumption caused by the access to the remote information service through a wireless link. Hence, the design of an information service that integrates the capabilities of palmtop-based navigational tools must be carefully designed around the goals of reducing both the perceived latency and the consumed energy. To this purpose, we investigate the use of caching and prefetching techniques. We present analytical and numerical results obtained by defining a probabilistic model of the typical utilization scenario of the considered service and corresponding cache management policies.

A user-access model-driven approach to proxy cache performance analysis

World-Wide Web usage has experienced tremendous growth in recent years. This growth has resulted in a significant increase in network and server loads that have adversely affected user response times. Among many viable and available approaches to reducing user response time, Web caching has received considerable attention. The purpose of this paper is to present an empirically derived model of Internet user-access activity, and to demonstrate its usefulness for conducting model-driven discrete simulation studies of cache performance analysis. The user-access model is shown to be a reasonable representation of Internet activity, and the user-access approach to cache performance analysis is shown to be a favorable alternative to trace-driven simulation. A report on the accuracy of the model and a summary of the findings are presented.

An analysis of cache performance for a hypercube multicomputer

Multicomputer cache simulation results derived from address traces collected from an Intel iPSC/2 hypercube multicomponent are presented. The primary emphasis is on examining how increasing the number of processor nodes executing a parallel application affects the overall multicomputer cache performance. The effects on multicomputer direct-mapped cache performance of application-specific data partitioning, data access patterns, communication distribution, and communication frequency are illustrated. The effects of system accesses on total cache performance are explored, as well as the reasons for application-specific differences in cache behavior for system and user accesses. Comparing user code results with full user and system code analysis reveals the significant effect of system accesses, and this effect increases with multicomputer size. The time distribution of an application's message-passing operations is found to more strongly affect cache performance than the total amount of time spent in message-passing code. >

Efficient trace-driven simulation methods for cache performance analysis

Efficient trace-driven simulation methods for cache performance analysis

Quick and easy cache performance analysis

Quick and easy cache performance analysis

Efficient trace-driven simulation method for cache performance analysis

We propose improvements to current trace-driven cache simulation methods to make them faster and more economical. We attack the large time and space demands of cache simulation in two ways. First, we reduce the program traces to the extent that exact performance can still be obtained from the reduced traces. Second, we devise an algorithm that can produce performance results for a variety of metrics (hit ratio, write-back counts, bus traffic) for a large number of set-associative write-back caches in just a single simulation run. The trace reduction and the efficient simulation techniques are extended to parallel multiprocessor cache simulations. Our simulation results show that our approach substantially reduces the disk space needed to store the program traces and can dramatically speedup cache simulations and still produce the exact results.