Performance Analysis Of Architecture Research Articles

Parallel GPU Architecture Simulation Framework Exploiting Architectural-Level Parallelism with Timing Error Prediction

The performance analysis and study of large-scale many-core processor architectures require fast and highly accurate simulation techniques in order to reduce time consumption. State-of-the-art graphics processing units (GPUs), which are used extensively as coprocessors in the high-performance-computing area, also require fast simulation techniques because they have massively complex microarchitectures with thousands of processing elements. At present, however, GPU simulators do not have sufficient simulation speed for advanced software and architecture studies. In this study, we propose a new parallel simulation framework and a new parallel simulation technique for improving the simulation speed of GPUs. The proposed framework facilitates multithreaded simulation by exploiting the architectural-level parallelism and execution model parallelism of GPUs. In addition, an error predictive synchronization scheme based on a timing error prediction mechanism is used to minimize the cycle errors and simulator slowdown during parallel simulations. The experimental results obtained using a simulator with the proposed framework showed that the proposed technique provided a speedup of up to 8.9 times compared with an existing single-thread-based GPU simulator on a 16-core machine.

Performance Analysis of NOC and Bus-Based Architecture

A number of research studies have demonstrated the feasibility and advantages of Network-on-Chip (NOC) over traditional bus-based architectures. This paper tells the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NOC, and provides specific data about Arteris’ NOC, the first commercial implementation of such architectures, using a generic design. For example, we provide detailed comparisons of scalability, performance and area of traditional busses or crossbars vs. Arteris’ NOC.

A New Methodology in Study of Effective Parameters in Network-on-Chip Interconnection’s (Wire/Wireless) Performance

Network-on-Chip (NoC) paradigm has been proposed as an alternative bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely considered. Time latency and throughput are two very critical parameters which play vital role to improve the system performance. In this work, these two elements are evaluated in both wire and wireless approaches under different conditions for networks contain 64,512 and 1024 number of cores. There are number of parameters those have direct and indirect effects on the delay and throughput, among all, these four are chosen: routing algorithm, buffer size, virtual channel and subnet. Thus this work is clustered into two general parts, in the first section the effect of algorithms and buffer size are calculated and then later on in second part when switching from wire approach to wireless, it’s shown that, virtual channel and subnet are able to influence the performance of a network on chip positively under some circumstances. We don't concentrate on approach and techniques here. Our target in this paper is to determine the critical points, trade-off and study the effect of mentioned parameters on entire system. Evaluation is done by means of Booksim and Noxim simulators which are based on system C.

Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography

Elliptic curve cryptosystems (ECC) are becoming more and more popular and are included in many standards, as they offer high security strength when compared with other conventional public-key cryptosystems, for the same key length. But the security strength of hardware implementations of ECC is challenged by side channel attacks (SCA) such as power analysis. Reversible logic circuits ideally consume zero energy, which serves as the motivation to implement cryptographic algorithms against power analysis attacks. This paper proposes two new hardware architectures for performing montgomery multiplication in GF(p) and GF(2m), as they are the power consuming operations in ECC. The two architectures are optimized to reduce the hardware cost and they are then implemented in reversible logic with reduced number of quantum cost. In this work, the reversible logic synthesis is performed with Toffoli family of reversible gates. The performance metrics of all the multipliers are analyzed and properly tabulated. Scalar multiplication on elliptic curve points, which is the core operation used in every elliptic curve cryptosystem, has been implemented in reversible logic by using the proposed reversible montgomery multipliers.

Editorial for MONET Special Issue on Networking in 5G Mobile Communications Systems: Key Technologies and Challenges

Editorial: This special issue includes eight high quality papers in the research area of Networking in 5G Mobile Communications Systems. With an ever-increasing number of mobile devices and the resulting explosive mobile traffic, 5G networking system should be re-designed by combining both communication and computation technologies. This special issue kicks off with an article on the cloudified wireless network architecture, namely BCloud-based Wireless Network: Virtualized, Reconfigurable, Smart Wireless Network to Enable 5G Technologies^, co-authored by Min Chen, Long Hu, Yin Zhang, Tarik Taleb and Zhengguo Sheng. The article reveals that 5G is a multiservice and multi-technology integrated network, meeting the future needs of a wide range of big data and the rapid development of numerous businesses, and enhancing the user experience by providing smart and customized services. Then, the authors propose a cloud-based wireless network architecture with four components, i.e., mobile cloud, cloud-based radio access network, reconfigurable network and big data centre, which is capable of providing a virtualized, reconfigurable, smart wireless network. The second article, BHybrid Architecture Performance Analysis for Device-to-Device Communication in 5G Cellular Network^, co-authored by Zhijian Lin, Zhibin Gao, Lianfen Huang, Chi-Yuan Chen and Han-Chieh Chao, first develops a new hybrid architecture concept for D2D communications, which combines ISM 2.4G spectrum as the Out-Band mode and uses Bluetooth and Wifi-Direct with the cellular spectrum as the InBand mode. And then a scheme is designed to form the Out-Band cluster and makes the following periodic signaling interaction via the Bluetooth interface. Traffic is transferred via the Wifi-Direct interface inside the cluster but carried on the cellular spectrum among the clusters. For the topic of spectrum sharing and cognitive radio techniques, the third article in the special issue, BA Cyclostationarity-Based Implicit Channel for Cognitive Radio Applications^, co-authored by Tianheng Xu, Sha Yao and Honglin Hu, provides a Cyclostationarity-based Implicit Channel (CIC), which can assist conflictavoidance coexistence for radio systems in the cognitive radio networks. The proposed implicit channel works as an add-on channel to a conventional OFDM system, which supplies extra communication opportunities without affecting the performance of the main system. Progressively, the article introduces the system model, interprets the operational principle, and manifests the modulation/demodulation scheme for the CIC technique. Afterwards, performance investigation is presented, showing the potential feasibility of the CIC technique being adopted in the future cognitive radio networks. The next article BReliable Machine-to-Machine Multicast Services with Multi-Radio Cooperative Retransmissions^ * Xiaohu Ge xhge@mail.hust.edu.cn

Hybrid Architecture Performance Analysis for Device-to-Device Communication in 5G Cellular Network

A large number of new data consuming applications are emerging in the daily routines of mobile users. Device-to-Device (D2D) communication as a new paradigm is introduced to reduce the increasing t...

Design Trade off and Performance Analysis of Router Architectures in Network-on-Chip

Abstract On chip interconnection networks simplify the challenges of integrating large number of processing elements. Routers are backbone of networks. Buffers and crossbar in router consumes significant area and power of network. Reducing buffers could lead to degradation of network performance. Dual Xbar router architecture combines buffered and bufferless feature to reduce buffer read/write energy with dual crossbars. While Switch folding technique introduced to reduce wire density and decrease muxes in crossbar by increasing resource utilization. In this paper, we propose Folded Dual Xbar architecture by combining the Dual Xbar and Folding technique in order to get advantages of both architectures. Performance of architectures is evaluated using OMNET++ platform under different load conditions. Simulation results shows that there is slight increase in throughput and reduction in buffer read/write energy by average 46% at high loads in proposed 2-Folded Dual Xbar as compared to conventional architecture. Proposed 3-Folded Dual Xbar results at least 16.6% increase in throughput as compared to conventional architecture with 43-45% reduced buffer read/write energy but slight increase in crossbar. Throughput of 3-Folded Dual Xbar decreased only by 5-7% as compared to Dual Xbar with distributed wire density advantage.

Performance analysis of mobility management architectures in cellular networks

Flattened cellular network architecture for the mobile internet is expected to meet the demands of rapidly increasing traffic from mobile users. Dynamic mobility anchoring (DMA) mechanism distributes the mobility management functions using such network architecture. In this paper, we compare DMA with a classical mobility protocol like proxy mobile IP (PMIP). A major cost factor of a mobility protocol is the management of contexts and tunnels. We propose an analytical model to compute the number of contexts and tunnels with DMA and with PMIP in a homogeneous network with random mobility of mobile nodes. The model is used under different configurations by varying the traffic loads and the capacities of access nodes in order to analyze the distributed and dynamic characteristics of DMA. The results show that the required number of contexts on an anchor node with DMA is significantly less than that required on an anchor node with PMIP and the required number of visitor contexts with DMA is significantly less in magnitude than that with PMIP for most of the configurations. The results also show that the number of required tunnels with DMA is less than those required with PMIP for most configurations.

Research on the Uncertainty Analysis of Architecture Performance

The early performance analysis of architecture can effectively avoid the risk of redesign when the performance cannot achieve the goal. As the absence of information and data in the early time, there are large numbers of uncertainties. From the analysis of uncertainty sources and quantifying combination, the performance probability integral formula can be derived, which is essential to compare the architecture performance. This formula describes uncertainties by the form of probability.

Performance analysis of WDM-PON architecture using different receiver filters

In this paper the performance effect of a 40Gb/s Wavelength-Division-Multiplexed Passive Optical Network (WDM-PON) is analyzed using different receiver filters namely Integrator filter, Bessel filter, Butterworth filter, Chebyshev filter, Inverse Chebyshev filter, Elliptic filter, Gaussian filter and Rectangular filter. The data rate and channel spacing are taken as 10Gb/s per channel and 100GHz, respectively. Among all the investigated filters, Bessel filter is considered to be the best one for WDM-PON network by the obtained BER and Q factor values.

Performance Analysis of Multilayer MIPv6 Architecture through Experimental Testbed

Mobility management is a key issue to achieve uninterrupted Internet services in IP based network. In IPv6, the mobility management is realized by its mobile version namely the Mobile IPv6 (MIPv6). The MIPv6 is further extended to Hierarchical MIPv6 (HMIPv6) to reduce handoff latency suffered by mobile nodes and signaling load incurred due to movement if nodes within the micro mobility region defined by HMIPv6. The HMIPv6 is considered as first widely accepted layered architecture for mobility management for IPv6 network. Influenced by the benefits of HMIPv6, many researchers have suggested extension of MIPv6 into multiple layers. However, there is very little work on finding optimal levels of hierarchy in such layered architecture. The focus of this paper is to evaluate the performance of a multilayer (N-layered with N as 5) MIPv6 architecture through experimental testbed. We have observed handoff latency, signaling overhead and tunneling cost and figured out the optimal levels of hierarchy that provides the best acceptable results for all the observed parameters. Since, HMIPv6 outperforms MIPv6 in terms of handoff latency and signaling cost, so we compare our results with HMIPv6. Testbed observation depicts that three levels of hierarchy in MIPv6 architecture provides optimal performance with 27 % reduction in handoff latency and 67 % reduction in signaling overhead compared to single layer architecture like Hierarchical MIPv6 (HMIPv6) protocol.

Performance Analysis of A Novel Inter-Networking Architecture for Cost-Effective Mobility Management Support

Mobile traffic is increasing a masse because of the propagation of the Internet and the development of wireless mobile technology. Accordingly, the Network Local Mobility Management (NETLMM) working group [1] of the Internet Engineering Task Force (IETF) has standardized Proxy Mobile IPv6 (PMIPv6) [2] as a protocol for accomplishing the transmissibility of mobile terminals. PMIPv6 is a network-led IP-based mobility management protocol, which can control terminal mobility without depending on the type of access system or the capability of the terminal. By combining PMIPv6 and the mobility of Session Initiation Protocol (SIP), we can establish terminal mobility and session mobility through a more effective route. The mobility function can be improved and the overlap of function reduced as compared to that in the case of independent operation. PMIPv6 is appropriate for a non-real-time service using TCP, and SIP is appropriate for a real-time service using RTP/UDP. Thus, in the case of a terminal using both services, an effective mobility management is possible only by using PMIPv6 together with SIP. In order to manage mobility in this manner, researches on PMIPv6-SIP are in progress. In line with this trend, this paper suggests a new PMIPv6-SIP architecture where when a mobile terminal conducts a handover, a network-led handover while maintaining the session without the addition of a special function or middleware is possible along with effective performance evaluation through mathematical modeling by comparing the delay and the packet loss that occur during the handover to the Pure-SIP.

서비스 연속성 지원을 위한 WiBro-WiFi 상호연동 아키텍쳐 설계 및 성능 분석에 관한 연구

서비스 연속성 지원을 위한 WiBro-WiFi 상호연동 아키텍쳐 설계 및 성능 분석에 관한 연구

Performance Analysis of Resilient FTTH Architecture with Protection Mechanism

Fiber-To-The-Home [FTTH] is an alternate technology for broadband access networks. Passive optical network (PON) is considered the most promising solution due to the relatively low deployment cost. Current time division multiplexing [TDM] PON architectures are economically feasible, are band limited. The WDM PONs currently available offers enough bandwidth for the present and also for future multimedia broadband services. The purpose of this paper is to simulate resilient access network architecture with a cable route protection function based on hybrid wavelength division multiplexing and time division multiplexing passive optical network (WDM/TDM-PON) systems. Hybrid WDM-TDM PON combines the advanced features of both TDM PON and WDM PON. The reuse of existing optical fiber cable networks allows the introduction of duplicate routes for the shared portions of PONs by using a few optical fiber cables with simple structures. In this work, the hybrid WDM/TDM PON based Ladder network is simulated and the transmission characteristics evaluated. Simulation is done by using Optsim ver.5.3.

A Survey of Design Model for Quality Analysis: From a Performance and Reliability Perspective

The use of a model for the analysis of the software quality attributes during the design phase has been gaining more attention in recent years. These models, which are peripheral in system design, are the center of quality analysis. The system design is the central focus in representing the structure and behavior of the system. Therefore, the goal of the software architecture performance and reliability analysis is to discover possible quality problems that may violate the quality requirements, which have been stated in the design. The use of an intermediate model to correlate the performance and reliability specification from the UML model and which is then transformed into an analysis model could facilitate the analysis process. This paper provides a survey of the existing intermediate metamodels from a performance and reliability perspective, through the evaluation and discussion on the similarities and differences focusing on the aspects of general concepts, modelling and analysis. The purpose of the discussion is to offer guidelines on which intermediate metamodel is appropriate for the use of quality analysis at design time as well as outline the possible space for improvement by making classifications and comparisons studies.

Performance Analysis and Experimental Demonstration of a Novel Network Architecture Using Optical Burst Rings for Interpod Communications in Data Centers

In this paper, we propose to use a novel network architecture of multiple optical burst rings to improve the interpod communications of the internal networks of data centers. In the proposed network architecture, bursty and fast-changing interpod traffic is handled by the electrical core switches, while the relatively stationary traffic is handled via optical burst rings. Compared to previously proposed hybrid optical/electrical switching schemes of using optical circuit switches, the proposed scheme offers high interpod transmission bandwidth, supports large number of pods, requires smaller connection reconfiguration time, and has better bandwidth utilization. Moreover, the proposed scheme only employs relatively low-cost commercial optical components, making it more practical for near-term implementations.

Optical interconnection reverse data vortex network: performance analysis

Multistage interconnection networks are employed in data centres to interchange information between the processors and memory elements. Data Vortex (DV) is a multistage minimum logic network which can be used in data centres. DV satisfies the requirements of the interconnection networks such as scalability and throughput. However, the latency is on higher side, and reduction in latency can lead to higher throughput. In the present paper, we describe the feasibility and performance analysis of DV architecture in reverse direction. The routing and the possible hardware model of the node switch have been discussed. We present the performance analysis of Reverse Data Vortex (RDV) architecture in terms of throughput, latency and latency distribution. A comparative study with DV on throughput, latency and latency distribution is also presented. The simulation result shows that the decrease in latency of RDV is about 50 % that of DV and this leads to an increase in injection rate of RDV to values more than two times that of DV.

Cloudlet-screen computing: a client-server architecture with top graphics performance

This paper presents a three-decoupling-boundary theory and classification for performance analysis of client-server architectures. Based on the analysis, a novel client-server architecture with top graphics performance is proposed. The client is only a display screen plus a few Human-Interface-Devices such as a mouse-keyboard-set or touchscreen with an optional mobile storage. The client is connected to a remote or nearby server cloudlet by a low latency link transferring primarily post-GPU display screen and HID data. By following exactly the same most-efficient CPU-GPU-screen graphics rendering pipeline from initial graphics primitives to final pixels as that in the traditional computer graphics architecture developed and optimised in the past decades, the architecture has higher graphics and multimedia performance than any other client-server and cloud-mobile computing architectures, e.g. VNC, Remote Desktop, VDI, Zero-client, and PCoIP. No read back of frame buffers as virtualised screen is necessary, so no CPU/GPU overhead occurs and display latency is minimised.

Performance Analysis of Neural Network Architecture Combined with DWT for Image Compression

Neural networks are significantly used in signal and image processing techniques for pattern recognition and template matching. In this work neural networks are used for image compression. In order to improve the performances image compression algorithm, DWT is combined with NN for achieving better MSE and increase in compression ration greater than 100%. NN architecture achieves maximum of 98% with use of four neurons in the hidden layer, with selection of LL sub band only the compression is improved by another 75%. The proposed architecture is analyzed for 20 images and MSE is found to be improved by a factor of 20%. Daubechies wavelet filter and Haar wavelet filters are used for DWT, input layer with one hidden layer and output layer consisting of tansig and purelin function us used for compression. The design proposed is suitable for high resolution image compression. General Terms

Trade-offs in designing High-Performance Digital Adder based on Heterogeneous Architecture

To design an efficient integrated circuit in terms of Area, Power and speed is one of the challenging task in modern VLSI design field. In the past decade numbers of research have been carried out to optimize design based on area, speed and power utilization. In this paper performance analysis of different available adder architectures has been carried out and then we proposed a Heterogeneous architecture, which composed of four different sub adders (Ripple Carry, Carry Look Ahead, Carry Skip and Carry Select Adder) to design an adder unit in order to demonstrate trade-offs between performance parameters i.e. Area, Power and speed. We consider area optimization under delay constraint, area optimization under power constraint and finally power optimization under delay constraint. All the adders are design using VHDL. To get power, delay and area report, we use XILINX 9.1 i as synthesis tool and Modelsim XE III 6.2g for simulation. FPGA-Spartan III is used for implementation.