Pentacene Thin-film Transistors Research Articles

Application of pentacene thin-film transistors with controlled threshold voltages to enhancement/depletion inverters

Oxygen plasma treatment has been carried out to control the threshold voltage in organic thin-film transistors (TFTs) having a SiO2 gate dielectric prepared by rf sputtering. The threshold voltage linearly changed in the range of −3.7 to 3.1 V with the increase in plasma treatment time. Although the amount of change is smaller than that for organic TFTs having thermally grown SiO2, the tendency of the change was similar to that for thermally grown SiO2. To realize different plasma treatment times on the same substrate, a certain region on the SiO2 surface was selected using a shadow mask, and was treated with oxygen plasma. Using the process, organic TFTs with negative threshold voltages and those with positive threshold voltages were fabricated on the same substrate. As a result, enhancement/depletion inverters consisting of the organic TFTs operated at supply voltages of 5 to 15 V.

Flexible solution-processed high-voltage organic thin film transistor

Abstract

Surface properties of SiO2 with and without H2O2 treatment as gate dielectrics for pentacene thin-film transistor applications

The effect of H2O2 treatment on the surface properties of SiO2 is studied. H2O2 treatment leads to the formation of Si(OH)x at the SiO2 surface that serves to reduce the number of trap states, inducing the shift of the Fermi level toward the conduction band minimum. H2O2 treatment also leads to a noticeable reduction in the value of the SiO2 capacitance per unit area. The effect of SiO2 layers with H2O2 treatment on the behavior of carrier transports for the pentacene/SiO2–based organic thin-film transistor (OTFT) is also studied. Experimental identification confirms that the shift of the threshold voltage towards negative gate-source voltages is due to the reduced number of trap states in SiO2 near the pentacene/SiO2 interface. The existence of a hydrogenated layer between pentacene and SiO2 leads to a change in the pentacene-SiO2 interaction, increasing the value of the carrier mobility.

The effect of indirect UV/ozone treatment on pentacene thin film transistors with double-stacked organic gate insulators

Abstract We investigated the indirect UV/ozone treatment, which means treating the insulator surface under tens of nanometers, rather than the direct surface of the insulator. The double-stacked organic layers are used as gate insulator and the UV/ozone treatment is conducted between these two layers. We analyzed the surface morphologies of the gate insulator and the pentacene by atomic force microscopy (AFM) to confirm the effect of indirect UV/ozone treatment. The UV/ozone treatment reduced the surface roughness of the upper side gate insulator and increased the pentacene grain size. Pentacene-based thin film transistors were fabricated and the electrical property improvement after this treatment was examined. The largest improvement was found when the UV/ozone treatment time is 10 min and the upper side gate insulator thickness is 20 nm, and the mobility at that condition is 1.21 cm2/V s, which is larger than three times that without UV/ozone treatment (0.33 cm2/V s).

Surface Treatments of Poly(4-Vinyl Phenol) Insulator for High-Performance Pentacene Thin-Film Transistors

We herein demonstrate a method for reducing the surface energy in polymer insulators for high-performance organic thin-film transistors (OTFTs). The surface energy of the poly(4-vinyl phenol) (PVP) insulator was reduced from 45 mJ/m2 to 32 mJ/m2 by treatment with UV/Ozone and octadecyltrichlorosilane (ODTS). The pentacene growth was controlled by the surface energy. It caused the pentacene film deposited on the ODTS-treated PVP insulator to induce three-dimensional growth, leading to an increase in the field-effect mobility of approximately 109%. These results demonstrate that the method of adjusting the surface energy in polymer insulators is suitable for enhancing the performance of OTFTs.

Relationship between initial and time-dependent cracks in charge transport of solution-processed organic thin-film transistor

ABSTRACTWe report on the comprehensive effect of initial and time-dependent crack on the charge transport of 6, 13-bis (triisopropylsilyethynyl) pentacene (TIPS-PEN) thin-film transistors (TFTs) upon exposure to air. Among the two types of TIPS-PEN films, with and without initial thermal cracks, temporally generated cracks were found to be severely affected by the initial status of the thermal cracks upon air-exposure. After 12 months of air-exposure, the charge transport characteristics of TIPS-PEN TFTs with initial thermal cracks degraded up to 98%, while those without initial thermal cracks degraded only 88%. Based on our long-term experimental results, we conclude that the initial physical status of the cracks play a significant role in the growth of time-dependent cracks and the capability of charge transport in solution-processed TFTs.

Effects of oxygen plasma generated in magnetron sputtering of ruthenium oxide on pentacene thin film transistors

Effects of oxygen plasma generated in a sputtering process for deposition of electrodes on pentacene thin films to configure top-contact (TC) transistors have been thoroughly investigated. Reactive oxygen species severely degraded electrical properties of pentacene films during the deposition of RuOx electrodes, leading to a failure of devices. In the off-region, the leakage current increased by about two orders of magnitude, and the subthreshold slope also increased by 6.5 times. The top surface of pentacene films was oxidized by oxygen plasma and C-O and C=O bonds awerere created. The pentacenequinone derivative was confirmed by X-ray photoelectron spectroscopy. The oxidation of pentacene films gives rise to charge traps at the pentacene/electrode interface, which produces a leakage channel between source and drain electrodes. We believe that this side effect of oxygen plasma on the fabrication of TC-devices should be considered carefully.

Bias stress effects in pentacene thin-film transistors with poly(methyl methacrylate) gate insulator

ABSTRACTWe demonstrated a bias stress effect on organic thin-film transistors (OTFTs) that causes device degradation, including a large shift in the threshold voltage and hysteresis in the transfer characteristics. Specifically, we analyzed the electrical characteristic variations in pentacene TFTs with a poly(methyl methacrylate) gate insulator under different bias stress conditions. We found that bias stress between the gate electrode and source/drain electrodes affects the charge transport properties, whereas bias stress between the source and drain electrodes influences the charge injection properties.

ポリシルセスキオキサンゲート絶縁膜の表面平坦化によるペンタセン薄膜トランジスタのキャリア移動度の向上

ポリシルセスキオキサンゲート絶縁膜の表面平坦化によるペンタセン薄膜トランジスタのキャリア移動度の向上

Two-step surface modification for bottom-contact structured pentacene thin-film transistors

We investigated surface treatment effects of hexamethyldisilazane (HMDS), poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) and l-cysteine on gold source/drain electrodes in bottom-contact structured pentacene thin-film transistors (TFTs). The treatment methods include spin coating and immersing. We have also researched on two-step treatment based on the combination of each treatment methods. The highest device performance was achieved by treating gold S/D electrodes with l-cysteine first and PEDOT:PSS afterwards, showing field effect mobility up to 0.35 cm2/V·s. l-cysteine can reduce the contact resistance between metal and semiconductor layer, and PEDOT:PSS acted as a hole transporting layer while HMDS decreased the surface energy, which enlarged the grain size of pentacene on it.

Surface-induced orientation of pentacene molecules and transport anisotropy on nanogroove SiO2 dielectric layer by simple scratched method: The study of surface roughness and molecular alignment on the mobility of organic thin film transistors

We obtained preferential in-plane molecular orientation and charge-transport anisotropy in pentacene thin-film transistors (TFTs) on conventional SiO2/Si substrates. The nanoscale SiO2 grooves with depths of 1–3 nm were prepared by a simple scratching process with diamond powder to create a new type of alignment template for inducing the aligned growth of pentacene with in-plane anisotropy. Results of atomic force microscopy and grazing-incidence X-ray diffraction showed that the nanogrooved SiO2 structure could control the alignment and growth mode of pentacene, and it remarkably decreased the grain size of the pentacene crystals. The charge-carrier mobility along the parallel axis of the nanogrooved structure (0.392 ± 0.039 cm2/(V·s)) was more than four-fold higher than that perpendicular to the alignment (0.104 ± 0.048 cm2/(V·s)). In addition, we investigated the effect of nanogrooved SiO2's surface roughness on the electrical properties of the pentacene TFT and found out that the surface roughness of SiO2 dielectric layer was more crucial factor on the device performance compared to the preferential alignment of the pentacene molecule.

Current‐Induced Joule Heating and Electrical Field Effects in Low Temperature Measurements on TIPS Pentacene Thin Film Transistors

The channel temperature (Tch) of solution‐processed 6,13‐bis(triisopropylsilylethynyl)‐pentacene (TIPS pentacene) thin film transistors (TFTs) is closely monitored in real time during current–voltage (I–V) measurements carried out in a He exchange gas cryostat at various base temperatures (Tb) between 300 K and 20 K. This is done using a platinum (Pt) resistance temperature sensor embedded within the transistor channel. Under large gate (Vg) and source‐drain (Vds) voltage biases, an increase inTchis observed, the magnitude of which depends on the thermal conductivity of the substrate. The increase inTchis associated with a simultaneous increase in the transistor drain current (Id) and becomes particularly pronounced at cryogenicTb. These experimental observations are rationalized using a 1D theoretical model and are attributed to current‐induced Joule heating. However, even though the heating of the channel unquestionably plays an important role, the corresponding amount of increase inIdat cryogenicTband large voltage biases cannot be fully accounted for unless at low temperatures μTIPSis enhanced in the presence of strong electrical fields. Therefore it is concluded that theI–Vcharacteristics of TIPS pentacene TFTs at lowTband large voltage biases are a result of a complex interplay between current‐induced Joule heating and electrical field effects.

Heterojunction effect on contact resistance minimization in staggered pentacene thin-film transistors

The MoO3/pentacene heterojunction is demonstrated to be effective for reducing the contact resistance in staggered organic thin-film transistors. The heterojunction-induced doping is nondestructive and may form a top conducting channel close to the pentacene surface. Contact interface doping and channel doping both significantly reduced the contact resistance. The effect of channel doping was prominent at low gate bias values, which is ascribed to the negligible access resistance owing to the presence of the top channel. Interface doping and channel doping were combined to obtain a complete heterojunction, which exhibited minimized contact resistance for a wide range of gate bias values.

Improved Electrical Properties of Pentacene MIS Capacitor With OTS Modified Ta2O5Dielectric

Ta2O5 films of 200 nm thick with and without octadecyltrichlorosilane (OTS) surface modification were prepared and used as gate dielectrics to fabricate pentacene metal–insulator–semiconductor (MIS) capacitors. The dielectric constants of Ta2O5 film and OTS-treated Ta2O5 film were determined to be 20.6 and 19.3 at 1 MHz, and both the films exhibit good permittivity stability and low leakage characteristics with the bias voltage sweeping from −10 to 10 V. Atomic force microscopy and Hall measurements show that a pentacene polycrystalline film deposited on OTS-treated Ta2O5 has a high grain packing density with an improved grain contact, and thus a high hole mobility of 3.5 cm2/Vs. Capacitance–voltage and conductance–voltage analysis of pentacene MIS capacitors demonstrate that OTS modification induces a positive shift of flatband voltage from 3.1 to 3.8 V, and effectively minimizes the interface state density of pentacene/dielectric from $5.1\times 10^{12}$ cm $^{-2}$ eV $^{-1}$ to $9.6\times 10^{10}$ cm $^{-2}$ eV $^{-1}$ . The results indicate that high- ${k}$ Ta2O5 film with OTS modification would be a promising gate dielectric for pentacene thin-film transistors in low-end electronics.

(Invited) Electrical and Structural Origin of Self-Healing Phenomena in Pentacene Thin Film Transistors

Despite the great potential for flexible large-area applications in organic electronics, electrical and structural instabilities have been widely regarded as an unavoidable weakness of organic semiconductors. Electronic components made of organic molecules are considered more fragile and sensitive to external conditions than their inorganic counterparts and the lifetime of them is shorter than that of conventional devices. Despite these shortcuts it is even more surprising that organic field-effect transistors (FETs) can undergo a self-healing process, i.e. their electrical characteristics can counter-intuitively improve over time, due to the unstable nature of weakly bound molecules. This remarkable phenomenon has never been understood completely. In this work, we demonstrate that the self-healing in pentacene FETs is induced by a structural phase transformation and can be triggered by various extrinsic or intrinsic influences. We evaluate in detail the necessary conditions for electrical self-healing in pentacene FETs and reveal the structure-property relation at the heart of this phenomenon: a structural phase transformation from the metastable monolayer phase to the so called “thin film phase”. The transformation basically involves a tilt of the molecules against the surface normal near both interfaces of pentacene thin films (pentacene-dielectric and metal-pentacene) and has a profound influence on the electronic properties of pentacene FETs, which we demonstrate by way of electronic structure calculations using DFT and semi-classical transport theory. Finally, possible external triggers able to initiate the self-healing process are discussed. A case study adopting various fabrication procedures reveals that external triggers such as nitrogen gas or other organic compounds seem to be necessary to initiate the self-healing process.

Ultra-Thin Flexible Electronics with the Enhancement Inverter Based-on Pentacene Thin Film Transistor

Thin film technology is advancing the research on fully flexible system for new applications in various fields, such as electronics, sensors and energy harvesting. In particular, thin film transistor (TFT) based flexible circuits have been studied for diagnostic devices, solar-cells, and flexible display. Although many companies and research groups have presented semi-flexible devices; a fully flexible system has not shown the sufficient result in terms of mechanical and electrical performance. Recently, inorganic-organic hybrid type TFTs have been developed and it shows the useful performance. However, the devices show limited performance at extremely small bending radius (< 1mm). In order to overcome the limitations, many researchers have suggested various solutions such as new materials of high mechanical strength, neutral strain position fabrication and ultra-thin substrates. Among these solutions, ultra-thin substrate is promising in the field of smart-skin, implantable device and patch-type biosensor. Depending on the decreasing substrate thickness, the strain strength also decreases dramatically. In this study, we demonstrate a nm-level ultra-thin device based on pentacene TFT, using de-bonding-technology. For de-bonding, a double layer of PVA and PAA based water soluble release layer was spin coated on the glass substrate. Subsequently, we coated the buffer layer on the release layer. The Al as gate electrode was deposited on the buffer layer by thermal evaporation. PMMA was then spin-coated and baked at 100 °C for 30 min. The pentacene and gold layer was deposited using thermal evaporation. CYTOP material was used for the passivation of the device. Finally, the device was de-bonded in double deionized water followed by curing at 75 °C for 30 min. Based on this process, we fabricated the nm-level thick TFT and enhancement inverter. After de-bonding process, the nm-level ultra-thin device showed good performance compared with the initial device before de-bonding.

Controlling of DOS of TFTs based 6,13-bis(triisopropylsilylethynyl) pentacene by solar light illumination

The effect of dipole layer and white light illumination on the density of states for the 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) thin film transistor were investigated. We developed a physical compact model based on variable range hopping (VRH) theory for expressing the DOS in OTFTs that takes into account the effects of dipole layer and white light illumination. Using this model, we explain that the DOS for TIPS-pentacene thin film transistor depend strongly on the white light illumination under the surface dipole effect. Finally, an analytical model of drain-current has been developed in order to reproduce the output and transfer characteristics curves of 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) phototransistor in saturation regime.

Spontaneously Formed Wrinkled Substrates for Stretchable Electronics Using Intrinsically Rigid Materials

The preparation of a stretchable substrate was carried out by blending poly (ethylene glycol)-block-poly (propylene glycol)-block-poly(ethylene glycol) and polydimethylsiloxane (PDMS) to enhance the stretchability and the surface energy of the elastic film. The deposition of a thin parylene film on this modified PDMS led to the formation of a spontaneously wrinkled surface, resulting in a highly stretchable substrate. Rigid Au conductors were deposited on the resultant wrinkles substrates, and could be stretched up to 20% strain. In addition, stretchable pentacene thin-film transistors were successfully fabricated on the wrinkled substrate without the formation of stiff islands.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.