By conducting C-V profile measurement, we analyzed the charge transport behavior in polycrystalline pentacene OTFTs. We found that carrier accumulation and depletion processes in the semiconductor channel layer is caused by a trap and de-trap mechanism. We apply such processes to explain C-V profiles at various gate voltages, ramp rates and sweep directions. At faster ramp rates, hysteresis can be observed from C-V profile. The phenomenon can be attributed to the asymmetry of the relaxation time of carrier trap and detrap mechanism. At the slower ramp rate, most carriers are able to interact with the gate stress, so the hysteresis disappears. And beyond this ramp rate, the corresponding threshold voltages are then kept at constant values, despite the existence of traps. Furthermore, low-mobility mobile ions or impurities participate in the charge accumulation and depletion when the ramp rate is much slower, which results in a skew of C-V profiles.
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